Forming via Holes in a Multilevel Substrate in a Single Step

1. Field of the Invention

The invention relates to the fabrication of multilevel electrical interconnects, and more particularly to a method of forming via holes between the top of a dielectric layer and various levels of underlying metallization prior to filling the via holes with a conductive material.

2. Description of Related Art

Current multi-chip circuitry design requires the attachment of numerous integrated circuit chips to high density electrical interconnects, also known as high density multi-chip-modules (MCMs) or as substrates. Substrates normally include surface pads for bonding to surface mounted chips, a dielectric, and electrical lines buried in the dielectric for connecting selected pads to provide electrical routing between various bond sites on the chips. It is common to use copper for the buried lines and a polymer such as polyimide for the dielectric. The copper lines may form separate layers of orthogonal wiring sets. It then becomes necessary to interconnect the copper lines to each other and/or the surface pads. This can be done by either staggered or stacked metallization (or metal vias). Staggered via designs normally result in lower interconnect density than stacked vias. Stacked vias, such as vertical metal pillars residing in vertical via holes, may be built either additively or subtractively. Additive construction involves building up pillars over an underlying base and depositing dielectric around the pillars. The subtractive approach, to which the present invention is directed, works in the opposite direction. Via holes are formed or etched in a dielectric and metal is deposited in the via holes.

Needless to say, one of the most important factors in the viability of any high density multilayer substrate is fabrication cost. Cost is roughly determined by the number of fabrication steps. More fabrication steps typically increase labor and material costs as well as decrease yields. Thus, any mature process which reduces the number of steps required to produce an equivalent substrate is useful and valuable.

Other methods have been developed in order to efficiently form via holes in a dielectric. The main thrust has been layer-by-layer. That is, for each layer with a dielectric over metal lines, via holes are formed in that layer before the next layer is constructed. In this manner, a separate step for forming via holes becomes necessary for each layer. See Levinson et al., "High Density Interconnects Using Laser Lithography," ISHM '88 Proc., 1988, pp. 301-306; and U.S. Pat. No. 4,897,153 to Cole et al. For instance, fabricating a four layer substrate (with a power plane, ground plane, X-conductors and Y-conductors) normally requires four separate steps (one for each layer) just to form the via holes. Therefore, the related art does not teach how to reduce the number of steps required to form via holes in each layer of a multilayer structure as additional layers are added.

The present invention addresses the previously described problems by providing a method of forming via holes through each layer of a multilayer structure in a single step. The present invention is described primarily in terms of copper/polymer substrates with buried conductive lines for interconnecting surface mounted integrated circuit chips. However, it is understood that the invention has more general utility, particularly for printed circuit boards, printed wiring boards, integrated circuit chips and other structures used for electrically connecting separate electronic components, or connecting separate regions of individual electronic components.

An object of the present invention is to form via holes in a multilayer structure in a single step, independent of the number of layers. The via holes can be formed individually by laser drilling, or formed concurrently by applying a dry etch through a patterned mask.

Another object of the present invention is to provide vertical metal pillars which connect metal lines in various layers of an interconnect substrate in a minimal number of process steps.

A feature in accordance with one aspect of the present invention includes disposing over a base a first layer comprising first metal lines beneath a first dielectric, disposing over the first layer a second layer comprising second metal lines beneath a second dielectric such that a portion of each first metal line is not beneath any second metal line, and forming via holes which extend through the second dielectric to the second metal lines and through the second dielectric and the first dielectric to said portions of the first metal lines.

Advantages of the present invention include the reduction of fabrication steps and costs, quick turnaround, improved yield, and improved planarization of polymer dielectrics. Furthermore, all of the process steps in the present invention have been demonstrated.

These and other objects, features and advantages of the present invention will be more readily apparent from a review of the detailed description and preferred embodiments which follow.

The following detailed description of the preferred embodiments can best be understood when read in conjunction with the following drawings, wherein:

FIG. 1 shows a fragmentary elevational view in cross-section of a layer of metal on a base,

FIG. 2 shows a fragmentary elevational view in cross-section of a patterned resist mask on the metal,

FIG. 3 shows a fragmentary elevational view in cross-section of the exposed metal etched to form first metal lines,

FIG. 4 shows a fragmentary elevational view in cross-section of a dielectric deposited over the first metal lines to form a first layer,

FIG. 5 shows a fragmentary elevational view in cross-section of a multilayer substrate containing three additional layers stacked on the first layer, wherein a portion of a metal line in each layer is uncovered by any other metal lines,

FIG. 6 shows a fragmentary elevational view in cross-section of via holes formed above the exposed portions of the metal lines in each layer in accordance with a laser drilling embodiment,

FIGS. 6A-6F show fragmentary elevational views in cross-section of via holes formed above the exposed portions of the metal lines in each layer in accordance with a reactive ion etching through a patterned mask embodiment,

FIG. 7 shows a fragmentary elevational view in cross-section of a conductive via metal deposited into the via holes and over the dielectric,

FIG. 8 shows a fragmentary elevational view in cross-section of a patterned resist mask over the substrate,

FIG. 9 shows a fragmentary elevational view in cross-section of patterned routing metallization over the substrate, and

FIG. 10 shows a fragmentary elevational view in cross-section of another multilayer structure which includes an integrated circuit chip in the base .

The first step of the present invention is to construct a multi-layer structure (with at least two layers) wherein each layer contains an electrically conductive line beneath a dielectric. This can be performed by many standard techniques well known in the art. For instance, separate layers can be inexpensively formed from lamination but the dielectric constant may be high. Or a layer of copper can be deposited on a base and selectively etched, as described in U.S. Pat. No. 4,810,332 to Pan and U.S. Pat. No. 5,011,580 to Pan et al. which are incorporated by reference. This approach will now be described.

Referring now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views and, more particularly to FIG. 1, there is shown a multilayer electrical interconnect substrate generally designated 10 according to a particularly preferred exemplification of the invention. Base 12 is shown as a ceramic such as alumina ceramic or glass ceramic, however, it is understood that base 12 can be a dielectric, a conductor, an electronic component (e.g., integrated circuit chip), or a preceding layer of a multilayer structure. Base 12 may require appropriate surface preparation, such as polishing, cleaning, etching, or roughening to assure acceptable contamination removal and/or surface finish. For example, it may be advantageous to roughen a copper/polymer base by plasma cleaning, or to smoothen a ceramic, plastic, or metal base by polishing. For illustration purposes, base 12 is a planarized alumina ceramic. A trilayer 13 is then evaporated on base 12. The trilayer consists of 500 angstroms chromium 14 on base 12, 5 microns copper 16 on the chromium, and 500 angstroms titanium 18 on the copper. Chromium 14 provides adhesion, copper 16 provides a first set of horizontal electrically conductive lines, and titanium 18 provides protection for the copper against oxidation and corrosion. More generally, tantalum, chromium and titanium each make useful adhesive or protective layer metals. Evaporation is preferred over sputtering which, due to the relatively slow deposition rate (e.g., 200-300 angstroms per minute), normally employs a subsequent plating step to form the bulk of the copper 16.

With reference now to FIG. 2, a layer of photoresist 20 is deposited on titanium 18 and patterned as is conventional.

In FIG. 3 the exposed trilayer 13 is wet etched by suitable chemical etchants. The etchants may also undercut (not shown) the edges of trilayer 13 beneath resist 20. In fact, isotropic wet etching is unsuitable where the desired metal pattern has a high aspect ratio and a very high pitch. Instead, the conductive lines could be pattern plated either electrolytically or electrolessly. Nonetheless, disposing the first metal lines on the base by wet etching a blanket layer, as illustrated hereafter, normally requires fewer process steps than pattern plating.

Referring now to FIG. 4, resist 20 is stripped and a first dielectric is disposed or coated over the first metal lines. Suitable dielectrics include inorganic materials such as silicon oxide, aluminum oxide and aluminum nitride. Inorganic dielectrics are particularly well suited for aluminum lines. The dielectric can also be an organic material such as a polymer. Preferably, a dielectric layer of polymer is provided from plasma polymerization of a silicone monomer or some hydrocarbon-rich monomer. These monomers can be subjected to plasma conditions and polymerized to form thin polymer films with low dielectric constants (e.g., 2.1) and good adhesion to copper. Suitable monomer dielectrics include benzocyclobutene (BCB), divinyly dimethylsiloxane, dihydrodimethyliloxane and their admixtures. The plasma can have not only a monomer fed into the chamber, but also a carrier gas such as argon, helium or neon. Another reactive gas such as oxygen, nitrogen, methane, carbon monoxide and carbon dioxide can also be added to modify the film properties. Graded thin film properties can also be generated by changing the composition/type of the gases/vapors fed into the plasma chamber as a function of time. This enables one or both sides of the film to have good adhesion to copper while assuring the bulk of the film has good electrical properties. Furthermore, a plasma deposition system can be used as a resist ashing system as well as a polymer etch-back to avoid leakage due to chromium diffused into the polymer. Alternatively to plasma polymerization, spin-on polymers such as polyimide can be used but then additional steps such as resist strip and etchback might be necessitated. Furthermore, polyimide has a dielectric constant typically in the range of 3.5 to 3.8. This presents a drawback in comparison to plasma polymerized polymers (2.1) since smaller dielectric constants require smaller interlayer dielectric thickness to maintain a constant characteristic impedance, such as 50 ohms. For illustration purposes, a 12 micron layer of plasma deposited polymer 24 is disposed over ceramic 12 and copper lines 16. The top surface of polymer 24 may be planarized by polishing, however, polymer 24 may already be fairly planar due to its larger thickness (12 microns) than copper lines 16 (5 microns). This provides a first signal layer 22 which contains copper lines 16 beneath polymer 24.

With reference now to FIG. 5, the aforementioned steps are repeated to fabricate three additional signal layers on substrate 10. As may be seen, second layer 26 containing copper lines 28 and polymer 30 is deposited on polymer 24, third layer 32 containing copper lines 34 and polymer 36 is deposited on polymer 30, and fourth layer 38 containing copper lines 40 and polymer 42 is deposited on polymer 36. Copper lines 28, 34 and 40 are preferably sandwiched in metal trilayers similar to trilayer 13 for copper lines 16. It is critical to note, however, that at least a portion of copper lines 16, 28, 34 and 40 is not covered by any copper line in a higher layer. In other words, portion 44 of copper lines 16 is not beneath any of copper lines 28, 34 or 40, portion 46 of copper lines 28 is not beneath any of copper lines 34 or 40, portion 48 of copper lines 34 is not beneath any copper lines 40, and no copper lines are above copper lines 40. This arrangement of conductive lines is at the heart of the present invention. It assures that vertical via holes originating at the top dielectric surface 50 and formed solely through dielectric material can reach and expose conductive lines in each layer. That is, a portion of a conductive line in each layer is not "blocked" from the upper substrate surface by any conductive lines in higher layers. As a result, every via hole in substrate 10 can be formed after the uppermost layer is deposited. There is no need to form vias layer-by-layer as the layers are stacked.

The next step of the present invention is to form the via holes from the top dielectric surface to conductive lines within each layer in a single step. It is essential to the present invention that the source which attacks the dielectric to form or etch the via holes is incapable of altering the conductive lines to any significant degree. In other words, the dielectric and conductive lines must have sufficiently different physical properties to assure that the conductive lines act as a barrier or etch stop to whatever is forming the via holes in the dielectric. This assures that the via holes extend downward vertically to expose the first underlying conductive line, but no further. Numerous approaches for forming or etching via holes in dielectrics are known to those having skill in the art. Several will be described.

Referring now to FIG. 6, a plurality of vertical through-holes or via holes are formed through dielectric layers of the substrate. "Vertical" via holes, as used herein, includes via holes with not only 90 degree sidewalls, but also substantially vertical sidewalls which taper slightly inwardly, such as 2.degree. to 5.degree., thereby causing the via hole diameter to decrease slightly with increasing depth. Via holes "through" a dielectric layer, as used herein, includes not only holes extending from the top to the bottom of a dielectric layer, but also holes extending from the top of a dielectric layer to a copper metal line inside the layer, as will be clear from the context. As may be seen, via holes 52 are formed through polymer layers 42, 36, 30 and 14 to expose portions 44 of copper lines 16. Likewise, via holes 54 are formed through polymer layers 42, 36 and 30 to expose portions 46 of copper lines 28, via holes 56 are formed through polymer layers 42 and 36 to expose portions 48 of copper lines 34, and via holes 58 are formed through polymer layer 42 to expose portions 49 of copper lines 40. For illustration purposes, the via holes are anisotropically formed one at a time by laser drilling, such as with a CO.sub.2 or Nd:YAG laser, preferably an excimer laser. The use of an excimer laser to remove selected regions of materials by photoablation is well known in the art. This is termed "ablative photodecomposition" (APD) and requires high powered pulsed laser beams. For instance, U.S. Pat. No. 4,414,059 describes an APD process in which ultraviolet radiation of wavelengths less than 220 nm cause fragmentation of resist polymer chains and the immediate escape of the fragmented portions from the resist layer. In effect, the incident energy is transferred to kinetic energy in rapid and large amounts of bond breaking whereby polymer chains are fragmented and explode-off as volatile by-products. The copper lines, however, must not ablate or be otherwise deformed by the laser beam to any significant degree.

Referring now to FIGS. 6A-6F, another etching technique for forming the via holes is set forth. An anisotropic (vertical) dry etch is applied through a patterned mask to avoid the isotropic undercutting typical to wet chemical etchants. As seen in FIG. 6A etch mask 60 is seen as a blanket layer of chromium deposited on polymer 42. Suitable metals for the etch mask further include copper, aluminum, chromium and tungsten. A copper etch mask may comprise a trilayer similar to trilayer 13. In FIG. 6B a resist mask 62 is deposited on etch mask 60 and selectively patterned. In FIG. 6C the exposed regions of etch mask 60 are removed by wet chemical etching. In FIG. 6D the photoresist 62 is stripped. In FIG. 6E a dry etch is applied to concurrently form the via holes 52, 54, 56 and 58 in a single etching step. A reactive ion etch is preferred, although plasma etching is also suitable. Whatever dry etch is used must not deform copper lines 16, 28, 34 or 40 to any appreciable degree, but rather must be vertically blocked upon reaching and exposing any copper. It should be noted that a metal line may only partially block the dry etch. For instance, copper line portion 65 is seen to only partially underlay mask opening 66 and thus unblocked region 68 under mask opening 66 is etched below portion 65. Finally, in FIG. 6F etch mask 60 is stripped.

The use of a patterned mask is not limited to dry etching. For instance (not shown), the substrate could be exposed to ultraviolet radiation from a scanning excimer laser through a metal mask, such as chromium on glass, with openings in the desired locations. This presents a tradeoff between a using patterned mask and laser drilling the vias one-by-one: with a patterned mask the via holes are formed concurrently instead of one at a time, greatly increasing throughput, however, several additional processing steps are required to utilize the mask. The choice may depend on the number of via holes desired. But in the event an inorganic dielectric is used, reactive ion etching would be preferred over laser drilling.

With reference now to FIG. 7, the via holes can now be filled with an electrically conductive material such as an appropriate metal. Suitable deposition techniques for metals include electrolytic, electroless, and most preferably chemical vapor deposition of copper, tungsten, nickel or nickel alloys. Chemical vapor deposition is particularly well suited for simultaneously filling via holes with similar diameters and high aspect ratios. Using electrolytic or electroless deposition, the via holes with shorter depths may fill sooner than deeper via holes, necessitating the additional step of planarizing the surface. However, filling the via holes with a thin layer of heavily biased sputtered titanium/copper/chromium, or chemical vapor deposited titanium and copper, may provide an electrolytic initiator throughout the via holes, equalize the plating times, and reduce the need for planarization. Furthermore, plating tends to have greater throughput than chemical vapor deposition. Returning to the example, any protective titanium above copper lines 16, 28, 34 and 40 is removed. Then a blanket layer of copper via metal 70 is deposited by low pressure chemical vapor deposition into via holes 52, 54, 56 and 58. Although the via holes are shown completely filled, if desired metal 70 may only partially fill the via holes.

Referring now to FIG. 8, a second photoresist mask 72 is patterned over copper 70.

With reference now to FIG. 9, the exposed copper 70 above polymer 42 is wet etched and second mask 72 is stripped. The unetched copper 70 above polymer 42 serves as routing metal 74. It is important to note that conductive paths can be formed between copper lines 16, 28, 34 and 40 in two ways. First, the routing metal 74 above top dielectric layer 42 can connect metal in separate via holes which extend to conductive lines in different signal layers. For instance, routing metal 74 connects copper 75 in via hole 76 to copper 77 in via hole 78, thereby forming a continuous conductive metal path between copper lines 80 and 82. Secondly, the conductive lines can be designed so that a conductive line in an upper level is exposed by and blocks only a portion of a via hole, and the unblocked portion of the via hole vertically extends downward to expose another conductive line in a lower layer. Filling the via hole with metal thus provides a conductive path between the exposed portions of the conductive lines on the upper and lower levels. This allows connections to be made between signal layers without additional metal 74 as previously described, and therefore may save space and allow custom designs to be more efficient. For example, metal 84 in via hole 86 provides a conduction path between copper lines 88, 90, 92 and 94. More generally, a preferred wiring configuration for customizable high density copper/polyimide substrates is disclosed in European Patent Application 88308996.3 entitled "Customizable Circuitry."

Those skilled in the art will recognize that many other processes are well suited to acheive the results from FIGS. 8 and 9. For example, metal 70 above upper polymer layer 42 can be planarized and removed by polishing, and then routing metal 74 can be electrolessly deposited on and between copper via metals 75 and 77.

Referring now to FIG. 10, it is important to note that the present invention can also provide via holes for interconnecting various terminals of electronic components. As may be seen in another multilayer structure, base 96 includes integrated circuit chips 98 with aluminum bonding pads 100 in alumina frame 102. Chips 98 and frame 102 are coated by kapton layer 104. Pads 106 and 108 are connected to metal deposited in via holes and linked by a conductive path comprising via metals 110, 112 and reroute metal 114.

The present invention, therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned, as well as others inherent therein. While presently preferred embodiments of the present invention have been described for the purpose of disclosure, numerous other changes and modifications in the details of construction, arrangement of parts and steps of processing can be carried out without departing from the spirit of the invention which is intended to be limited only by the scope of the appended claims.