Dynamic Semiconductor Memory Device for Raising Voltage Level of a Word Line

1. Field of the Invention

The present invention relates to dynamic memory devices and, more specifically, to a dynamic semiconductor memory device improved to raise voltage level of word lines.

2. Description of the Background Art

Recently, in order to meet the demand of microelectronics implementation of various devices in industry and in civil equipments, VLSIs (Very Large Scale Integrated circuits) having larger scale than LSIs (Large Scale Integrated circuits) have been developed and come to be commercially used.

FIG. 6 is a block diagram of a dynamic RAM (Random Access Memory) formed of such a LSI or VLSI. Referring to FIG. 6, the dynamic RAM includes a memory array 1, a word line driving signal generating circuit 2 for generating a signal R.sub.X for driving word lines WL included in the memory array 1, and a word line boost circuit 3 for boosting the word line driving signal R.sub.X. The word line driving signal generating circuit 2 is connected to receive a RAS (Row Address Strobe) signal through a RAS buffer 4. A row decoder 1a, a sense amplifier 1b, a column decoder 1c and an I/O gate 1d are connected to the memory array 1. The dynamic RAM is accessed by row address signals.multidot.column address signals output from an address buffer 5 to the memory array 1.

The operation will be described in the following.

Generally, the dynamic RAM receives time sequentially the row and column address signals through terminals A0 to A9. First, the respective address signals are input at an edge timing at which the RAS signal and a CAS (Column Address Strobe) signal from the CAS buffer 6 fall, respectively. Then a word line is selected by the row address signal, and by a word line driving signal R.sub.XB which has been boosted, the word line is activated. A bit line is selected by the column address signal. Consequently, in reading operation, a signal stored in the memory cell is applied to the bit line. The signal applied to the bit line is output through the I/O gate 1d.fwdarw.output buffer 7.fwdarw.data output terminal Dout. In writing, in response to a write enable signal WE from a write buffer 8, input data is applied to the memory cell through the data input terminal Din.fwdarw.input buffer 9.fwdarw.I/O gate 1d.

FIG. 7 is a block diagram showing the memory cell, the row decoder and the boost circuit. Referring to FIG. 7, the memory cell MC includes a capacitor C.sub.S and a switching transistor Q.sub.M connected to the word line WL and to the bit line BL. By applying a voltage of high level "1" or low level "0" to the capacitor C.sub.S, a signal is stored. When the word line WL is activated, the transistor Q.sub.M is turned on. When the transistor Q.sub.M is turned on, the charges stored in the capacitor C.sub.S are applied to the bit line BL which has been at a floating state. The stray capacitance of the bit line BL is about ten times the capacitance of the capacitor C.sub.S. Therefore, a potential change as small as about several hundred milli-volts appears on the bit line BL. The potential change is amplified by a sense amplifier 1b and is applied to the I/O gate 1d for reading/writing.

By the above described series of operations, a signal from a designated memory cell MC of the plurality of memory cells MCs of the memory array 1 is applied through the I/O gate 1d to the output buffer 7. In writing, in response to a write enable signal WE, the write buffer 8 drives an input buffer 9, and data applied through the input buffer 9 is written through the I/O gate to the memory cell MC.

The word line boost circuit will be described in the following.

When the word line WL is changed to the high level, the transistor Q.sub.M is turned on. If this high level is the supply voltage level V.sub.cc, the high storage level is reduced by the threshold voltage V.sub.TH of the transistor Q.sub.M. The ratio of this loss is normally about 20%, which is not so high as to immediately cause malfunction. However, if the supply voltage level becomes lower, the loss becomes greater comparatively, reducing operation margin. The word line boost circuit is used to solve this problem. This circuit serves to raise the voltage level of the word line to be higher than the sum of the supply voltage level V.sub.cc and the threshold value V.sub.TH of the transistor Q.sub.M. The word line boost circuit 3 of FIG. 7 attains this object. The word line boost circuit 3 includes a charge line 31 for charging the word line WL, a delay circuit 32 connected to receive the word line driving circuit R.sub.X, and a boosting capacitor 33 connected between the charge line 31 and the output of the delay circuit 32.

FIG. 8 is a timing diagram illustrating the operation of the word line boost circuit 3 shown in FIG. 7.

Referring to FIGS. 7 and 8, the operation of the word line boost circuit 3 will be described. At time T0, the word line driving signal R.sub.X changes to the high level. The output signal R.sub.XB is delayed by the delay circuit 32 and changes to the high level at time T1. Consequently, the voltage level of the output signal R.sub.XB is raised to a level V.sub.cc +V.alpha. due to the capacitance coupling of the capacitor 33, which level is higher than the supply voltage level V.sub.cc. By appropriately setting the capacitance value of the capacitor 33, V.alpha. is made higher than the threshold voltage V.sub.TH of the transistor Q.sub.M. In this manner, the word line driving signal R.sub.X is boosted, providing the boosted word line driving signal R.sub.XB. The high level signal R.sub.XB is output from an output which is in a floating state, separated from the power supply. The boosted word line driving signal R.sub.XB is applied to the memory array 1 though the row decoder 1a, and activates the word line WL selected by the row decoder 1a.

Returning to FIG. 7, the row decoder will be described. Referring to FIG. 7, the row decoder 1a includes a plurality of unit row decoders RD each for activating one of a plurality of rows. For the simplicity of description, a row decoder for one row is shown. The unit row decoder RD includes an NAND gate 11 connected to receive row decoder address signals RA1 to RA9, an inverter 12 connected to the output thereof, and three N channel transistors Q.sub.AK, Q.sub.BK and Q.sub.CK.

In operation, when this unit row decoder RD is selected, for example, the row address signals RA0 to RA9 are set to high level, and the NAND gate 11 outputs a low level signal. This signal is inverted by the inverter 12 and applied to the gate of the transistor Q.sub.BK and to the gate of the transistor Q.sub.CK. Consequently, the transistor Q.sub.BK is turned on, and the boosted word line driving signal R.sub.XB is applied to the word line WL.sub.K through the transistor Q.sub.BK.

However, in the conventional word line boost circuit 3, when there is a leak in the capacitor 33, the level of the word line driving signal R.sub.XB gradually lowers, as shown in FIG. 9. Especially when the RAS signal has a long period (longer than several ten .mu.sec), the level of the boosted word line driving signal R.sub.XB becomes too low to activate the word line WL. Therefore, when the write enable signal WE falls to write new data to the memory cell MC near the end of the period of the RAS signal, the channel of the transistor Q.sub.M is not perfectly formed, since the level of the word becomes very low. Therefore, data can not be written to the memory cell. In other words, the conventional boost circuit has small write margin.

Therefore, an object of the present invention is to provide a dynamic semiconductor memory device enabling larger write margin and to provide a method of boosting level of a word line.

Another object of the present invention is, in a dynamic semiconductor memory device, not to lower level of the word line in writing.

A further object of the present invention is, in a dynamic semiconductor memory device, to surely effect writing, even if a row address strove signal has a long period.

Briefly, the dynamic semiconductor memory device in accordance with the present invention includes memory cells arranged at crossings of a plurality of word lines and a plurality of bit lines, and a memory array including at least one of said memory cells. The dynamic semiconductor memory device further includes a row address strobe buffer, an address buffer, a write buffer, a word line driving signal generating circuit, a first word line boost circuit, a second word line boost circuit, and a row decoder. The row address strobe buffer receives an external row address strobe signal for controlling state of storage of the dynamic RAM. The write buffer receives an external write enable signal. The address buffer receives an external address signal for addressing the dynamic RAM. The word line driving signal generating circuit sets the word line to the supply voltage, in response to the row address strove signal input through the row address strobe buffer. The first word line boost circuit raises the level of the word line higher than the supply voltage. The second word line boost circuit raises again the level of the word line in response to the write enable signal. The row decoder is connected to the memory cell array, decodes the address signal from the address buffer, and supplies driving voltage which has been boosted by the second word line boost circuit to the word line corresponding to the address signal.

In operation, in response to a write signal applied from the write control signal input means, the word line boost circuit raises the level of the word line to be higher than the supply voltage in writing, and therefore, even if the level of the word line lowers due to a leak of the capacitor, writing can be effected.

Consequently, even if the level of the word line lowers during writing, the level of the word line can be raised again, and therefore the write margin can be enlarged.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a schematic diagram showing the details of the RAS buffer 4 of FIG. 1.

FIG. 3 shows details of the word line driving signal generating circuit.

FIG. 4 is a schematic diagram showing details of the first word line boost circuit, the second word line boost circuit and the memory array.

FIG. 5 is a diagram of waveforms for describing the word line boosting operation of the dynamic RAM shown in FIGS. 1 to 4.

FIG. 6 is a block diagram of a conventional dynamic RAM.

FIG. 7 is a schematic diagram showing the details of the conventional word line boost circuit and the memory array.

FIG. 8 is a diagram of waveforms for illustrating the operation of the word line boost circuit of FIG. 7.

FIG. 9 is a diagram of signal waveforms of various portions for describing the problems of the prior art.

FIG. 1 is a block diagram showing one embodiment of the present invention. Referring to the figure, different from the dynamic RAM of FIG. 6, a second word line boost circuit 50 is connected between the word line boost circuit 3 and the memory array 1, and internal write enable signals WE and WE are applied to the word line boost circuit 50 from the write buffer 8. The same or corresponding portions are denoted by the same reference characters as FIG. 6. The second word line boost circuit 50 raises again the word line boost signal R.sub.XB from the first word line boost circuit 3 again in response to the internal WE and WE signals from the write buffer 8, and applies this signal to the memory array 1.

FIG. 2 is a schematic diagram showing the details of the RAS buffer shown in FIG. 1. Referring to this figure, the RAS buffer 4 includes an N channel transistor 41 receiving an external RAS signal at its gate, an N channel transistor 42, a P channel transistor 43 supplying supply voltage to the drain of the transistor 41, and a plurality of inverters 44. In operation, in response to the external RAS signal, an internal RAS signal is output from the inverter 44 of the last stage, and an internal RAS signal is output from the second last inverter. The internal RAS and RAS signals output from the RAS buffer 4 are applied to the word line driving signal generating circuit 2.

FIG. 3 shows details of the word line driving signal generating circuit 2. The word line driving signal generating circuit 2 includes an NOR gate 21 receiving R.sub.AN and R.sub.AN for selecting a memory array from the address buffer 5; an NOR gate 24 receiving an output from the NOR gate 21 input through the inverters 20 and 23 and the external RAS signal; an inverter 25 inverting the output from the NOR gate 24 for generating a trigger signal R.sub.XT for generating a driving voltage; and a switching circuit 26 for generating the driving voltage R.sub.X based on the trigger signal R.sub.XT and on the internal RAS and RAS signals. The switching circuit 26 further includes a P channel transistor 27 and three N channel transistors 28, 29 and 30. In operation, the word line driving signal generating circuit 2 generates a trigger signal R.sub.XT for driving a desired word line of the memory array, in response to the signals R.sub.AN and R.sub.AN from the address buffer 5 and to the internal RAS signal. In response to the low level of the trigger signal R.sub.XT, the P channel transistor 27 is turned on. In response to a high level of the internal RAS signal, the N channel transistor 29 is turned on. Consequently, the output from the switching circuit 26 is raised to the supply voltage. Until the low level of the trigger signal R.sub.XT is input, the internal RAS signal is kept at the high level, and in response to this high level signal, the N channel transistor 30 is turned on. Consequently, the output from the switching circuit 26 is set to the low level. Namely, the N channel transistor 30 is in the standby state.

FIG. 4 shows connections between the first word line boost circuit 3, the second word line boost circuit 50 and the memory array 1 of FIG. 1. Referring to the figure, different from FIG. 7, the second word line boost circuit 50 is connected. The second word line boost circuit 50 includes an inverter 51 connected to an output of the delay circuit 32; an NOR gate 52 receiving the output from the inverter 51 and the internal WE signal; a transmission gate 53 connected to an output of the NOR gate 52; a capacitor 54 connected between the output of the transmission gate 53 and the charge line 31; and an N channel transistor 55 connected between the capacitor 54 and the ground terminal. The transmission gate 53 connects the output of the NOR gate 52 to the capacitor 54 in response to the internal WE and WE signals. FIG. 5 shows signal waveforms of the circuits in the dynamic RAM shown in FIGS. 1 to 4. Referring to the figure, the word line boosting operation of the dynamic RAM of the present embodiment will be described. The reference characters V.sub.N 1, V.sub.N 2 and V.sub.N 3 respectively represent the waveform of the output signal from the inverter 51, and the waveforms of the input/output signals of the transmission gate 53. When the external RAS signal is input, the RAS buffer 4 latches this signal, and provides internal RAS and RAS signals from the latched signal through the plurality of inverters 44. The internal RAS and RAS signals are applied to the word line driving signal generating circuit 2. In response to the RAS and RAS signals, the word line driving signal generating circuit 2 raises the charge line 31 to the supply voltage V.sub.cc. The charge line 31 is further raised to V.sub.cc +V.alpha. by the first word line boost circuit 3. The above operation is approximately the same as in the prior art.

Thereafter, in response to the external write enable signal WE, the write buffer 8 generates internal write enable signals WE and WE. The NOR gate 52 generates, based on the signals WE and WE and on the signal V.sub.N 1 from the inverter 51, a high level signal V.sub.N 2 only when the RAS signal is at the low level and the write enable signal WE is at the low level. The signal V.sub.N 2 is transmitted through the transmission gate 53 to the capacitor 54. Consequently, the capacitor 54 is charged, and the charge voltage V.beta. is applied to the charge line 31. Consequently, the word line driving signal R.sub.XB is raised to V.sub.cc +V.beta.. In this manner, the boosted word line driving signal R.sub.XB is transmitted through the N channel transistor Q.sub.BK of the row decoder 1a to the word line WL.sub.K.

Thus, the level of the desired word line can be raised again during writing operation.

When the external RAS signal is inverted to the high level, the high level internal RAS signal is applied to the gate of the N channel transistor 55 of the second word line boost circuit 50. The N channel transistor 55 turns on in response to the high level internal RAS signal, and the charges in the capacitor 54 flow to the ground. Consequently, the word line driving signal R.sub.XB attains to the low level.

Although a plurality of memory arrays are provided in this example, the number of the memory array may be one. When the number of the memory array is one, the NOR gate and the inverter of the word line driving signal generating circuit 2 can be omitted.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.