Single Ended to Fully Differential Converters

This invention relates to a single ended to fully differential conversion scheme incorporated into a fully differential switched capacitor integrator architecture resulting in an input to this architecture having a single ended signal instead of the heretofore required balanced fully differential input signal.

In recent years considerable interest has been shown in combining analog and digital circuits on a single semiconductor chip with particular importance to complementary metal oxide semiconductor (CMOS) analog circuits having very high performance, as required in analog to digital converters. The lack of desirable resistors in CMOS technology has led to increased development in switched capacitor techniques for replacing filters that have been conventionally constructed using discrete resistors, capacitors and inductors. In switched capacitor circuits resistors are replaced by switches and capacitors.

In the analog circuit technology two of the most important circuits are the analog to digital (A/D) converters and analog filters. Both of these types of circuits use a large number of switched capacitor circuits. For example, oversampled analog to digital converters have recently been found to be very useful in achieving high resolution conversion for low frequency signals. The oversampled A/D converters are inherently nonlinear systems which operate on the principle of oversampling and noise averaging. The principal building block of these systems is a fully differential switched capacitor integrator block. This fully differential switched capacitor integrator block is also the main building block of the switched capacitor filters.

In order to achieve high resolution, it is important to minimize noise contribution from power supplies and charge injection from switches. Since fully differential systems are inherently immune to supply noise and achieve a high common mode rejection ratio most high resolution switched capacitor applications use fully differential architecture. However, fully differential architectures require fully differential high gain amplifiers.

High gain fully differential amplifiers require common mode feedback circuitry to maintain the common mode level of output at a predetermined level. Thus, systems using common mode feedback circuitry require that the input differential signal be such that each of the input terminals for a fully differential system have signals applied thereto and these signals should be such that the signal V.sub.IN.sup.+ on the first of two input terminals be equal to the signal -V.sub.IN.sup.- on the second of the two input terminals. For instance, if the input signal V.sub.diff is a sine wave, then when the first half of the sine wave cycle is positive as applied to the first input terminal, the second input terminal should have a sine wave applied thereto with its first half being negative. Accordingly, the input signal

The use of switched capacitor circuits with differential amplifiers is disclosed in U.S. Pat. No. 4,896,156, filed on Oct. 3, 1988, No. 4,862,121, filed on Aug. 13, 1987, and U.S. Pat. No. 4,574,250, filed on Oct. 13, 1981.

The use of fully differential architectures in designing the high resolution A/D converters and filters provides very desirable results but it also provides the requirement that the input to these systems be a balanced signal around the common mode point of the system. This requirement is generally not compatible in systems where these parts are used. Thus, the choices normally available to the designer using these parts is to design signal conditioning circuitry to precede the high resolution converter on the board. This arrangement requires additional discrete components and very low noise and low distortion design of the signal conditioning circuit block which receives a single ended signal and provides a fully balanced output signal. Such a requirement not only drives the cost up but also places a very difficult requirement on the board designer who wants to design a 16-bit circuit if a 16-bit A/D converter has to be used. Thus, in view of the above mentioned issues, it becomes very important that the input to these high resolution systems be a single ended signal.

It is an object of this invention to provide a single ended to fully differential conversion scheme which can be incorporated into an architecture of a fully differential switched capacitor integrator without affecting the functionality of an integrator block, this block being the first block in a system such that it can perform single ended to fully differential conversion and integration simultaneously, and, if required, the block can also act only as a single ended to fully differential conversion block with scalable gain.

In accordance with the teachings of this invention, a single ended to fully differential converter is provided which has a single ended input signal and differential output signals, with the output signals applied directly to both first and second inputs of a differential amplifier using appropriate non-overlapping clock pulses to a plurality of switches, e.g., CMOS transistors, to couple the single ended input signal through a first capacitor to the first input of the differential amplifier and through a second capacitor to the second input of the differential amplifier. More specifically, the single ended input signal is applied across the first capacitor during a first period of time and to the second input of the differential amplifier during a second period of time through the second capacitor with the stored signal in the first capacitor also being applied to the first input of the differential amplifier during the second period of time.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.

FIG. 1 is a circuit diagram of a fully differential switched capacitor integrator or summation block known in the prior art,

FIG. 2 is a circuit diagram of a preferred embodiment of the present invention,

FIG. 3 is a graph indicating the clock pulses applied to the circuit of the invention illustrated in FIG. 2,

FIG. 4 is a circuit diagram of a preferred embodiment of the invention made in the CMOS technology, and

FIG. 5 is a graph indicating the clock pulses applied to the circuit of the invention illustrated in FIG. 4.

In order to more fully understand the teachings of the present invention, a basic fully differential integrator block, somewhat similar to that disclosed in the hereinabove cited U.S. Pat. No. 4,862,121, is illustrated in FIG. 1 of the drawings and discussed hereinbelow. The fully differential integrator block shown in FIG. 1 of the drawings is one of the most commonly used switched capacitor circuit designs. With the switches S9 and S10 open, this block acts as an integrator. This block may also be used as a gain element and as a summation block. Thus, this block forms the heart of many switched capacitor circuits.

Using the block of FIG. 1 as an integrator with switches S9 and S10 open, it can be seen that on clock phase A, as indicated in FIG. 3 of the drawings, an input signal V.sub.IN.sup.+ is sampled across capacitor C.sub.s.sup.+ with switches S1 and S3 closed and input signal V.sub.IN.sup.- is sampled across capacitor C.sub.s.sup.- with switches S5 and S7 closed. On non-overlapping clock phase B the charge on capacitors C.sub.s.sup.+ and C.sub.s.sup.- is transferred to integrating capacitors C.sub.i.sup.+ and C.sub.i.sup.-, respectively, with switches S2, S4, S6 and S8 closed.

The switched capacitor integrator block shown in FIG. 1 is a sampled data system and, thus, the Z-transform of the system function of this block with the clocking scheme indicated is

This arrangement performs the integration function with a positive gain and a unit delay. This same architecture when operated with a modified clocking scheme can perform the integration function with a negative gain and no delay. This modified clocking scheme is also indicated in FIG. 1 of the drawings wherein switches S3 and S5 are controlled by clock phase B (shown in parenthesis) instead of by clock phase A and switches S4 and S6 are controlled by clock phase A (shown in parenthesis) instead of clock phase B, with the other switches being controlled as indicated in FIG. 1. The Z-transform of this system using the modified clocking scheme is

This same architecture can be used as a simple gain block. When the clock signals are applied as specified for the integrator with a positive gain and a delay, clock phase A is applied to switches S9 and S10 of FIG. 1. Accordingly, when the input capacitor C.sub.s is being charged up with the input voltage V.sub.IN, at the same time the switches S9 and S10 are on across the capacitors C.sub.i.sup.+ and C.sub.i.sup.- so that these capacitors will be discharged. Thus, on clock phase B when the charge from the capacitor C.sub.s is transferred to the capacitor C.sub.i the output is simply a scaled version of the input signal, i.e.,

As indicated in FIG. 1, the input to the switched capacitor integrator block shown therein is a fully differential signal. Although the prior art circuit of FIG. 1 functions very satisfactorily, it does require a fully differential input signal, which as mentioned hereinabove requires the use of a single ended signal generator coupled to an off-chip signal conditioning circuit having a differential output and coupling the output of the signal conditioning circuit to an on-chip fully differential amplifier.

FIG. 2 of the drawings illustrates an architecture of a single ended to fully differential converter circuit incorporated into an integrator architecture having the addition of only four switches and a novel clocking scheme to provide single ended to fully differential conversion, in accordance with the teachings of the present invention. The converter shown in FIG. 2 does not require the use of a complex noise-generating off-chip signal conditioning circuit.

Referring to FIG. 2 of the drawings in more detail, it can be seen that the single ended to fully differential converter includes an integrating fully differential amplifier 10 having input terminals + and - and output terminals - and + and a first integrating capacitor C.sub.i.sup.+ connected between the output terminal - and the input terminal + of the amplifier 10, as well as a second integrating capacitor C.sub.i.sup.- connected between the output terminal + and the input terminal - of the amplifier 10. Output terminals of the single ended to fully differential converter are indicated at V.sub.O.sup.+ connected to the output terminal - of the amplifier 10 and at V.sub.O.sup.- connected to the output terminal + of the amplifier 10.

A single ended input signal terminal V.sub.IN is coupled to a first differential signal terminal V.sub.IN.sup.+ through a switch S11 and to a second differential signal terminal V.sub.IN.sup.- through a switch S12. A point of reference potential such as a ground terminal G is coupled to the first differential signal terminal V.sub.IN.sup.+ through a switch S13 and to the second differential signal terminal V.sub.IN.sup.+ through a switch S14. A switch S1 is connected between the first differential signal terminal V.sub.IN.sup.+ and a first plate P1 of a first storage capacitor C.sub.s.sup.+ and a switch S2 is connected between the first plate P1 of the first storage capacitor C.sub.s.sup.+ and a common mode voltage terminal V.sub.cm. A switch S3 is connected between a second plate P2 of the first storage capacitor C.sub.s.sup.+ and the common mode voltage terminal V.sub.cm and a switch S4 connects the second plate P2 of the first storage capacitor C.sub.s.sup.+ to the first input terminal + of the amplifier 10. A switch S7 is connected between the second differential signal terminal V.sub.IN.sup.- and a first plate P1 of a second storage capacitor C.sub.s.sup.- and a switch S8 is connected between the first plate P1 of the second storage capacitor C.sub.s.sup.- and the common mode voltage terminal V.sub.cm. A switch S5 is connected between a second plate P2 of the second storage capacitor C.sub.s.sup.- and the common mode voltage terminal V.sub.cm and a switch S6 connects the second plate P2 of the second storage capacitor C.sub.s.sup.- to the second input terminal - of the amplifier 10. Additionally, switches S9 and S10 connected across integrating capacitors C.sub.i.sup.+ and C.sub.i.sup.-, respectively, may be included and driven by clock pulse phase A when it is desired to remove the integrating function from the circuit of FIG. 2 to provide a simple single ended to fully differential conversion block, with the capacitance of the capacitors C.sub.s and C.sub.i having the same values.

To better understand the operation of the circuit of the present invention illustrated in FIG. 2 reference may be had to the non-overlapping clock pulses, phase A and phase B, indicated in FIG. 3 of the drawings, which operate the switches S1-S8 and S11-S14 of the single ended to fully differential converter shown in FIG. 2. During the clock pulse phase A, which may, e.g., have a voltage magnitude of 5 volts and be equal to that of the voltage supply of the circuit, the switches S11, S1 and S3 are closed to sample the input voltage V.sub.IN applied to the first differential input terminal V.sub.IN.sup.+ and across the first storage capacitor C.sub.s.sup.+. Switches S5, S8 and S14 are also closed during the clock pulse phase A to discharge the plates P1 and P2 of the second storage capacitor C.sub.s.sup.- and to ground the second differential input terminal V.sub.IN.sup.-. During the clock pulse phase B, which does not overlap in time clock pulse phase A and which may have a voltage magnitude similar to that of clock pulse phase A, the switches S12, S7 and S6 are closed to apply a sample voltage to the input terminal - of the amplifier 10 through the second differential input terminal V.sub.IN.sup.- and the second storage capacitor C.sub.s.sup.-, while switch 13 grounds the first differential input terminal V.sub.IN.sup.+. Also during the clock pulse phase B the switches S2 and S4 are closed to apply the charge stored in the storage capacitor C.sub.s.sup.+ during the clock pulse phase A to the input terminal + of the amplifier 10. Thus, during the clock pulse phase B the signals at both the first and second differential input terminals V.sub.IN.sup.+ and V.sub.IN.sup.- are simultaneously applied to the input terminals + and -, respectively, of the amplifier 10. It should be understood that the frequency of the input signal or sine wave at V.sub.IN is significantly lower than the frequency of the clock pulses, with the clock pulses having a frequency of one megahertz or higher, if desired. Accordingly, it can be seen that fully differential signals V.sub.IN.sup.+ and V.sub.IN.sup.- have been applied to the differential amplifier 10 from the singled ended signal V.sub.IN without resorting to the use of costly, noise generating off-chip signal conditioning circuits. It should be noted that the single ended to fully differential converter of the present invention shown in FIG. 2 of the drawings has been produced by merely adding four switches to the integrator illustrated in FIG. 1 and altering the control of switches by the clock pulses. The circuit block of the present invention shown in FIG. 2 performs the single to fully differential conversion without affecting its operation as an integrator.

Of course, as mentioned hereinabove in connection with the circuit of FIG. 1 of the drawings, the block of FIG. 2 can be used simply as a gain block or a simple single ended to fully differential conversion block by applying clock phase A to switches S9 and S10 to discharge the capacitors C.sub.i.sup.+ and C.sub.i.sup.- during clock phase A, with the ratio of the capacitance of the capacitors C.sub.s /C.sub.i being used to scale the signal amplitude.

The following relationships in the circuit of the present invention shown in FIG. 2 of the drawings should be noted:

therefore,

Thus, it can be seen that the output signals V.sub.O.sup.+ and V.sub.O.sup.- satisfy the requirement of a fully differential signal, i.e.,

The factor of 2 can be cancelled by scaling the capacitor ratio C.sub.s /C.sub.i, or any other scale factor can be achieved by simply scaling the C.sub.s /C.sub.i ratio.

Accordingly, it can be seen that the present invention discloses a circuit having a single ended input signal with an output signal balanced about the common mode level of a fully differential circuit.

Thus, it can be readily seen that the switching scheme taught in FIG. 2 of the drawings performs a simple and inexpensive single ended to fully differential conversion on a single semiconductor chip without adversely affecting the function of any fully differential system requiring a fully differential input.

It can also be seen that the present invention improves noise performance by eliminating off-chip circuitry which often includes two amplifiers and other discrete components. It should also be noted that the circuit of the present invention saves surface area on a semiconductor chip since only four switches are added to the basic fully differential integrator block illustrated in FIG. 1 of the drawings to provide the conversion from a single ended signal to a fully differential signal.

FIG. 4 of the drawings illustrates a preferred circuit diagram of a single ended to fully differential converter of the present invention made in the CMOS technology. This circuit is somewhat similar to the circuit of the present invention shown in FIG. 2 of the drawings with similar elements in FIGS. 2 and 4 having the same reference characters. The circuit of FIG. 4 differs from that of FIG. 2 of the drawings in that the switches 1-8 and 11-14 are indicated as being transmission gates, each of which includes an N-channel field effect transistor connected in parallel with a P-channel field effect transistor. The circuit of FIG. 4 also differs from the circuit in FIG. 2 of the drawings in that the common mode terminal V.sub.cm connected to the switches S2 and S8 in FIG. 2 have been replaced by feedback terminals V.sub.FB.sup.+ and V.sub.FB.sup.-, respectively, so that, if desired, any feedback signal may be applied to these feedback terminals to subtract a feedback signal from the input signal. Also, if desired, the switches S1-S8 and S11-S14, instead of being transmission gates each of which has both N-channel and P-channel field effect transistors parallelly arranged, may consist of only a single field effect transistor of either the N-channel or P-channel type. However, as is known, the use of transmission gates is generally preferred since they provide a very low resistance path which makes full supply voltage swings available in the circuit.

The single ended to fully differential converter of FIG. 4 operates in a very similar manner to that of the circuit of FIG. 2 except that appropriate clock pulse voltages must be applied to the transmission gates S1-S8 and S11-S14 so as to simultaneously turn on both the N-channel and P-channel field effect transistors. Accordingly, as seen in FIG. 5 of the drawings, during phase A a first voltage A.sub.N has a positive voltage of, e.g., 5 volts, to turn on the appropriate N-channel field effect transistors while simultaneously a second voltage A.sub.P is at, e.g., 0 volts to turn on the corresponding P-channel field effect transistors. Likewise, during phase B a first voltage B.sub.N has a positive voltage of 5 volts to turn on the appropriate N-channel field effect transistors while simultaneously a second voltage B.sub.P is at approximately 0 volts to turn on corresponding P-channel field effect transistors.

It can be readily seen that since, in accordance with the teachings of this invention, the converter requires only CMOS transistors, or, if preferred, single metal oxide semiconductor (MOS) transistors, for the switches, along with capacitors which, as is known, are readily made from transistors by interconnecting the current carrying electrodes or source and drain terminals, an entire high gain fully differential amplifier having common mode feedback circuitry can be made on a single semiconductor chip at less cost, with less noise and in less space.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.