Self-Scanning Code Reading Device

1. A bar code scanning device, comprising: means for generating clock signal signals; means for performing repeated scans on a bar code presented to said scanning device, and for providing a set of transitions in an electrical signal corresponding to edges between bars and spaces encountered in each scan; means receiving in each of said repeated scans said electrical signal and said clock signals for detecting said transitions in said electrical signal and for providing successive time interval values each equalling the number of said clock signals received between corresponding successive transitions in said electrical signals; means receiving in each of said repeated scans said successive time interval values for detecting that a bar code is scanned whenever a subset of said time interval values in said scan demarcates bar code data, and for providing a decoded value for said bar code detected and asserting a successful decode signal; first memory means, receiving said decoded value from said means for providing a decoded value, for storing said decoded value as a most recent decoded value, said first memory means storing said decoded value whenever said successful decode signal is asserted; second memory means, receiving said most recent decoded value from said first memory means, for storing said most recent decoded value of said first memory means as a second most recent decoded value, said second memory means storing said most recent decoded value received in accordance with a control signal; a comparator, receiving and comparing said most recent decoded value from said first memory means and said second most recent decoded value from said second memory means, for asserting said control signal whenever said second most recent decoded value and said decoded value received are compared different; means for providing as output value of said bar code scanning device said most recent decoded value when said most recent decoded value and said second most recent decoded value are compared by said comparator to be the same for a predetermined number of times said successful decode signal is asserted.

2. A bar code reading device, comprising: means for receiving a generating clock signals; a photoelectric converting means for performing repeated scans on a bar code presented to said reading device and converting edges between the bars and spaces in each of said repeated scans into a set of transitions in an electrical signal; edge detecting means receiving in each of said repeated scans said electrical signal for detecting said transitions and for providing, for every transition detected in said electrical signal, a corresponding transition in an edge detection signal; counter means receiving in each of said repeated scans said clock signals and said edge detection signal for providing a series of counts, each count provided in accordance with the number of said clock signals received between successive transitions of said edge detection signal; decoding means, receiving in each of said repeated scans said series of counts and said edge detection signal, for detecting a bar code whenever a subset of said series of counts received demarcates bar code data, for decoding said bar code detected, in accordance with said series of counts and said edge detection signal, and upon successfully decoding said bar code detected, for providing a decoded value of said bar code and asserting a successful decode signal; first memory means receiving said decoded value from said decoding means and said successful decode signal for storing said decoded value received when said successful decode signal is asserted, said first memory means providing a first output value representing the stored content of said first memory means; second memory means receiving a first control signal and said first output value of said first memory means for storing said first output value when said first control signal is received in an asserted state, said second memory means providing a second output value representing the stored content of said second memory means; comparator means, receiving said first output value and said second output values value, for comparing said first output value and said second output values value, said comparator means asserting said first control signal when said first output value and said second output values value are different, said comparator means asserting a second control signal when said first output value and said second output values value are the same; and output means, receiving each decoded value of said decoding means and said first and second control signals, for outputting the decoded value of said decoding means when said first control signal is asserted and for inhibiting output of said decoded value when said second control signal is asserted.

3. A device as in claim 2, further comprising: start-stop means receiving a reset signal, said edge detection signal and said series of counts for detecting a pair of start and stop codes in each of said repeated scans, said start-stop means is initialized to detect said start code when said reset signal is in an asserted state, said start-stop means asserting a code normal signal when both said start and stop codes are detected, and asserting a code fail signal when at least one of said start and stop codes is not detected; wherein, said decoding means receives said code normal and code fail signals, said decoding means asserting said successful decode signal upon successfully decoding said bar code and receiving said asserted code normal signal, said decoding means asserting said reset signal after decoding said bar code, regardless of whether said decoding is successful, and said counter means also receives said reset signal and initializes said count to zero whenever said reset signal is asserted.

4. A device as in claim 3, wherein said first memory means further comprises: first memory control means receiving said decoded values from said decoding means and said successful decode signal for providing said first output value when said successful decode signal is asserted; and a first data memory receiving said first output value from said first memory control means for storing said first output value.

5. A device as in claim 4, wherein said second memory means further comprises: second memory control means receiving said first control signal and said first output value, for providing said second output value when said first control signal is asserted; and a second data memory receiving said second output value from said second memory control means for storing said second output value.

6. A device as in claim 5, wherein said second data memory also receives said reset signal, said second data memory is cleared when said reset signal is asserted.

7. A bar code reading device, comprising: means for generating clock signals; a photoelectric converting means for performing repeated scans on a bar code presented to said reading device and converting edges between the bars and spaces in each of said repeated scans into a set of transitions in an electrical signal; edge detecting means, receiving in each of said repeated scans said electrical signal, for detecting said transitions and for providing, for every transition detected in said electrical signal, a corresponding transition in an edge detection signal; first counter means, receiving in each of said repeated scans said clock signals and said edge detection signal, for providing a series of counts, each count provided in accordance with the number of said clock signals received between successive transitions of said edge detection signal; decoding means, receiving in each of said repeated scans said series of counts and said edge detection signal, for detecting a bar code scan whenever a subset of said series of counts received demarcates bar code data, for decoding said bar code detected, in accordance with said series of counts and said edge detection signal, and upon successfully decoding said bar code, for providing a decoded value of said bar code and asserting a successful decode signal; first memory means, receiving said decoded value from said decoding means and said successful decode signal, for storing said decoded value received when said successful decode signal is asserted, said first memory means providing a first output value representing the value stored in said first memory means; second memory means receiving an external reset signal, first and second control signals, and said first output value for storing said first output value when said first control signal is received in an asserted state, unless said second control signal is received in an asserted state after initialization and prior to receiving said asserted first control signal, said second memory means being initialized when receiving said external reset signal in an asserted state, and for providing a second output value representing the value stored in said second memory means; comparator means, receiving said first output value and said second output value, for comparing said first output value and said second output value, said comparator means asserting said first control signal when said first output value and said second output value are different, said comparator means asserting a second control signal when said first output value and said second output value are the same; second counter means, receiving said second control signal, a third control signal and said external reset signal, for providing as an assertion count the number of times said second control signal is asserted after either said external reset signal or said third control signal is received in an asserted state; judging means for asserting said third control signal when said assertion count is not less than said predetermined number and asserting a fourth control signal when said assertion count is less than said predetermined number; and output means, receiving each decoded value of said decoding means and aid third and fourth control signals, for outputting said decoded value when said third control signal is asserted and for inhibiting output of said decoded value when said fourth control signal is asserted.

8. A device as in claim 7, wherein said comparator means also receives said external reset signal, said comparator means comprises: a comparator for comparing said first and second output values, said comparator asserting an internal signal when said first and second output values are different and asserting said second control signal when said first and second output values are the same; and comparator control means for asserting, after said external reset signal is received in an asserted state, said first control signal in response to said asserted internal signal, and for preventing said first control signal to be asserted after said second control signal is asserted at least once, until said asserted external reset signal is received.

9. A device as in claim 7, wherein said second counter means comprises: a counting circuit receiving said second control signal and an internal reset signal for maintaining said assertion count, said second count being initialized to zero when said internal reset signal is received in an asserted state; and counter control means for asserting said internal reset signal in response to said asserted external reset signal or said asserted third control signal.

10. A device as in claim 7, wherein said judging means comprises: register means for storing said predetermined number; and data comparator means for comparing said predetermined number and said assertion count, said data comparator means asserting said third control signal when said assertion count is not less than said predetermined number and asserting said fourth control signal when said assertion count is less than said predetermined number.

11. A bar code reading device, comprising: means for generating clock signals; a photoelectric converting means for performing repeated scans on a bar code presented to said reading device and converting edges between the bars and spaces in each of said repeated scans into a set of transitions in an electrical signal; edge detecting means, receiving in each of said repeated scans said electrical signal, for detecting said transitions and for providing, for every transition detected in said electrical signal, a corresponding transition in an edge detection signal; first counter means, receiving in each of said repeated scans said clock signals and said edge detection signal, for providing a series of counts, each count provided in accordance with the number of said clock signals received between successive transitions of said edge detection signal; start-stop means, receiving a reset signal, said edge detection signal and said series of counts, for detecting in each bar code scanned a pair of start and stop codes, said start-stop means is initialized to detect said start code when said reset signal is in an asserted state, said start-stop means asserting a code normal signal when both said start and stop codes are detected, and asserting said code fail signal when at least one of said start and stop codes is not detected; decoding means, receiving said code normal and code fail signals, said series of counts and said edge detection signal, for decoding said bar code in each detected bar code scan in accordance with said series of counts, said code normal and code fail signals and said edge detection signal, and upon successfully decoding said bar code, for providing a decoded value of said bar code and asserting a successful decode signal, and for asserting said reset signal whenever a decoding is incorrectly executed; first memory means, receiving said decoded value from said decoding means and said successful decode signal, for storing said decoded value received when said successful decode signal is asserted, said first memory means providing a first output value representing the stored content of said first memory means; second memory means, receiving first and second control signals and said output value of said first memory means, for storing said output value when said first control signal is received in an asserted state, said second memory means cleared by said second control signal received in an asserted state, said second memory means providing a second output value representing the stored content of said second memory means; comparator means, receiving said first output value and said second output value, for comparing said first output value and said second output value, said comparator means asserting a third control signal when said first output value and aid second output value are different, said comparator means asserting a fourth control signal when said first output value and said second output value are the same; switch means for receiving said second, third and fourth control signals for providing said third signal as said first control signal from the time said second control signal is received in an asserted state to the time said fourth control signal is received in an asserted state; second counter means, receiving said second, third, and fourth control signals and a fifth control signals, for providing an assertion count equal to the number of times said fourth control signal is received in an asserted state since the last time said second control signal is received in an asserted state, said assertion count is initialized to zero when either said second control signal or said fifth control signal is received in an asserted state; judging means, receiving said assertion count, for asserting said fifth control signal when said second count is not less than a predetermined number, and asserting a sixth control signal when said assertion count is less than said predetermined number; and output means, receiving each decoded value of said decoding means and said fifth and sixth control signals, for outputting said decoded value when said fifth control signal is asserted and for inhibiting output of said decoded value when said sixth control signal is asserted.

12. A bar code reading device, comprising: means for generating clock signals; a photoelectric converting means for performing repeated scans on a bar code presented to said reading device and converting edges between the bars and spaces in each of said repeated scans into a set of transitions in an electrical signal; edge detecting means, receiving in each of said repeated scans said electrical signal, for detecting said transitions and for providing, for every transition detected in said electrical signal, a corresponding transition in an edge detection signal; first counter means, receiving in each of said repeated scans said clock signals and said edge detection signal, for providing a series of counts, each count provided in accordance with the number of said clock signals received between successive transitions of said edge detection signal; decoding means, receiving in each of said repeated scans said series of counts and said edge detection signal for detecting that a bar code is scanned whenever a subset of said series of counts received demarcates bar code data, for decoding, in each bar code scanned, said bar code detected in accordance with said series of counts and said edge detection signal, and upon successfully decoding said bar code, for providing a decoded value of said bar code and asserting a successful decode signal; first memory means, receiving said decoded value from said decoding means and said successful decode signal, for storing said decoded value received when said successful decode signal is asserted, said first memory means providing a first output value representing the stored content of said first memory means; second memory means, receiving a first control signal and said output value of said first memory means, for storing said output value when said first control signal is received in an asserted state, said second memory means providing a second output value representing the stored content of said second memory means; comparator means, receiving said first output value and said output value, for comparing said first output value and said second output value, said comparator means asserting said first control signal when said first output value and said second output value are different, said comparator means asserting a second control signal when said first output value and said second output value are the same; second counter means, receiving said first and second control signals, for providing an assertion count equal to the number of times said second control signal is received in an asserted state since the last time said first control signal is received in an asserted state; judging means, receiving said assertion count, for asserting a third control signal when said second count is not less than a predetermined number, and asserting a fourth control signal when said assertion count is less than said predetermined number; and output means, receiving each decoded value of said decoded means and said third and fourth control signals, for outputting said decoded value when said third signal is asserted and for inhibiting output of said decoded value when said fourth control signal is asserted.

13. A device as in claim 12, wherein said second counter means also receives an external reset signal, said second counter means further comprises reset circuit for initializing said second count to zero when either said first control signal or said external reset signal is received in an asserted state.