Phase-Locked Loop With Sync Detector

The present invention relates generally to phase-locked loops, and more particularly to a phase-locked loop with a sync detection circuit.

A prior art sync detection circuit, as shown and described in U.S. Pat. No. 4,724,402 issued to K. A. Ireland, for a phase-locked loop operates on a one-to-one comparison between the rising or falling edge of the output of a voltage-controlled oscillator and the corresponding edge of an input pulse signal of the phase-locked loop. If two or more edges occur or no edges occur during the period of the input signal, the circuit recognizes that the phase-locked loop has entered an asynchronous condition and determines that it is serious if such condition should continue for several periods of the input signal.

Since it is necessary to monitor the asynchronous condition for several periods of the input signal before making a final decision, a delay is inevitably introduced. Since the degree of precision of a phase-locked loop is proportional to such delay time, a long period of time would be required to monitor the asynchronous condition to implement a high-precision-sync-detection circuit.

It is therefore an object of the present invention to provide a high-precision-sync-detection circuit without introducing a substantial delay.

According to the present invention, the sync detection circuit comprises a phase detection circuit having a first input terminal to which an input pulse signal at frequency f.sub.0 is applied and a second input terminal to which an output pulse signal is applied for producing a frequency control signal representative of a difference in frequency or phase between the input and output pulse signals. A variable frequency oscillator is connected to the phase detection circuit to generate pulses at a fixed frequency f.sub.0 .times.N (where N is equal to or greater than 2) when the control signal indicates the absence of frequency or phase difference, or pulses at a variable frequency when the control signal indicates a frequency or phase difference. A frequency divider is provided for dividing the frequency of the pulses generated by the oscillator by a factor N and applying the frequency-divided pulses to the second input terminal as the output pulse signal to form a phase-locked loop. A decision circuit is provided for detecting when the pulses generated by the variable-frequency oscillator during an interval, which is defined between pulses of the input pulse signal, are equal to at least N so as to give an indication that a phase alignment is established between the input and output pulse signals. Therefore, a decision that a phase misalignment has occurred can be quickly made at the instant the number of pulses existing in that interval becomes equal to N-1 or N+1.

With N being equal to or greater than 4, the decision circuit preferably comprises a second frequency divider for dividing the frequency of the input pulse signal by a factor M to define said interval between successive pulses from the second frequency divider, where M is equal to or greater than 2 and the ratio N/M is equal to or greater than 2.

The present invention will be described in further detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a sync detection circuit for a phase-locked loop according to the present invention; and

FIG. 2 is a timing diagram associated with the sync detection circuit in which the integers M and N are set equal to 2 and 4, respectively.

A sync detection circuit of the present invention, as represented in FIG. 1, comprises a binary counter 6 connected to the voltage-controlled oscillator 4 of a phase-locked loop 1, a digital comparator 7, a reset 8 that resets the counter 6 to zero at intervals, a D-type flip-flop 11, and a divide-by-M frequency-dividing counter 12 to which an input signal at a frequency f.sub.0 is supplied through a terminal 13. Phase-locked loop 1 includes a phase detector 2 which compares the input signal supplied to terminal 13 with the output of a divide-by-N frequency-dividing counter 5 and supplies a phase difference signal through a low-pass filter 3 to the VCO 4. With a zero-voltage input, the VCO 4 generates a signal at frequency f.sub.0 .times.N, and varies this frequency as a function of the phase difference signal. The output of VCO 4 is counted down by divide-by-N counter 5 and the output of this counter is supplied to the phase detector 2 as a feedback signal so that the output of phase detector 2 substantially reduces to zero.

The output of VCO 4 is a pulse signal at a frequency which is N times higher than the input frequency of the phase-locked loop 1. Counter 6 is successively incremented in response to pulses from the VCO output and generates a digital signal that represents in binary fashion the count incremented from a count zero that occurs in response to the output of reset circuit 8. The instantaneous value of counter 6 is compared by digital comparator 7 with a binary reference value (M.times.N)-1. If coincidence occurs between the two inputs, comparator 7 supplies a coincidence indicating pulse to the D input of flip-flop 11 in order to latch it in response to the output of divide-by-M counter 12.

Reset circuit 8 comprises a zero detector 9 connected to the output of counter 6 and a D-type flip-flop 10 having a clock input coupled to the divide-by-M counter 12, the data input being constantly supplied with a logic 1. The output of flip-flop 10 goes high in response to the leading edge of the output of divide-by-M counter 12 and goes low in response to a pulse supplied to its clear input from zero detector 9 when it detects that the counter 6 is reset to zero. The high-level output of flip-flop 10 is supplied as a reset signal to the counter 6. Counter 6 is of a synchronously-resettable type. With a reset pulse being supplied from flip-flop 10, counter 6 is reset to zero in response to the trailing edge of an output pulse from the VCO 4.

The operation of the sync detection circuit will be best understood with reference to a timing diagram shown in FIG. 2. For simplicity of explanation disclosure, the integers M and N are set equal to "2" and "4", respectively. Thus, frequency-dividing counters 12 and 5 operate as divide-by-2 and divide-by-4 counters, respectively. The VCO output frequency is four times higher than the frequency of the input of phase-locked loop 1 and eight times the frequency of the output of divide-by-2 counter 12. Binary counter 6 is, therefore, incremented from zero in response to those pulses from VCO 4 that occur during the interval between successive leading edges of the output of counter 12. The output of digital comparator 7 goes high when binary counter 6 reaches a count value "7" (=2.times.4-1). In FIG. 2, the output frequency of the phase-locked loop 1 is lower than the input signal and gradually increases, and hence the phase difference between the inputs of phase detector 2 gradually decreases with time. In response to the leading edge of each pulse from the divide-by-2 counter 12, the Q output of flip-flop 10 goes high to generate a reset pulse and counter 6 is reset to zero at the trailing edge of a pulse from VCO 4. This zero count is detected by detector 9 and flip-flop 10 is reset. During the interval between successive leading edges of the output of divide-by-2 counter 12 as indicated by t.sub.0 and t.sub.1, counter 6 is incremented to a count "4" and during the next interval (t.sub.1 and t.sub.2), it is shown incremented to a count "6". Since the output of dividing counter 12 appears before counter 6 reaches the reference count "7" during the interval between times t.sub.0 and t.sub.2, no output is generated from comparator 7. With a further reduction in the phase difference during the interval between times t.sub.2 and t.sub.3, counter 6 reaches the reference count "7" immediately prior to time t.sub.3 and comparator 7 produces an output pulse. If the phase alignment is precise (i.e., if M.times.N pulses exist during the interval between successive leading edges of output of counter 12), the leading edge transition of the output of counter 12 occurs during the time the output of comparator 7 is high. If this is the case, the high-level output of comparator 7 is latched by flip-flop 11 in response to the leading edge of a pulse 20 from counter 12. Flip-flop 10 responds to this leading edge transition by applying a reset pulse to counter 6 at time t.sub.3 and so it is reset to zero, causing the output of comparator 7 to go low. The high level output from flip-flop 11 indicates that a stabilized phase alignment is established between the output of the phase-locked loop and the incoming signal.

If the output frequency of the phase-locked loop becomes higher than the input frequency, the output of comparator 7 goes low prior to the leading edge of the output of counter 12. Because of this misalignment, flip-flop 11 is reset, indicating the occurrence of a phase misalignment.

It is seen that the sync detection circuit of the present invention ensures high precision and a quick search for sync detection. The decision that a phase misalignment has occurrd can be made when the count of VCO pulses existing during the interval between successive pulses of the output of dividing counter 12 becomes equal to or lower than threshold MN-2 or equal to or higher than threshold MN. The time taken to ascertain phase misalignment, or degree of precision, can therefore be represented by values (MN-1)/MNf.sub.0 and (MN+1)/MNf.sub.0. In the above example, the precision is given by a range of values 7/8f.sub.0 and 9/8f.sub.0.

A further advantage of the present invention lies in the fact that if the positon of a pulse in the input of PLL1 is displaced due to jitter as shown at 21 in FIG. 2, divide-by-M counter 12 has the effect of averaging out such displacements so that the interval between successive leading edges of the output of counter 12 is rendered substantially constant and prevents the sync detection circuit from being adversely affected from jitter. However, the frequency-dividing counter 12 could be dispensed with for applications where timing jitter can be tolerated. In such applications, the integer M is set to "1" and N can be set equal to or greater than "2" to give a precision in the range between 1/2f.sub.0 and 3/2f.sub.0 for N=2, and 3/4f.sub.0 and 5/4f.sub.0 for N=4.

Therefore, according to a broader aspect of the present invention, the integer M is equal to or greater than unity and the ratio N/M is equal to or greater than 2. However, for applications where jitter is not tolerable, it is preferred that the integer M be equal to or greater than 2. For applications where sync detection speed is important and jitter is not tolerable, M is preferably equal to 2.

The foregoing description shows only one preferred embodiment of the present invention. Various modifications will be apparent to those skilled in the art without departing from the scope of the present invention which is limited only by the appended claims. Therefore, the embodiment shown and described is only illustrative, not restrictive.