Method for Forming a Grown Bipolar Electrode Contact Using a Sidewall Seed

The present invention relates generally to semiconductor technology, and more particularly, to methods of forming bipolar electrode contacts.

A known and accepted circuit element in the integrated circuit industry is the bipolar junction transistor (BJT). A popular and widely accepted BJT is known as the diffused BJT. In a diffused BJT, a diffusion region is formed that functions as a collector for the BJT. A base diffusion is formed within the collector diffusion, and an emitter electrode diffusion is formed within the base diffusion.

Another BJT that is known and accepted in the integrated circuit industry is the single polysilicon BJT. In the single polysilicon BJT, a deposited polysilicon layer is used to form an emitter electrode and/or an emitter contact. A diffusion is used to form a base electrode adjacent the emitter electrode, and a deep collector is formed by a buried doped region which underlies the base and emitter electrodes.

Yet another BJT which is known and accepted in the integrated circuit industry is the double polysilicon BJT. In the double polysilicon BJT, a first deposited polysilicon layer is used to form an emitter electrode and/or an emitter contact. A second deposited polysilicon layer is used to form a base electrode portion adjacent the emitter electrode. A deep collector is formed by a buried doped region which underlies the base and emitter electrodes in a manner which is similar to the single polysilicon BJT.

In the above embodiments, electrical contacts are formed to each of the emitter, base, and collector by forming one or more conductive layers over each of either the emitter, base, and collector by either deposition or a sputtering process. The contacts are therefore not self-aligned in some cases and result in structures that are less than optimal in terms of surface area. Photolithographic alignment and alignment tolerances also contribute to increased surface area when using this technology.

In order to self-align various features of a BJT, epitaxially grown emitter electrode contacts have been used. These epitaxially grown emitter electrode contacts are grown only from the substrate. In some cases, the emitter electrode contacts are grown in a manner that allows for the contact material to laterally overgrow a top portion of an oxide layer wherein the oxide layer is positioned adjacent the emitter electrode contacts. The lateral overgrowth of the emitter electrode contact is used to form a self-aligned contact pad for the emitter electrode. By initiating the growth from the substrate surface only, a long growth time is required for overgrowth to occur. Therefore, the epitaxial step, which is usually performed at temperatures of 850.degree. C. or higher, contributes greatly to a thermal budget of the overall integrated circuit process. A large thermal budget results in deeper diffused electrode regions that will, in most cases, increase parasitic capacitance and resistance and degrade bipolar transistor performance.

The previously mentioned disadvantages are overcome and other advantages achieved with the present invention. In one form, the present invention comprises a method for forming an electrical contact to a bipolar transistor electrode wherein a substrate is provided. A layer of material having a top surface is formed overlying the substrate. An opening is formed in the layer of material wherein the opening exposes a portion of the substrate and has a sidewall. A conductive region is formed within the substrate. The conductive region functions as the bipolar transistor electrode. A sidewall selective source material is formed adjacent the sidewall of the opening. A conductive contact region is formed within the opening via growth. The growth uses the sidewall selective source material as a growth source. The conductive contact region electrically contacts the bipolar electrode.

The present invention will be more clearly understood from the detailed description below in conjunction with the accompanying drawings.

FIGS. 1-6 illustrate, in cross-sectional form, a method for forming a grown bipolar electrode contact in accordance with the present invention;

FIGS. 7-11 illustrate, in cross-sectional form, another method for forming a grown bipolar electrode contact in accordance with the present invention;

FIGS. 12-14 illustrate, in cross-sectional form, yet another method for forming a grown bipolar electrode contact in accordance with the present invention;

FIG. 15 illustrates, in cross-sectional form, a spacer formation that is used as a source material for formation of a grown bipolar electrode contact in accordance with the present invention;

FIG. 16 illustrates, in cross-sectional form, yet another method for forming a grown bipolar electrode contact in accordance with the present invention;

FIGS. 17 and 18 illustrate, in cross-sectional form, yet another method for forming a grown bipolar electrode contact in accordance with the present invention;

FIG. 19 illustrates, in cross-sectional form, yet another method for forming a grown bipolar electrode contact in accordance with the present invention; and

FIGS. 20 and 21 illustrate, in cross-sectional form, yet another method for forming a grown bipolar electrode contact in accordance with the present invention.

Illustrated in FIG. 1 is a structure suitable for formation of a bipolar transistor 10 which has an epitaxially grown bipolar electrode contact. Transistor 10 has a substrate 12. Substrate 12 has a top planar surface prior to transistor processing. The substrate 12 is formed having a conductivity type which is one of either a P type conductivity or an N type conductivity if the substrate 12 is silicon-based. Substrate 12 may be made of silicon, gallium arsenide, silicon on insulator (SOI) structures, epitaxial formations, germanium, germanium silicon, polysilicon, amorphous silicon, and/or like substrate or conductive materials. Preferably, the substrate 12 is made of single-crystalline silicon.

A collector buried region 14 is formed via an implantation step or formed by a doping step which is subsequently followed by epitaxial growth of substrate material. Many conventional methods exist for formation of a buried region, some of which include ion implantation, diffusion technology, trenching and/or epitaxial growth. A collector well region 18 is formed overlying the collector buried region 14. The collector well region 18 is formed within a portion of the substrate material. The portion of the substrate material is either a portion of the substrate 12 or a similar substrate material such as an epitaxial substrate region grown from substrate 12. A deep collector region 16 is formed to provide a low resistance/highly-doped electrical contact to the collector buried region 14. Together, regions 14, 16, and 18 form a collector electrode or a collector for the transistor 10. The collector is doped to a conductivity type which is opposite the conductivity type of the substrate 12.

A field dielectric layer 20 is selectively formed overlying portions of the substrate 12. Field dielectric layer 20 is usually a grown wet silicon dioxide (SiO.sub.2) layer although other dielectric materials may be used. The dielectric layer 20 as well as other dielectric materials described herein may be formed as wet or dry silicon dioxide (SiO.sub.2), silicon nitride, tetraethylorthosilicate (TEOS) based oxides, borophospho-silicate-glass (BPSG), phospho-silicate-glass (PSG), boro-silicate-glass (BSG), oxide-nitride-oxide (ONO), plasma enhanced silicon nitride (P-SiN.sub.x), a spin on glass (SOG), and/or like dielectric materials unless otherwise noted. Other forms of isolation exist, such as trench isolation, local oxidation of silicon (LOCOS), or polysilicon buffered LOCOS (PBL), and any known form of isolation may be used to replace the field oxide isolation illustrated via dielectric layer 20. Regions of the surface of the substrate 12, deep collector region 16, and/or collector well region 18 which are not covered by dielectric layer 20 are referred to as active areas.

A thin dielectric layer 22 is formed over the deep collector region 16 and the collector well region 18 as illustrated in FIG. 1. The dielectric layer 22 is preferably grown to a single thickness within a range from 80 Angstroms to 500 Angstroms. Dielectric layer 22 is, in most cases, a grown wet or dry SiO.sub.2 layer. A sacrificial oxide layer (not illustrated) may be formed and removed before formation of the dielectric layer 22 to improve device performance.

In FIG. 2, portions of the dielectric layer 22 which overlie the collector well region 18 are removed. A conductive layer 24 is formed overlying the dielectric layer 22, the collector well region 18 and the dielectric layer 20. The conductive layer 24 is in electrical contact with the collector well region 18. Preferably, the conductive layer 24 is polysilicon, amorphous silicon, or a like silicon-based material. The conductive layer 24 is ion implanted or doped with dopant atoms which are of the same conductivity type as the substrate 12 (one of either P type or N type). A dielectric layer 26 is formed over the conductive layer 24. Preferably, the dielectric layer 26 is a TEOS-based oxide and is formed via a CVD process.

In FIG. 3, portions of the dielectric layer 26 and the conductive layer 24 are removed in an etch step to expose portions of the collector well region 18 and to expose portions of the dielectric layers 20 and 22. An opening 36 is formed through layers 24 and 26 via this etch step. In general, oxides may be etched using, for example, a CHF.sub.3 and O.sub.2 plasma or a C.sub.2 F.sub.6 plasma. Polysilicon may be etched using a HBr and Cl.sub.2 plasma. Any of the above stated plasma environments may contain one or more inert carrier gases such as Ar, H.sub.2, He, N.sub.2, or a like inert carrier gas. The etching of layers 24 and 26 forms sidewalls of conductive layer 24.

In FIG. 3, the sidewalls of the conductive layer 24 and an exposed portion of the collector well region 18 are oxidized to selectively form oxide regions 28. Oxide regions 28 are preferably wet or dry silicon dioxide films. If the conductive layer 24 is made of a material which either does not oxidize or does not form a reliable quality oxide, a dielectric sidewall spacer (not illustrated) may be optionally used to electrically isolate portions of the conductive layer 24 from adjacent regions (not illustrated in FIG. 3).

In FIG. 3, either the thermal processing used to form the oxide regions 28 or an independent thermal processing step is used to drive dopant atoms from the conductive layer 24 into the collector well region 18 to form doped base regions 32. In addition, an ion implant step, a diffusion step, or a like doping step is used to form a self-aligned second doped base region 30 within the collector well region 18. The doped base regions 30 and 32 are of a conductivity type which is opposite the conductivity type of collector well region 18 and is the same as the conductivity type of the substrate 12. During the formation of the doped base region 30 a mask layer (not illustrated) may be needed to prevent dopant atoms from entering the deep collector region 16.

In FIG. 4, a conductive layer (not illustrated) is deposited overlying the dielectric layers 20,22, and 26, and the oxide regions 28. The conductive layer is etched via a reactive ion etch (RIE) process or a similar etch process to form spacers 38. Preferably, the spacers 38 are formed of polysilicon or a like silicon-based material. The spacers 38 are formed with a bottom base spacer thickness ranging roughly from 400 Angstroms to 2,500 Angstroms.

In FIG. 5, a conventional photoresist masking step is used to mask the spacers 38 which are adjacent the doped base regions 30 while the spacers 38 which are overlying the dielectric layer 20 are removed via an etch step. A wet etch step, such as etching in a solution containing nitric acid and HF, is used to remove the spacers 38 if the spacers 38 are polysilicon or silicon-based materials. In some cases, to avoid photoresist removal, a dry etch is used instead of a wet etch.

An optional masking layer (not illustrated) may be formed to protect exposed dielectric layers 20,22,26 and portions of oxide regions 28. A dielectric layer etch step is then used to etch the oxide regions 28 which overlie the collector well region 18. If no masking layer (not illustrated) is used, then the dielectric layers 20,22, and 26 must be formed thick enough to withstand a small time period of oxide etching without being completely removed. "L-shaped" dielectric regions of oxide regions 28, which are positioned laterally adjacent the sidewall of conductive layer 24, remain after the dielectric etch step as illustrated. The dielectric etch step may, as indicated above, slightly remove exposed portions of other oxides and may undercut the spacers 38 in some cases.

In FIG. 6, a conductive region 34, referred to also as a conductive contact region, is formed by epitaxial growth or selective processing. The spacers 38 are used as silicon growth seed regions. Spacers 38 are also referred to as growth source material or sidewall selective source material. In other words, the spacers 38, or a like sidewall formation, are a source of silicon for selective formation of the conductive region 34. In addition, an exposed surface of the collector well region 18 which lies between the spacers 38 is also an epitaxial seed layer or epitaxial source layer for formation of conductive region 34. The conductive region 34 may be selectively formed as any silicon based material such as polysilicon, single-crystalline silicon, germanium silicon, doped silicon, a silicide, or a combination of silicon-based materials in a preferred form. The conductive region 34 is either in-situ doped, ion implanted, or doped in a similar manner to a conductivity type which is the same as the collector well region 18 but opposite the conductivity type of the substrate 12.

A diffusion region, referred to as an emitter doped region 31, is formed by thermally driving dopant atoms out of the conductive region 34 into the doped base region 30. The emitter doped region 31 is of a conductivity type that is the same as the conductive region 34 and is self-aligned to the opening 36. Conductive region 34 forms an electrical contact to the emitter doped region 31. The conductive region 34 may also be referred to as a portion of an emitter electrode.

The conductive region 34 is laterally grown over a top portion of the dielectric layer 26 to form a self-aligned conductive contact pad. The conductive contact pad is used to more reliably form electrical contact between the emitter doped region 31 and an overlying conductive layer (not illustrated). Polysilicon is a preferred material for conductive region 34 because dopants diffuse in polysilicon at a rate that is faster than many other silicon-based conductive materials. In addition polysilicon has a lateral overgrowth to vertical growth rate ratio of 1:1 whereas single-crystalline silicon has a lateral to vertical growth rate ratio of 1:2. Therefore, a polysilicon epitaxial conductive region will have improved topography and have a potentially larger contact pad surface area to decrease electrical short circuits and/or misalignment problems.

One advantage of forming the transistor 10 as taught herein is due to the conductive spacers 38. The growth of conductive region 34 requires less time than selective growth from only the surface of doped base region 30 due to the presence of the spacers 38. Therefore, because epitaxial growth requires a high thermal temperature, a reduced growth time will result in less impurity diffusion and charge diffusion, shallower bipolar electrode junctions, and improved device performance. In other words, the thermal budget of the bipolar process taught above will be lessened, which is desirable, and more flexible.

It is important to note that diffusion regions for transistor electrodes may be formed in the substrate 12 prior to forming openings in overlying layers. Although the diffusion regions will not be self-aligned to the openings when using this method, this method is still used to some extent in the integrated circuit industry.

FIGS. 7-11 illustrate another method for forming an electrical contact to an electrode of a bipolar transistor 11. Elements of FIGS. 7-11 that are analogous to elements in FIGS. 1-6 are identically labeled. In FIG. 7, the substrate 12, the collector buried region 14, the deep collector region 16, the collector well region 18, and the dielectric layers 20 and 22 are formed or provided in a manner similar to that which is illustrated in FIG. 1.

In FIG. 7, a base diffusion region 44 is formed within the collector well region 18. The base diffusion region 44 has a conductivity type which is the same as the substrate 12. The base diffusion region 44 is either diffused or ion implanted before or after formation of the dielectric layer 22. Sacrificial oxides (not illustrated) or screen oxide layers (not illustrated) may also be used in a conventional manner to improve ion implantation processing. A dielectric layer 40 is formed overlying the dielectric layers 20 and 22. The dielectric layer 40 is preferably a nitride layer such as silicon nitride. The thickness of dielectric layer 40 is preferably less than 1000 Angstroms. A dielectric layer 42 is formed overlying the dielectric later 40. The dielectric layer 42 is preferably a TEOS-based oxide or a like dielectric layer.

In FIG. 8, a plurality of openings 46 is formed through the dielectric layers 40 and 42. The plurality of openings 46 may be two physically separate openings or may form a single cylindrical-shaped opening. The cylindrical-shaped opening would surround the portion of the dielectric layer 42 which overlies the collector well region 18. The plurality of openings 46 is formed by silicon and/or TEOS etching. Silicon nitride and/or TEOS etching is accomplished via CHF.sub.3 or CF.sub.4 combined with O.sub.2 or CO.sub.2 in a plasma environment or C.sub.2 F.sub.6 plasma environments. In addition, silicon nitride may be wet etched in a solution of phosphoric acid ((C.sub.2 H.sub.5 O).sub.2 POOH) or may be etched via methanol-based (CH.sub.3 OH) chemistry. Oxide may be wet etched in an HF solution or buffered HF which is HF mixed with ammonia hydroxide. The etching of dielectric layer 42 is performed selectively to dielectric layer 40, and dielectric layer 40 is etched selective to dielectric layer 20 and base diffusion region 44.

In FIG. 8, conductive sidewall spacers 48 are formed adjacent sidewalls of the openings 46 as illustrated. An RIE over-etch step may be optionally used to vertically recess the spacers 48 down the sidewalls of the dielectric layer 42 as illustrated in FIG. 8. In a preferred form, spacers 48 are formed of polysilicon or a like silicon-based material.

In FIG. 9, an epitaxial growth step is used to form a conductive region 50. Conductive region 50 is epitaxially or selectively seeded from the spacers 48 and in most cases is also epitaxially seeded from exposed portions of base diffusion region 44. The vertical recession of the spacers reduces or prevents lateral overgrowth of conductive region 50 over top surfaces of dielectric layer 42. In this embodiment, the lateral overgrowth of the conductive region 50 is undesirable. The conductive region 50 makes electrical contact to the base diffusion region 44 and therefore makes electrical contact to a base electrode of transistor 11. Conductive region 50 may be in-situ doped, ion implanted, or doped in any manner with dopant atoms. The dopant atoms have a conductivity type which is the same as the conductivity type of the substrate 12.

In FIG. 10, the dielectric layers 40 and 42 are completely removed and a dielectric layer 56 is formed to insulate the conductive region 50. Preferably, the dielectric layer 56 is grown from conductive region 50 thereby forming a silicon-based oxide layer (i.e. silicon dioxide).

In FIG. 10, a conductive layer (not illustrated) is deposited over the surfaces of dielectric layers 20, 22, and 56. The conductive layer (not illustrated), which is preferably polysilicon or a silicon-based material, is etched to form a spacer 54. It should be apparent that the spacer 54 will form along other sidewalls illustrated in FIG. 10. The spacers formed adjacent other sidewalls are removed by conventional masking and etching procedures which were also illustrated and taught in reference to FIGS. 4-5.

In addition, dopant atoms from the conductive region 50 are thermally driven from the conductive region 50 into the substrate 12 and/or base diffusion region 44 via a heat cycle to form a base diffusion region 52. Typical dopant atoms are boron for a P type dopant and arsenic or phosphorus for an N type dopant.

In FIG. 11, a portion of the dielectric layer 22 which is exposed within an inner perimeter of the spacer 54, is removed. A self-aligned emitter contact, referred to as a conductive region 60, is formed via a process similar to the process taught for conductive region 34 of FIG. 6. Furthermore, dopant atoms are placed within conductive region 60 as described herein. A heat cycle is used to thermally drive dopant atoms from the conductive region 60 to form an emitter doped region 58. The conductive region 60 has all of the advantages of conductive region 34, such as the formation of an improved self-aligned contact pad, improved overgrowth capability, and a reduced thermal budget. A collector contact to deep collector region 16 is formed in one of several conventional manners (not illustrated in FIG. 11).

FIGS. 12-14 illustrate yet another method for forming a self-aligned contact to an emitter electrode of a bipolar transistor 13. Element in FIGS. 12-14 which are analogous to elements FIGS. 7-11 are identically labeled. In FIG. 12, the substrate 12, the collector buried region 14, the deep collector region 16, the collector well region 18, the dielectric layers 20 and 22, and the base diffusion region 44 are formed or provided in a manner similar to the process discussed above in reference to FIG. 7. A dielectric layer 62 is formed overlying the dielectric layers 20 and 22. Preferably, dielectric layer 62 is a TEOS-based dielectric layer which has a thickness ranging from roughly 2,000 Angstroms to 10,000 Angstroms.

In FIG. 13, an opening is formed in the dielectric layer 62 as illustrated. The opening exposes a portion the base diffusion region 44. A thin dielectric layer (not illustrated) is grown over the exposed portion of the base diffusion region 44 to replace the removed dielectric layer 22. A spacer 64 is formed from a silicon-based material as described herein. The thin dielectric layer (not illustrated) which overlies the base diffusion region and lies within an inner perimeter of the spacer 64 is selectively removed. A portion of dielectric layer 22 remains underlying the spacer 64 as illustrated.

In FIG. 14, the spacer 64 and an exposed portion of the base diffusion region 44 are used to epitaxially seed the conductive region 66 as described herein. The dielectric layer 62 is removed to expose portions of the base diffusion region 44. The exposed portions of the base diffusion region 44 are implanted or doped to form base regions 68 which are self-aligned via conductive region 66. The doping or implanting of base regions 68 may optionally be performed through a dielectric screen layer (illustrated as a portion of dielectric layer 22). Contact to the base regions 68 and the deep collector region 16 are accomplished in a conventional manner.

FIG. 15 illustrates an alternative spacer formation that is used to provide an epitaxial growth source region to form a grown bipolar electrode contact. In FIG. 15, the substrate 12 is as described herein. A diffusion 70 may be one of either a collector, an emitter, or a base electrode formation or only a portion of one of these electrodes. A material 72, which in most cases is a dielectric material, is formed overlying the substrate 12 and has an opening. A dielectric spacer 74 is formed adjacent a sidewall of the opening. Spacer 74 is preferably made of an oxide or nitride material. A conductive spacer 76 is formed adjacent the dielectric spacer 74. The conductive spacer 76 is used to seed a conductive electrical contact (not illustrated in FIG. 15) to the diffusion 70 in an epitaxial or selective manner. This method may be used in any of the embodiments illustrated herein, in any bipolar transistor structure, or in any structures requiring electrical contact or connection. One advantage is that smaller contacts or smaller bipolar electrodes are desired for some applications. Smaller contacts and/or smaller bipolar electrodes will result when using the structure illustrated in FIG. 15.

In FIG. 16, a method for forming selective or epitaxial electrical contact to a collector electrode is illustrated. The contact may be formed simultaneously with the formation of either a base contact or an emitter contact or may be formed sequentially along with the formation of other contacts. In FIG. 16, the substrate 12, the collector buried region 14, the deep collector region 16, the collector well region 18, and the dielectric layers 20 and 22 are formed or provided in a manner similar to that which is illustrated in FIG. 1.

In FIG. 16, a dielectric layer 78 is formed wherein dielectric layer 78 has an opening. A conductive spacer 80 is formed as described herein. The conductive spacer 80 is used to seed or source a selective or epitaxial contact to the deep collector region 16 as described herein. Therefore, a collector region contact may have all of the advantages discussed herein in reference to FIGS. 6, 11, and 14.

In FIGS. 17-18, another method for forming a self-aligned grown bipolar electrode contact is illustrated. FIG. 17 illustrates the doped collector well region 18 which is identically labeled to FIG. 1. A dielectric layer 82 is formed in FIG. 17. The dielectric layer 82 has an opening. A seed layer of material is deposited to form a layer 84. Preferably layer 84 is polysilicon or a similar seed layer. A dielectric layer 86 is formed overlying layer 84 via spin-on techniques, planarization etch-back, chemical mechanical polishing (CMP), or the like as illustrated in FIG. 17. It should be mentioned that in FIGS. 17-18 all regions within collector well region 18 and many other structural regions are not specifically illustrated. FIGS. 17-18 are intended to focus on the contact formation and focus less on the other structural details which have already been taught herein.

In FIG. 18, portions of the layer 84 which overlie the dielectric layer 82 are removed leaving a "U" shaped region of layer 84 in the opening of dielectric layer 82 due to dielectric layer 86. Dielectric layer 86 is then removed selective to layer 84. Layer 84 is then used as a source for selective growth. It is important to note that the method illustrated in FIGS. 17-18 may be used to minimize trenching of various substrate regions.

FIG. 19 illustrates yet another method which may be used to form a grown bipolar electrode contact. The collector well region 18 is illustrated in FIG. 19. As in FIGS. 17-18, all regions within collector well region 18 and many other structural regions are not specifically illustrated for simplicity. A dielectric layer 88 is formed, a conductive seed layer 90 is formed overlying the dielectric layer 88, and a dielectric layer 92 is formed overlying the conductive seed layer 90. An opening is formed through the layers 88, 90, and 92 as illustrated in FIG. 19. A sidewall of conductive seed layer 90 is used to grow a portion of the selective grown bipolar electrode contact. Growth occurs in the directions of the arrows which are illustrated in FIG. 19.

FIGS. 20-21 illustrate yet another method for forming a grown bipolar electrode contact. The collector well region 18, the dielectric layer 82 with the opening, and the layer 84 are illustrated as in FIGS. 17-18. As in FIGS. 17-18, all regions within collector well region 18 and many other structural regions are not specifically illustrated for simplicity. In FIG. 20, a dielectric spacer 94 is formed overlying the layer 84 and adjacent a sidewall of the opening in dielectric layer 82. An etch step is performed to form an "L" shaped region of seed material from layer 84 using the dielectric spacer 94 as a hard mask. Region 84 is used as a source material for contact growth.

While the present invention has been illustrated and described with reference to specific embodiments, further modifications and improvements will occur to those skilled in the art. For example, electrical contacts may be made to other devices using the inventive methods discussed herein. In addition, the method discussed herein may be able to form electrical contacts for any lateral or vertical bipolar device. The methods of growing electrical contacts, as taught herein, may be used to connect two substrate-overlying conductive layers together. In other words, the contact methods taught herein are not limited to substrate contacts. For example, the substrate 12 of FIG. 15 could instead be a dielectric layer, and the diffusion 70 of FIG. 15 could instead be a conductive region overlying an underlying substrate. Epitaxial growth, as discussed in the above embodiments is intended to cover any selective method of formation which is seeded from spacers or sidewall formations. There are sidewall formations, other than spacers, that are functionally equivalent to spacers which are formed by other methods, such as selective deposition used in conjunction with etch-back or planarization techniques. The spacers described herein may also be formed as silicided or salicided material or other known conductive seed materials such as TiN. Overgrowth of the epitaxial electrical connection taught herein is optional. Growth, as lithographic dimensions are reduced or if underlying layers do not provide for growth, may be initiated only off of the spacers. The growth from spacers which is taught herein may result in electrode contact regions which have non-planar top surfaces. Known chemical and/or mechanical polishing steps or like planarization steps may be used to planarize the top surface of the electrode contact regions taught herein. It is to be understood, therefore, that this invention is not limited to the particular forms illustrated and that it is intended in the appended claims to cover all modifications that do not depart from the spirit and scope of this invention.