Quasi-Static Level Shifter

This invention relates to a level shifter comprising a charging path between a first supply voltage and an output, and a discharging path between the output and a second supply voltage, the paths being controllable in a mutually complementary fashion by an input signal on an input, one of the paths being DC coupled to the input while the other path is coupled thereto via a capacitance. The invention also comprising a driver circuit which includes such level shifters and to a display provided with such a driver circuit.

A level shifter of this kind is known per se. The operation of the known level shifter is fully dynamic, i.e. its output signal is not available in static form. Driving of further circuits by means of this output signal requires either a time-critical behaviour of these circuits or special steps to safeguard control of these circuits because at least one of the levels of this output signal is not stable. Therefore, it is an object of the invention to provide a level shifter of the kind set forth which does not have said drawbacks.

This object is achieved by a level shifter in accordance with the invention which is characterized in that in order to regenerate a control voltage on a control input of the other path, the input signal is logically combined with a recurrent signal which can be applied to the control input via the capacitance. The signal transferred via the capacitance to the gate electrode of an FET in the other path is then continuously regenerated by the recurrent signal. The logic combination of the recurrent signal with the input signal ensures that the level shifter behaves as a static level shifter at its output, i.e. both logic levels on the output are substantially constant.

In the context of the present Patent Application, a recurrent signal is to be understood to mean not only a periodic signal, i.e. a signal which recurs after a regular time interval, but also a signal which recurs after an irregular time interval and/or with a deviating waveform.

In comparison with static level shifters, the level shifter in accordance with the invention also requires less surface area. Moreover, the power consumption of the level shifter in accordance with the invention is substantially lower.

The level shifter is preferably used in a driver circuit for controlling the row-wise and column-wise arranged display elements of a display apparatus, for example, an LCD display. A plurality of level shifters can then be advantageously combined so that a number of components can be used in common in a number of level shifters. For example, a spike generator can then apply the same recurrent signal to several level shifters simultaneously. Such common use results in a substantial further reduction of the surface area required.

It is to be noted that the level shifter and driver circuits in accordance with the invention can be realised on a semiconductor substrate or also according to the so-called thin-film technique. In this respect reference is made to the article by J. C. Erskine and P. A. Snopko "A thin-film-transistor-controlled liquid-crystal numeric display", IEEE TED 26 (5), 1979, pp. 802-806. Thin-film integrated circuits can be advantageously used for display applications where the circuits are integrated in a thin film on a substrate, for example, a glass plate or a quartz plate. The substrate then forms part of the screen of the (LCD) display. It will be evident that a higher degree of system integration can thus be achieved.

The invention will be described in detail hereinafter with reference to the accompanying drawing; in which

FIG. 1 shows an example of a dynamic level shifter,

FIG. 2 shows an example of a level shifter in accordance with the invention,

FIG. 3 shows the voltages at various points in the circuit shown in FIG. 2, and

FIG. 4 shows an array of level shifters in accordance with the invention which use parts in common.

FIG. 1 shows a dynamic level shifter 10 which is integrated on a semiconductor substrate in the present example. The level shifter 10 comprises a P-channel transistor 16 connected between a first supply terminal 12 and the output 14 and an N-channel transistor 20 connected between the output 14 and a second supply terminal 18. The supply voltage on the terminal 12 is, for example, 5 V and that on the terminal 18 is, for example, minus 30 V. The input 22 receives input signals whose level (for example, 0-5 V) is transformed by the level shifter 10. The input 22 is directly connected to the gate of the transistor 16 and the capacitance 24 provides a capacitive coupling between the input 22 and the gate of the transistor 20. There is also provided a control discharging path for the gate of the transistor 20 which in this case comprises the output branch 26 of a current mirror 28. The control discharging path ensures that an accumulation of charge on the gate of the transistor 20, caused by a positive signal transition on the input 22, flows to the terminal 18. On the other hand, the PN-junction 30, being inherent in a P-well technology, provides equalization in the case of a negative signal transition on the input 22. The control discharging path as well as said PN-junction prevent a floating potential on the gate. It is a drawback of this circuit that the lowest level of the output signal on the output 14 does not have a fixed value because the transistor 20 is turned on only during and briefly after a positive transition of the input signal. The circuits controlled by the output signal thus have to respond only briefly to the negative transition of the output signal or buffering is required at the input side.

FIG. 2 shows an embodiment of a level shifter 40 in accordance with the invention which does not have said drawbacks. The reference numerals corresponding to those used in FIG. 1 denote similar or identical components. Instead of the direct capacitive coupling of the input 22 to the gate of the N-channel transistor 20, the input signal is first combined with a spike-shaped recurrent signal in the logic gate 42 whose input side is connected to the input 22 and to a spike generator 44. In the absence of the gate 42 and the spike generator 44, i.e. with the input terminal 22 directly connected to capacitor 24, the control voltage at the gate of FET 20 would change gradually due to the leakage of the electrical charge. This could then result in a variation in the output voltage at the output terminal 14 so that the logic state could be erroneously interpreted by the following circuit. According to the invention, the control voltage at the gate of FET 20 is refreshed by logically combining the input signal with the recurrent signal and supplying the combination signal to the control input of FET 20 via the capacitor 24. In effect, the input signal at terminal 22 functions as an enabling signal for the transmission of the recurrent signal to the capacitor. The signals present at various points in the circuit are shown in FIG. 3. The upper line V.sub.22 represents the input signal on the input 22. The second line V.sub.1 represents the spike-shaped recurrent output signal of the spike generator 44. The line V.sub.2 therebelow represents the signal combined in the logic gate 42 and which is supplied to the capacitance 24. V.sub.3 represents the signal filtered by the capacitance 24 and present on the gate of the transistor 20, and the line V.sub.14 represents the output signal of the level shifter at the output 14. As a result of the combination operation, the voltage on the gate of the transistor 20 is periodically regenerated. This means that the logic high level of this voltage remains defined within a given range and hence also the low level of the output signal V.sub.14. The input signal V.sub.22 varies between V.sub.DD and V.sub.SS, whereas the range of the output signal V.sub.14 lies between V.sub.DD and V.sub.EE. The output range is greater than the input range.

Instead of a spike-shaped signal, a signal having an arbitrary waveform can be used when this signal is recurrently applied to the logic gate 42 during a short period of time. In either case, when the signal voltage V.sub.22 switches from the voltage level V.sub.SS to V.sub.DD, transistor 16 is turned off. At the same time, the AND gate 42 is enabled and transmits the spike voltage V.sub.1, superimposed on the voltage V.sub.22, to the capacitor 24. The capacitor functions as a short circuit for the high frequency spike-shaped signal V.sub.1 so that the negative going spike is applied to the gate of transistor 20, where it is added to the voltage already present at the gate. For a brief instant, the sum of the voltages may be lower than the voltage V.sub.EE so that diode 30 conducts, whereupon electric charge is supplied to the gate of FET 20. When the spike voltage disappears, the charge will remain at the gate so as to produce a higher voltage than was present prior to the occurrence of the spike. This charge will gradually leak away via transistor 26 causing the gate voltage V.sub.3 to gradually decrease until it is refreshed by the next spike voltage. So long as the spike voltages reappear before the gate voltage drops below a given limit value, the output voltage V.sub.14 of the level shifter circuit will remain stable.

FIG. 4 shows an embodiment comprising a plurality of n level shifters in accordance with the invention, the spike generator 44 as well as the input branch of the current mirror 28 being shared by a plurality of level shifters a . . . n. This embodiment offers the advantage that the surface area required and also the current consumption are reduced. In this Figure each of the elements of the level shifters a . . . n is denoted by the same reference numeral as used in FIG. 2, supplemented by one of the letters a . . . n.

It is to be noted that the described embodiments relate to combined control of the N-channel transistor. A similar arrangement in the complementary case, i.e. in the case of capacitive control of the P-channel transistor, can be controlled in a similar manner.

It is also to be noted that the same principle can also be used, for example, in the case of a push-pull stage consisting of two N-channel transistors.

Finally, it is to be noted that instead of a current mirror as used in the above preferred embodiment, other control input discharging paths can be used, such as a diode, for example, a high-ohmic poly-diode, a resistor, a parallel connection of a resistor and a diode.