Precharge Circuit

This invention relates to a precharge circuit, and more particularly to a precharge circuit used for the precharge operation of a dynamic random access memory (DRAM), etc. driven by a single power supply and having no need for initialization. The initialization mentioned above refers to a standby operation for a time period until the precharge circuit is caused to normally function after being powered.

A conventional precharge circuit used for the precharge operation of a DRAM, etc. is shown in FIG. 1. This precharge circuit comprises N-channel metal oxide semiconductor (MOS) transistors (hereinafter referred to as transistors for convenience) N.sub.1, . . . N.sub.8, N-channel MOS capacitors (hereinafter referred to as capacitors for convenience C.sub.apl, . . . C.sub.ap4, inverter circuits I.sub.NV1, . . . I.sub.NV3, and a NOR circuit NORl. This precharge circuit operates in such a manner that when the voltage level of an input signal provided for step-up operation as inputted to the input terminal of capacitor C.sub.ap4 is equal to a zero level irrespective of values of an input signal I.sub.N1 inputted to the drain of the transistor N.sub.l, an input signal I.sub.N2 inputted to one end of the capacitor C.sub.apl, and an input signal I.sub.N3 inputted to the input terminal of the inventor circuit I.sub.NVl, the level of the potential on the output terminal Boot becomes the power supply voltage V.sub.cc level. However, when the voltage level of the input signal Push is equal to the power supply voltage V.sub.cc level, the potential on the output terminal Boot is stepped up so that it is greater than V.sub.cc +V.sub.Th, where V.sub.Th represents a threshold value of a MOS transistor.

The problems with the above-mentioned conventional precharge circuit will now be described with reference to FIG. 2. In the initial state (time t.sub.0) immediately after the precharge circuit is powered, input signals I.sub.N1, I.sub.N2 and I.sub.N3 are either at the power supply voltage V.sub.cc level provided by a single power supply, i.e., at a high of "H" level, or at a zero level (reference level), i.e., at a low or "L" level. It is now assumed that those signals are at "H" level. Generally, capacitors C.sub.api (i=1, . . . 4) are (electrostatically) coupled with nodes connected to respective output terminals at the points of time when input signals inputted to the respective input terminals vary, and their rise or fall operations have been completed. For this reason, at the time t.sub.0, there occurs no connection between the capacitor C.sub.apl and the node 101. As a result, the level of a potential on the node 101 connected to the source of the transistor N.sub.1 becomes equal to the level of V.sub.cc -V.sub.Th. This potential is applied to the gates of the transistors N.sub.2 and N.sub.3. On the other hand, the node 103 connected to the output terminal of the inverter circuit I.sub.NVl is placed at the in "L" level in potential because the input signal I.sub.N3 is in the state of "H" level. Accordingly, the level of potential on the node 104 connected to the output terminal of the inverter circuit I.sub.NV2 becomes equal to "H" level, and the level of a potential on the node 105 connected to the output terminal of the inverter circuit I.sub.NV3 becomes equal to "L" level. Since the nodes 103 and 105 connected to respective input terminals of the NOR circuit NORl are at "L" level, the node 106 connected to the output terminal of the NOR circuit NORl is held at "H" level, i.e., level of the power supply voltage V.sub.cc. On the other hand, the node 102 connected to the drains of the transistors N.sub.3 and N.sub.4 and the gate of the. transistor N.sub.5 is kept at a potential level V.sub.cc -V.sub.Th by the transistor N.sub.4. Further, the node 107 connected to the drains of the transistors N.sub.5 and N.sub. 6, the gate of the transistor N.sub.7, and the output terminal of the capacitor C.sub.ap3 is kept at a potential level V.sub.cc -V.sub.Th by the transistor N.sub.6. In addition, the output terminal Boot of the precharge circuit connected to the drains of the transistors N.sub.7 and N.sub.8 and the output terminal of the capacitor C.sub.ap4 is kept at a potential level V.sub.cc -V.sub.Th by the transistor N.sub.8.

When the input signal I.sub.N1 is caused to change or shift from "H" to "L" level at time t.sub.1, the transistor N.sub.1 is placed in an OFF state. As a result, while the node 101 is seemingly at a potential level of V.sub.cc -V.sub.Th, it is actually in a floating state (also referred to as H floating (high-floating) in this case). Thereafter, at time t.sub.2, when the input signal I.sub.N2 is caused to shift from "H" to "L" level, the capacitor C.sub.ap1 is (electrostatically) coupled with the node 101. As a result, the level of potential on the node 101 shifts from the level V.sub.cc -V.sub.Th to "L" level, but the levels of potentials on the other nodes, e.g., the level of potential on the node 107 or the output terminal Boot remain at the previous level. Further, at time t.sub.3, when the input signal I.sub.N3 is caused to shift from "H" to "L" level, the level of a potential on the node 103 shifts to "H" level and the level of potential on the node 106 shifts to "L" level, and the capacitor C.sub.ap2 is coupled with the node 102. Thus, the potential level of the node 102 is stepped up, so a level of a potential on of node 102 becomes equal to a value of V.sub.cc -V.sub.Th or more. For this reason, the level of the potential on the node 107 connected to the drain of the transistor N.sub.5 becomes equal to the Vcc level. At this time (time t.sub.3), when the level of the input signal Push is caused to shift from "L" to "H" level, the capacitor C.sub.ap4 is (electrostatically) coupled with the output terminal Boot, so the level of voltage (potential) on the output terminal Boot is stepped up. Namely, when the input signal Push is at "L" level a potential, the level of a potential on the output terminal Boot is equal to V.sub.cc -V.sub.th, while when the input signal Push is at "H" level, the level of potential on the output terminal Boot is equal to V.sub.cc. In other words, when the input signal Push is at "L" level, a normal output of the precharge circuit does not exceed the level V.sub.cc. Further, when the input signal Push is at "H" level, the level of the normal output of the precharge circuit does not exceed a level of more than V.sub.cc +V.sub.Th. For this reason, it is required to carry out initialization as shown below.

At time t.sub.4, the level of the input signal I.sub.N1 is caused to shift from "L" to "H" level, and the level of the input signal Push is caused to shift from "H" to "L" level. As a result, the node 101 is kept at the level V.sub.cc -V.sub.Th by the transistor N.sub.1, and the output terminal Boot is kept also at the level V.sub.cc -V.sub.Th. Thereafter, at time t.sub.5, when the level of the input signal I.sub.N2 is caused to shift from "L" to "H" level, the capacitor C.sub.ap1 is coupled with the node 101. As a result, the level of voltage (potential) on the node 101 is stepped up to a certain level more than V.sub.cc +V.sub.Th. Further, at time t.sub.6, When the potential level of the input signal I.sub.N3 is caused to shift from "L" to "H" level, the node 103 is kept at "L" level by the inverter circuit I.sub.NV1, so the capacitor C.sub.ap2 is coupled with the node 102. At this time, since the level of potential on the node 101 is above V.sub.cc +V.sub.Th, the node 102 is kept at the level V.sub.cc by the transistor N.sub.3. On the other hand, the level of potential on the node 106 connected to the output terminal of the NOR circuit NORl shifts from "L" to "H" level. Thus, the capacitor C.sub.ap3 is coupled with the node 107, so the level of voltage (potential) on the node 107 is stepped up to a certain level above V.sub.cc +V.sub.Th. Accordingly, the output terminal Boot is kept at the level Vcc by the transistor N.sub.7.

When the level of the input signal I.sub.N1 is caused to shift from "H" to "L" level at time t.sub.7, and the level of the input signal I.sub.N2 is caused to shift from "H" to "L" level at time t.sub.8, the level of voltage (potential) on the node 101 is stepped or dropped down to a certain level below V.sub.cc -V.sub.Th by the capacitor C.sub.apl. Thereafter, at time t.sub.9, when the potential level of the input signal I.sub.N3 is caused to shift from "H" to "L" level, the level of potential on the node 103 is allowed to shift from "L" to "H" level by the inverter circuit I.sub.NV1, and the level of potential on the node 106 is caused to shift from "H" to "L" level by the inverter circuits I.sub.NV2 and I.sub.NV3 and the NOR circuit NORl. Accordingly, the capacitor C.sub.ap2 is coupled with the node 102, and the capacitor C.sub.ap3 is coupled with the node 107. Thus, the level of voltage (potential) on the node 102 is stepped up by the capacitor C.sub.ap2 from the level V.sub.cc to a certain level above V.sub.cc +V.sub.Th, and the level of voltage (potential) on the node 107 is dropped down by the capacitor C.sub.ap3 to the level V.sub.cc. At this time (time t.sub.9), when the potential level of the input signal Push is caused to shift from "L" to "H" level, the level of voltage (potential) on the output terminal Boot is stepped up from the level V.sub.cc to a certain level above V.sub.cc +V.sub.Th.

Thereafter, when the potential levels of the input signals I.sub.N1, I.sub.N2 and I.sub.N3 are respectively caused to shift from "L" to "H" level at times t.sub.10, t.sub.11 and t.sub.12, and the level of the input signal Push is caused to shift from "H" to "L" at time t.sub.10, the output terminal Boot of the precharge circuit is held at the level V.sub.cc.

As described above, in the conventional precharge circuit, immediately after being powered, the level of potential on the output terminal Boot is below V.sub.cc -V.sub.Th. At this time, even if the potential level of the input signal Push shifts from "L" to "H" level, the level of potential on the output terminal Boot becomes equal to V.sub.cc. Namely, this level is lower than a normal level (above V.sub.cc +V.sub.Th). That potential level is conspicuously dropped by greater degree according to the power supply voltage becoming smaller. As a result, there was the possibility that a device using such a precharge circuit, e.g., a DRAM might be erroneously operated.

Further, it is necessary to carry out initialization in order to provide a normal output level, but the node 101 is in a floating state as previously described for a time period from the time t.sub.1 to the time t.sub.2. Generally, such a node in the floating state may be apt to follow other nodes because of the coupling, etc., causing erroneous operation of the precharge circuit.

This invention has been made in consideration of the above-mentioned problems, and its object is to provide a precharge circuit capable of normally operating without the necessity of carrying out initialization.

The precharge circuit of this invention comprises a first P channel MOS transistor having a gate terminal supplied with a first input signal, and a source terminal and a substrate terminal supplied with an output signal; an N-channel MOS .transistor having a gate terminal supplied with the first input signal, a source terminal to which the ground of a power supply is connected, and a drain terminal to which a drain terminal of the first P-channel MOS transistor is connected; and a second P-channel MOS transistor having a gate terminal to which the drain terminal of the. first P-channel MOS transistor is connected, a source terminal to which a positive potential supply source is connected, and a drain terminal and a substrate terminal, supplied with the output signal.

In accordance with the precharge circuit thus constructed, a .first input signal is inputted to the input terminal of a CMOS inverter comprised of the first P-channel MOS transistor and the N channel MOS transistor. As a result, an output of the CMOS inverter is delivered to the gate terminal of the second P-channel MOS transistor. Thus, when the drain terminal of the second P-channel MOS transistor is used as the output terminal of the precharge circuit of this invention, the precharge circuit of this invention normally operates immediately after it is powered. For this reason, initialization as required in the prior art becomes unnecessary.

In accordance with this invention, the precharge circuit may normally operate without carrying out initialization.

In the accompanying drawings:

FIG. 1 is a circuit diagram showing a conventional precharge circuit;

FIG. 2 is a time chart for explaining the operation of the conventional precharge circuit shown in FIG. 1;

FIG. 3 is a circuit diagram showing a precharge circuit according to an embodiment of this invention; and

FIG. 4 is a time chart for explaining the operation of the precharge circuit shown in FIG. 3.

An embodiment of a precharge circuit according to this invention is shown in FIG. 3. The precharge circuit of this embodiment comprises a CMOS inverter, comprised of an N-channel MOS transistor (hereinafter simply referred to as a transistor) N.sub.1 and a P-channel MOS transistor (hereinafter simply referred to as a transistor) P.sub.1, a P-channel MOS transistor P.sub.2, and an N-channel MOS capacitor (hereinafter referred to as a capacitor) C.sub.ap1. The source terminal of the transistor P.sub.2 is connected to the power supply voltage Vcc terminal, and the drain terminal thereof is connected to the substrate terminal and is also connected to the source terminal of the transistor P.sub.1 of the CMOS inverter. Further, the gate terminal of the transistor P.sub.2 is connected to an intermediate node 11 of the transistors P.sub.1 and N.sub.1, which serves as an output terminal of the CMOS inverter. One end (output terminal) of the capacitor C.sub.ap1 is connected to the output terminal Boot together with the drain terminal of the transistor P.sub.2. Further, a ground potential Vss (=0) is applied to the source terminal of the transistor N.sub.1 of the CMOS inverter, and an input signal I.sub.N1 is applied to the gates of the transistors P.sub.1 and N.sub.1. In addition, another input signal Push is applied to the input terminal of the capacitor C.sub.ap1.

The operation of the above-described precharge circuit will now be described with reference to FIG. 4. In the initial state immediately after the precharge circuit is powered (time t.sub.0), it is now assumed that the input signal I.sub.N1 is at the level Vcc, i.e., in "H" level state, and the input signal Push is at zero level, i.e., in "L" level state. At this time, the transistors P.sub.1 and N.sub.1 constituting the CMOS inverter are turned OFF and ON, respectively. As a result, the potential level of the node 11 becomes equal to the ground level Vss, i.e., "L" level. Thus, the transistor P.sub.2 is turned ON, so the potential level of the output terminal Boot becomes equal to Vcc level. Thereafter, when the level of the input signal I.sub.N1 shifts to "L" level at time t.sub.1 (>t.sub.0), the transistor I.sub.N1 is turned OFF and the transistor P.sub.1 is turned ON. Thus, the potential level of the node 11 shifts from "L" to "H" level, so the transistor P.sub.2 is turned OFF. However, since the output terminal Boot is connected also to the substrate terminal, its potential level is unchanged to maintain the state Vcc.

When the level of the input signal Push changes from "L" to "H" at time t.sub.2 (>t.sub.1), the capacitor C.sub.apl is coupled with the output terminal Boot to step up the potential level of the output terminal Boot so that it is above the level V.sub.cc +V.sub.Th. At this time, the node 11 is charged so that its level becomes equal to substantially the same level as the level of the output terminal Boot through the transistor P.sub.1. Thus, there is no possibility that charges on the output terminal Bopt are discharged to the power supply connected on the source side of the transistor P.sub.2 through the transistor P.sub.2.

Thereafter, at time t.sub.3, when the level of the input signal I.sub.N1 is caused to shift from "L" to "H" level, and the level of the input signal Push is caused to shift from "H" to "L" level, the transistors P.sub.1 and N.sub.1 are turned OFF and ON, respectively. As a result, the potential level of the node 11 shifts to "L" level. Thus, the transistor P.sub.2 is turned ON, so the level of the output terminal Boot becomes equal to V.sub.cc.

As described above, the precharge circuit of this embodiment can normally operate immediately after being powered. Thus, initialization becomes unnecessary.

It is to be noted that since a CMOS inverter is used, no node is placed in a high-floating state.

In addition, the circuit configuration of the precharge circuit according to this invention becomes is simpler than that of the conventional precharge circuit.

As will be understood from the above description, this invention aims at stepping up a voltage level V.sub.cc from a single power supply to a specific level higher by the threshold value V.sub.Th in order to drive a load such as a DRAM, etc. The technology for realizing this by using the configuration of the present P-channel MOS transistor P.sub.2 has been not disclosed until now. Only the prior technology using the above N-channel transistor configuration rather than the P-channel transistor P.sub.2 configuration had been conventionally proposed. However, with an approach which merely replaces the N-channel transistor by the P-channel transistor P.sub.2, there was considerable difficulty in that, when the potential level of the output terminal Boot reaches the power supply voltage level V.sub.cc, discharge begins from the sub-terminal of the transistor P.sub.2, so a desired voltage level above "V.sub.cc +V.sub.Th " cannot be maintained. For this reason, this invention employs a novel configuration and technique such that the P-channel MOS transistor P.sub.1 is turned on immediately before the output drive voltage Boot exceeds the predetermined voltage V.sub. cc due to the drive voltage Boot being raised by the step-up input signal Push, and is turned off when the gate voltage of the P-channel MOS transistor P.sub.1 becomes the same as the drive voltage Boot.

Thus, this invention is characterized by the provision of a main P-channel MOS transistor for raising the dive voltage level up to the power supply voltage level V.sub.cc which serves as a reference, and the provision of a subsidiary P-channel MOS transistor for interrupting the action of the step-up input voltage in order to eliminate the problem in which discharge starts when the main transistor reaches the V.sub.cc level.