Multiplexing Scheme for Modem Control Signals

The present invention is directed to a method and apparatus for transferring modem control and status signals between a host processor and a series of modems. More particularly, the present invention provides a coupling between a host processor and a series of modems that allows the transfer of modem control and status signals in a time-division-multiplexed format in order to reduce the number of wire connections between the host processor and the modems.

One of the more common means of communication between computers and the outside world is through modulators/demodulators (modems). The coupling between a host processor and a modem requires a plurality of different communication wires. These communication wires include ground, status, control, clock, and data signals for the operation of the modem.

As processing speeds increase for computer processors, one computing device can be coupled to several modems via respective line interfaces. Unfortunately, each modem requires its own set of communication wires between itself and its respective line interface. As more modems are coupled to the computer processor, more modem communication wires are needed. For example, in a standard modem protocol, sixteen communication wires are needed for the transfer of just the control, status, clock, and data signals for proper operation. If eight modems are coupled to the computer processor, then a total of at least 128 communications wires are needed. The coupling of so many wires between the line interfaces and a modem distribution panel can be physically difficult.

The present invention is directed to a method and apparatus for reducing the number of required communication wires between a computer processor and a plurality of modems. The respective line interfaces for a plurality of modems are coupled to a remote modem distribution module via a multiplexing serial communication controller. All of the control signals of the module and modems are transmitted between the line interfaces and the serial communication controller which time-division-multiplexes (TDM) the signals before transmitting them to the remote distribution module.

The remote distribution module includes a packet receiver which receives the TDM data as a serial data stream from the multiplexing serial communication controller. In order to insure that the appropriate signals are transferred to the modems at the distribution panel, the first several bits of the serial TDM data stream are checked for a predetermined pattern by packet recognition circuitry. If such a pattern is matched, the TDM data signals are latched and the modem control and status signals are transmitted to the proper modem.

The remote distribution module includes a packet generator which is coupled to each of the modems. Status data to be sent to the line interfaces by the modems and the remote distribution module are transmitted in TDM format by the packet generator. The TDM data is received by the multiplexing serial communication controller and disseminated to the appropriate line interfaces.

In a test mode, the serial communication controller can initiate an automatic loop-back. In this operation, the TDM data passes through the packet receiver to the packet generator and back to the multiplexing serial communication controller. At this point, the controller can verify that the TDM data is being properly received and transmitted between the controller and the remote distribution module.

FIG. 1 is a block diagram illustrating a coupling between a line interface card and a remote distribution panel.

FIG. 2 is a block diagram for a fan out modem connection between the line interface card and remote distribution panel of FIG. 1.

FIG. 3 is a block diagram of receiving and transmitting circuitry of the remote distribution panel illustrated in FIG. 2.

FIGS. 4A & 4B together provide a circuit diagram of the packet receiver of the circuitry illustrated in FIG. 3.

FIGS. 5A-5D together provide a circuit diagram for the packet generator of the circuitry illustrated in FIG. 3.

Referring to FIG. 1, the coupling between a line interface card 1 and a remote distribution panel 3 is shown. The line interface card can be a 64K bps low speed synchronous transmission line interface card. The line interface card 1 is coupled to the remote distribution panel 3 which is provided with eight serial ports 5, each to be coupled to a modem to provide eight separate and independent low speed communication channels for the line interface card 1. The distribution panel 3 supports, e.g., connectivity for one of the V.11/EIA-RS422, V.35 and V.28/EIA-RS-232-D modem control and signalling standards having a range of line speeds of from 1.2 to 64K bps. The ports 5 are coupled by a 50 wire cable 77 to a line interface 9 which comprises three Motorola MC68302 Integrated Multi-Protocol Processors, each of which comprises three line interfaces 11. The MC68302 processors support 16 and 32 bit CRC generation and checking, HDLC and LAPB data link layer protocols and NRZ and NRZI data encoding formats.

The line interface card 1 utilizes a subset of each of the line interface processors 11, namely the three serial communication controllers (SCC) in each processor comprising a line interface 11, for a total of nine SCC facilities. Eight of the SCC's are used for serial communication control, each dedicated to one of the eight ports 5 of the distribution panel 3. The ninth SCC is used to multiplex the modem and module signals required by the eight modems that are to be coupled to the ports 5 across a subset of the wires of the 50 wire cable 7. The line interface card 1 may also comprise a memory 13, such as a RAM, and a processor 15 coupled to a central bus 17. The memory 13 and processor 15 could be used to facilitate control of the line interface card 1. Additionally, the central bus 17 may be coupled to a system bus 21 via a bus interface 19. This would allow other components coupled to the system bus 21 to communicate with the modems coupled to the remote distribution panel 3.

In general, a modem requires the transfer of a plurality (e.g., sixteen) of signals between the modem and the line interface card 1 to provide full modem control data communications. The signals include control, data, clock and status signals. The remote distribution panel 3 is coupled to eight modems. In addition to the sixteen control, data, clock, and status signals sent between the line interface card 1 and the modem, ground and voltage level signals are required as well. The line interface card 1 is coupled directly to the remote distribution panel 3 via a 50 wire cable 7. If the remote distribution panel 3 is coupled to eight modems, the transfer of at least 128 signals is required between the line interface card 1 and the distribution panel 3. Because of the difficulty in hard wiring such a large number of signal lines, the number is reduced to thirty six using a Time Division Multiplexing (TDM) scheme according to the present invention.

Referring to FIG. 2, a general block diagram of the connection between the remote panel 3 and the line interface card 1 is shown. The line interface card 1 is coupled to the remote distribution panel 3 through a 50 wire cable 7 which comprises fifty signal lines 31-53. The first fourteen lines are standard ground and voltage connections. Six of the lines are for ground 31, four of the lines are for +5 volts 33, two of the lines are for +12 volts 35, and two of the lines are for -12 volts 37.

In this example, eight modems are to be coupled to the remote distribution panel 3. Eight lines are dedicated for the transmit data 39, one for each modem, and eight lines are dedicated for receive data 41, one for each modem. In addition, eight lines are dedicated for the received transmit clocks 43 one for each modem, and eight lines are dedicated for the received receive clocks 45. There is a reset line 47, which resets the remote distribution panel 3 when asserted. All modem control and status signals are transferred on TDM transmit and receive lines 51 and 53. A signal line is dedicated for the clock signal 49 of the lines 51 and 53.

The transmit data 39, receive data 41, transmit clock 43, and receive clock 45 signal lines are all coupled to their respective modems through driver receiver interfaces (not shown). The transmit line 51 is controlled by one of the SCCs of one of the MC68302 Integrated Multi-Protocol Processors on the line interface card 1, as described above.

The SCC dedicated to the control of the transmit line 51 is configured to operate in a BISYNC mode of operation. In a BISYNC mode of operation, one serial channel is used for receiving and transmitting data. The actual operation of the serial channel is determined by the toggling of an ownership bit in the MC68302 processor. The processor sends out the contents of preselected buffers, bit serially, to the SCC pin. In this embodiment, two 10-byte buffer spaces are required for transmitting and receiving data. Modem and module control information is written from the line interfaces to the transmit buffer space. Conversely, modem and module status information is read from the receive buffer space. The dedicated SCC transmits the contents of the transmit buffers to the respective SCC pin of the processor. This pin is directly coupled to the TDM transmit line 51 shown in FIG. 2.

Referring to FIG. 3, the receiving and transmitting circuitry of the remote distribution panel 3 is shown. The signal clock 49 (see FIG. 2) is coupled through two inverters 55 and 57 to a packet receiver 59. The TDM transmit line 51 (see FIG. 2) is also coupled to the packet receiver 59. The packet receiver 59 comprises a series of shift registers which shift in the contents of the serially transmitted control signals from transmit buffers of the line interface card 1. The TDM transmit line 51 transmits modem and module control signals in a TDM format. The entire string of transmit control signals captured by the shift registers is in a packet format in the shift registers. The first eight bits of the packet have a certain bit pattern, which acts as a flag to identify the string as a valid packet. In this embodiment, the bit pattern flag is 01111110. Since the packet receiver 59 comprises shift registers, the first eight bits of a data string are shifted into packet recognition circuitry 61. If the first eight bits match the preselected bit pattern, 01111110, the packet recognition circuitry 61 sends an enabling signal to a latch controller 63 and a load controller 70.

If the packet in the packet receiver 59 is valid, the latch controller 63 will send a latch enable signal to a modem control latch 65. The modem control latch 65 latches the modem control signals 65a-e from the shift registers to the respective modems. These signals are then sent on to the appropriate modem using modem control signal drivers 67. In this embodiment there are five different modem control signals 65a-e for each modem coupled to the remote distribution panel 3: RTS (Request to Send) 65a, DTR (Data Terminal Ready) 65b, DSRS (Data Speed Rate Selector) 65c, RL (Remote Loopback) 65d, and LL (Local Loopback) 65e.

In addition to modem control signals 65a-e, the transmit control string also includes three different module control signals 65f-h. Clock.sub.-- 113.sub.-- On 65f is an enabling signal for a 64khz clock which is coupled to a CCITT 113 pin external serial interface connector. There is one Clock.sub.-- 113.sub.-- On signal 65f for each modem. DCD.sub.-- CLR 65g is used to reset a DCD ON detection circuit, as described above. There is one DCD.sub.-- CLR signal 65g for each modem. Remote Internal Loopback (RIL) 65h places the receiving/transmitting circuitry of FIG. 3 into an internal loopback mode. This allows the connectivity between the line interface card i and the distribution panel 3 to be analyzed.

The packet receiver 59 is coupled to a module control signal latch 69 which latches the aforementioned RIL signal 65h. The module control signal latch 69 also receives packet recognition information from the latch controller 63. Upon receipt of a valid RIL signal 65h at the module control signal latch 69, an inhibit signal is sent to the latch controller 63, thus inhibiting the latching of data in the packet receiver 59.

Clock.sub.-- 113 On 65f and DCD.sub.-- CRL 65g are latched in the modem control latch 65. The Clock.sub.-- 113.sub.-- On signals 65f are sent to CCITT 113 control circuitry 71 which, in turn is coupled to CCITT 113 drivers 73. The clock signal 75 is coupled to a divider circuit 75 which converts this clock signal into a 64khz clock for the CCITT 113 drivers 73. The DCD.sub.-- CLR signals 65g are sent to the DCD-ON latches 77. Each channel has an individual circuit which sets a flag whenever DCD changes from OFF to ON. This flag remains set until the DCD.sub.-- CLR signal 65g is received for that particular channel.

The packet generator 79 is coupled to the inverted clock signal 49. It is also coupled to the packet recognition circuitry 61 in order to loopback transmit data during a RIL test. Flag circuitry 81 transmits a flag byte 81a to the packet generator 79 in order to preset the first eight bits of the TDM Receive Data 53 to the packet flag, 01111110. Module status circuitry 83 is coupled to the packet generator to provide two types of module status. Module Identification (MID) 83a is a three bit value indicating the electrical interface standard currently being supported (e.g., V.28, V.11, V.35). Module Revision Number (MRN) 83b is also a three bit value indicating the hardware revision number of the distribution panel.

Modem status signal receivers 85 are also coupled to the packet generator 79. The receivers 85 provide six different modem status signals 85a-f received from each modem. These signals are as follows: CTS (Clear to Send) 85a, DSR (Data Set Ready) 85b, DCD (Data Carrier Detect) 85c, SMI (Speed Mode Indicate) 85d, RI (Ring Indicate) 85e, and TI (Test Indicate). The modem status signal receivers 85 also provide a Data Carrier Detect On (DCD ON) signal to the DCD-ON latches 77. The purpose of the DCD ON signals is to insure detection of a change of state in the DCD signal (from off to on). When handling minimum size packets in a half duplex mode of operation, a window exists in which a legitimate packet may have been received and rejected because the assertion of the DCD signal was missed. This signal is set when DCD changes from the OFF to the ON state only. It remains set until the reset signal is given.

The reset signal 47 is coupled directly to the module control signal latch 69 and the DCD-ON latches 77. Also, the module control signal latch 69 can send a load inhibit signal to the load controller 70 thus disabling the packet generator 79 in the case of a RIL signal. In that situation, the packet generator 79 merely sends back the transmit data from the packet recognition circuitry 61.

Referring to FIGS. 4A and 4B, a circuit diagram of the packet receiver 59 is shown. The packet receiver 59 comprises a plurality of shift registers 101-119. Each shift register can be, but is not limited to, a 74LS164 chip manufactured by National Semiconductor Corp. The clock 49 is coupled to each of the shift registers 101-119. The transmit data line 51 is coupled to the first input of the first shift register 101.

Data serially received from the transmit line is continuously shifted through the shift registers 101-119 and into the packet recognition circuitry 61. Once the appropriate 01111110 bit pattern flag has been shifted into the shift register 121 of the packet recognition circuitry, the values in the previous shift registers 101-119 are assumed valid and are latched into the signal latches 65 and 69 (see FIG. 4B). As an option, the reset signal line 47 can be coupled to all shift registers 101-121 to insure no erroneous data gets to the modems. It is important to note that no more than five control signals can be bit-serially adjacent to one another. This insures that the packet recognition circuitry 61 will not mistake control data as a packet flag (which comprises six consecutive "1" bits in this embodiment).

Referring to FIGS. 5A-5D, a circuit diagram of the packet generator 79 is shown. The packet generator 79 also comprises a series of shift registers 201-221 which can be, but are not limited to, 74LS166 chips manufactured by National Semiconductor. Flag and status data are constantly updated by the modems at the respective inputs to the shift registers 201-221, as illustrated in FIGS. 5A-5D. To insure that data is received and transmitted at different times in the remote distribution panel 3, the inverse of the clock 49 is coupled to each of the shift registers 201-221. Also, as an option, the reset signal line 47 can be coupled to each of the shift registers 201-221.

The high order bit on the last shift register is directly coupled to the TDM receive data line 53. The load controller 70 (see FIG. 4B) is directly coupled to each of the shift registers 201-221. An enabling signal from the load controller 70 causes the shift registers 201-221 to load the flag, status and control signals coupled to the respective individual registers of the shift registers 201-221 via the modem status signal receiver 85, the flag circuitry 81 and the module status circuitry 83 (see FIG. 3). The data loaded into the shift registers is then shifted out serially to the receive data line 53. It should be readily apparent that the MC68302 processor should be appropriately programmed so that the correct status and control signals are read from and written to the proper buffers.