Circuit for Performing a Parallel Write Test of a Wide Multiple Byte for Use in a Semiconductor Memory Device

The present invention generally relates to a write chain circuit for a parallel test in a high density semiconductor memory device and, more particularly, to multiple byte wide parallel write circuits in which the number of data bits, written during one cycle, is not limited to the number of data buses, and which is capable of simultaneously writing a number of data bits equal to the number of data input/output (I/O) lines.

In general, a semiconductor memory device such as, in particular, a dynamic random access memory (DRAM), reads/writes in parallel a number of data bits equal to the number of data buses. Accordingly, the data having a number of bits equal to the number of data buses are written in parallel during one cycle when the parallel write test is made in the semiconductor memory device. However, when there is a need to expand the semiconductor memory device capacity, the number of data bits must be increased accordingly so as to perform the above parallel write test properly, in the same manner as presented above. Therefore, when its capacity is expanded, the semiconductor memory device widens its dimension (chip area) greatly because of a necessity for increasing the number of data buses. In addition, as the number of the data bits increases, the load of the semiconductor memory device increases correspondingly. In conclusion, it is a drawback of the prior art device that the data processing speed is lowered when performing the write test, especially in a expanded semiconductor memory device.

An object of the present invention is therefore to provide a multiple byte wide parallel write circuit capable of writing, at a same time, data having the same number of bits as the number of input/output (I/O) lines, without limiting the number of the data bits, which are written during one write cycle, to the number of data buses.

Another object of the present invention is to provide a multiple byte wide parallel write circuit for decreasing the overall write testing time by greatly increasing the number of parallel write bits, without increasing the dimension for layout thereof and the load carried thereon.

According to one aspect of the present invention to achieve the object and features of the invention, a multiple byte wide parallel write circuit for use in a semiconductor memory device, the write circuit has a number of cell array blocks comprised of a plurality of I/O lines, each I/O line being comprised in pairs, and a plurality of data input buffers for buffering to respective data bus lines the input data received from data input pads or the input data received from data input/output multiplexed pads, in response to a clock pulse applied from a buffer input control clock generator, includes a plurality of data bus selectors for selecting the data buses which are output lines of the data input buffers on the basis of a respective data bus selector control signal, a plurality of clock pulse generators for generating a control clock for an individual data input driver on the basis of a test mode enable signal and a column/row address signal, and a plurality of individual data input drivers for driving respective output of the data bus selectors and for applying the output driven to the entire input/output (I/O) lines at a same time, the I/O lines being connected to the respective individual data input driver one to one, on the basis of the clock pulses generated from the clock pulse generators.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:

FIG. 1 is schematic diagram of a multiple byte wide parallel write circuit according to the present invention;

FIG. 2 is a detailed circuit illustrating one of the data bus selectors (A.sub.1 -A.sub.4) of FIG. 1 in detail according to the present invention;

FIG. 3 is a detailed circuit illustrating one of the clock pulse generators (AA.sub.1 -AA.sub.4) of FIG. 1; and

FIG. 4 is a detailed circuit of an individual one of the data input drivers (B.sub.1 -B.sub.16) of FIG. 1.

An embodiment of the multiple byte wide parallel write circuit for high speed memory test will now be described with reference to the accompanying drawings, by way of an example. Throughout the drawings, like reference symbols are used to designate like or equivalent parts or portions, for simplicity of illustration and explanation.

With particular reference to FIG. 1, cell array blocks 10-40 have a plurality of I/O lines 100 made in pairs respectively. Data input buffers C.sub.1 -C.sub.4 buff the input data received from a data input pad D.sub.5 or the input data received from data input/output multiplexed pads D.sub.1 -D.sub.4 and provide the buffered data to data bus lines 200 made in pairs respectively, on the basis of a buffer input clock signal 300. Data bus selectors A.sub.1 -A.sub.4 select the data Ab.sub.i (AB.sub.1 -AB.sub.4) on the output lines of the data input buffers C.sub.1 -C.sub.4, in response to the clock signal received from the data bus selector control signal generator 500. Clock pulse generators AA.sub.1 -AA.sub.4 generate control clock pulses for controlling a number of individual data input drivers B.sub.1 -B.sub.16 which drive the respective data passed through the data bus selectors A.sub.1 -A.sub.4 to be suited for input of the cell array blocks 10-40, on the basis of a test mode enable clock signal and column/row address signal. According to the control clock pulses generated from the clock pulse generators AA.sub.1 -AA.sub.4, the individual data input drivers B.sub.1 -B.sub.16 drive the data selected by the data bus selectors A.sub.1 -A.sub.4 and then provide the driven data to the entire I/O lines 100 at a same time, the I/O lines being connected to the I/O lines of the cell array blocks 10-40 one to one.

Referring now to FIG. 2, one of the data bus selectors A.sub.1 -A.sub.4 of FIG. 1 is illustrated in detail in accordance with the present invention. In the drawing, the data buses AB.sub.i (AB.sub.1 -AB.sub.4) made in pairs of data lines A, A are connected to any one of either input of NOR gates NO.sub.1, NO.sub.2, respectively. The other input terminals of the NOR gates NO.sub.1, NO.sub.2 are commonly connected to the clock signal generated from the data bus selector control clock pulse generator 500. In addition, the respective output of the NOR gates NO.sub.1, NO.sub.2 are connected to inverters N.sub.1, N.sub.2 so that the respective output of the inverters N.sub.1, N.sub.2 is coupled to the individual data input drivers B.sub.1 -B.sub.16.

Referring to FIG. 3, one of the clock pulse generators AA.sub.1 -AA.sub.4 of FIG. 1 is illustrated according to the present invention, wherein the column/row address terminals CAi, CAi, RAi, RAi are coupled to NAND gates NA.sub.1 -NA.sub.4 as illustrated, and a test mode enable terminal FTE is coupled to any one of the input terminals of each of the NAND gates NA.sub.5 -NA.sub.8 of which the other input terminals are coupled to respective output terminals of the NAND gates NA.sub.1 -NA.sub.4. Then, the respective output terminals of the NAND gates NA.sub.5 -NA.sub.8 are coupled to the control clock lines 400 (AA.sub.0k -AA.sub.3k) which are the input of the individual data input drivers B.sub.1 -B.sub.16.

Referring further to FIG. 4, the individual data input drivers B.sub.1 -B.sub.16 are illustrated according to the present invention, in which a line AA.sub.ik of the control clock pulse lines 400 is connected to the gates of the P-channel MOS (PMOS) transistors T.sub.1, T.sub.2 and, at the same time, connected to the gates of the N-channel MOS (NMOS) transistors T.sub.5, T.sub.6. Then, a pair of data lines A', A' are the output of the data bus selectors A.sub.1 -A.sub.4 are connected to the respective source of the NMOS transistors T.sub.5, T.sub.6. The gate of a PMOS transistor T.sub.3 and the input of an inverter N.sub.62 are commonly connected to a first node 41 to which the respective drains of the PMOS transistor T.sub.1 and the NMOS transistor T.sub.5 are also connected. In the same manner, the gate of a PMOS transistor T.sub.4 and the input of an inverter N.sub.61 are commonly connected to a second node 42 to which the respective drains of the PMOS transistor T.sub.2 and the NMOS transistor T.sub.6 are also connected. Thereafter, the output signals of the inverters N.sub.61, N.sub.62 are respectively coupled to the gates of NMOS transistors T.sub.7, T.sub.8. Thus, a third node 43 formed between the respective drains of the PMOS transistor T.sub.3 and the NMOS transistor T.sub.7, and a fourth node 44 formed between the respective drains of the PMOS transistor T.sub.4 and NMOS transistor T.sub.8 are respectively connected one of the I/O lines 100 which are, at the same time, connected to the cell array 10-40 by way of the respective bit lines thereof so as to access the memory cells.

The embodiment of the invention will be described more specifically hereinbelow with reference to FIG. 1 through FIG. 4. For the convenience of explaining the illustrated embodiment, only two groups of cell array blocks 10-40 are described out of a plurality of the cell array blocks as illustrated in FIG. 1. The plurality of data I/O lines 100 of the cell array blocks 10-40 are coupled to the bit lines of the cell array blocks 10-40, thereby to access the memory cells. The respective data I/O lines 100 are driven by the output of the individual data input drivers B.sub.1 -B.sub.16 and the respective blocks receive the data selected by the data bus selectors A.sub.1 -A.sub.4 on the basis of the control clock pulse generated from the control clock pulse generators AA.sub.1 -AA.sub.4. The data bus selectors A.sub.1 -A.sub.4 select the data on the data buses AB.sub.i (AB.sub.1 -AB.sub.4) and provide them to the individual data input drivers B.sub.1 -B.sub.16, on the basis of the clock pulse applied from the data bus selector control signal generator 500. Since the data input buffers C.sub.1 -C.sub.4 are coupled to the respective data bus lines AB.sub.1 -AB.sub.4, the data bus lines AB.sub.1 -AB.sub.4 are driven by the data received from the data input pad D.sub.5 and the data I/O multiplexed pads D.sub.1 -D.sub.4, on the basis of the buffer input clock signal 300. In other words, the buffer input clock signal 300 plays the role of providing to the data input buffers C.sub.1 -C.sub.4 the data received from the data I/O multiplexed pads D.sub.1 -D.sub.4 and the data input pad D.sub.5. Since the data bus selectors A.sub.1 -A.sub.4 are connected to the existing data bus lines AB.sub.1 -AB.sub.4 and the individual data input drivers B.sub.1 -B.sub.16 prepared in this embodiment of the invention are the same in number with the data I/O lines 100, if one or more than one cell array blocks 10-40 is activated, the data may be written in parallel, at a same time, on the cell array blocks 10-40 through the entire data I/O lines 100.

In more detail to the parallel test operation, the data received from the data I/O multiplexed pads D.sub.1 -D.sub.4 and the data received from the data input pad D.sub.5 are buffered in the data input buffers C.sub.1 -C.sub.4 and then provided to the data bus lines 200, in response to the buffer input clock signal 300. Then, the data on the data bus lines 200 is selected correspondingly by the data bus selectors A.sub.1 -A.sub.4, in response to the clock pulse of the data bus selector control clock generator 500. That is to say, as best illustrated in FIG. 2, the data on the data lines A, A of the data buses AB.sub.i (AB.sub.1 -AB.sub.4) is selected by the NOR gates NO.sub.1, NO.sub.2 dependently upon the logic state of the data bus selector control clock generator 500. Therefore, it is noted that when the data applied to the two input terminals of the respective NOR gates NO.sub.1, NO.sub.2 is both at the logic "low" state, the NOR gates NO.sub.1, NO.sub.2 produce the logic "high" state to the inverters N.sub.1, N.sub.2 by which the previous logic states are inverted. For example, if the clock signal from the data bus selector control clock generator 500 is logic "low" and the data on the input line A of the NOR gate NO.sub.1 is at the logic "high" state, then the NOR gate NO.sub.1 generates the logic "low" state to the inverter N.sub.1 which inverts the logic states to logic "high" state. In this case, the data on the data lines A, A is complementary to each other, therefore the output of the circuit is also complementary, i.e., with the same logic condition as given above, the output of the inverter N.sub.2 will be at the logic "low" state. Thereafter, the output data is transferred to the individual data input drivers B.sub.1 -B.sub.16.

The clock pulse generators AA.sub.1 -AA.sub.4, as best illustrated in FIG. 3, generate the clock pulse for controlling the individual data input drivers B.sub.1 -B.sub.16, in response to the signal applied to the test mode enable terminal FTE. In operation, the signals inputted through the column/row address terminals CAi, CAi, RAi, RAi are first processed logically by the NAND gates NA.sub.1 -NA.sub.4, and then the output signals are logically processed by the NAND gates NA.sub.5 -NA.sub.8, in response to the enable clock pulse inputted through the test mode enable terminal FTE so as to be transferred to the individual data input driver control clock pulse lines 400 (AA.sub.0k -AA.sub.3k).

The output signals generated from the individual data input control clock pulse lines AA.sub.0K -AA.sub.3k are transferred to one of the individual data input drivers B.sub.1 -B.sub.16, which are best illustrated in FIG. 4. That is, the output signals AA.sub.0k -AA.sub.3k of FIG. 3 are applied to the PMOS transistors T.sub.1, T.sub.2 and NMOS transistor T.sub.5, T.sub.6 of FIG. 4, as the control clock pulse of the individual data input drivers B.sub.1 -B.sub.16. For example, if an individual data driver control clock pulse AA.sub.ik is at the logic "high" state, the NMOS transistors T.sub.5, T.sub.6 are turned on and a predetermined data of the data lines A', A' (for example, the logic "high" on the data line A' and the logic "low" on the data line A' are provided) of the data bus selectors A.sub.1 -A.sub.4 will be respectively passed to the first and second nodes 41, 42 by way of the NMOS transistors T.sub.5, T.sub.6. Then, the first node 41 becomes the logic "high" state while the second node 42 becomes the logic "low" state, and the PMOS transistor T.sub.3 and the NMOS transistor T.sub.8 are turned off because of the logic "high" state of the first node 41. On the other hand, the PMOS transistor T.sub.4 and the NMOS transistor T.sub.7 are turned on because of the logic "low" state of the second node 42. Thus, the logic states of the data lines A', A' are inverted in the individual data input buffers B.sub.1 -B.sub.16 and transferred to the cell array blocks 10-40 by way of the data I/O lines 100 (I/O,I/O) so as to be written into a corresponding memory cell.

On the other hand, if the individual data driver control clock pulse AA.sub.ik is at the logic "low" state, the PMOS transistors T.sub.1, T.sub.2 are turned on while the NMOS transistors T.sub.5, T.sub.6 are turned off, causing the first node 41 and the second node 42 to be both at the logic "high" state. At this moment, since the NMOS transistors T.sub.7, T.sub.8 and the PMOS transistors T.sub.3, T.sub.4 are all turned off, the I/O lines 100 are cut off from the individual data input buffers B.sub.1 -B.sub.16.

Therefore, it is understood that since the respective data bus lines AB.sub.i (AB.sub.1 -AB.sub.4) are driven by the data input buffers C.sub.1 -C.sub.4 which can be enabled by the buffer input clock signal 300 during the parallel test mode and the respective data bus selectors A.sub.1 -A.sub.4 are driven according to the control clock inputted from the data bus selector control clock generator 500, the data on the data bus lines AB.sub.i (AB.sub.1 -AB.sub.4) is transferred to the individual data input drivers B.sub.1 -B.sub.16 and is written into a memory cell. In addition, the data provided to the individual data input drivers B.sub.1 -B.sub.16 is driven in the manner that is described in detail in connection with FIG. 4 and is saved (written) into the cell array blocks 10-40 through the respective data I/O lines 100. In a normal read/write mode, the control clock pulse received through the data bus selector control clock generator 500 enables one of the data bus selectors A.sub.1 -A.sub.4 and the control clock pulse of the individual data input driver control clock generators AA.sub.1 -AA.sub.4 enables again one of the individual data input drivers B.sub.1 -B.sub.16, thereby finally the data may be saved (written) into one of the cell array blocks 10-40.

As is described above, the improvement writes into a memory cell the data having a greater number of bit lines than that of the data buses, without increasing the layout area nor increasing the load on the bus lines. Therefore, the invention has an advantage of decreasing the time-loss during the write test in a semiconductor memory device and of elevating the processing speed of the write test without increasing the layout area and the load on the bus lines.