US 5,202,591 AGrant
Dynamic Circuit Disguise for Microelectronic Integrated Digital Logic Circuits
Issue Date:1993-04-13
•13 Claims
•5 Drawing Sheets
Abstract
Focussed ion beam (FIB) implants (38,40) are used to set the threshold voltages of metal-oxide-semiconductor field-effect transistors (MOSFETs) in a selected logic gate (34,36) in a microelectronic integrated digital logic circuit (31) such that the direct current (DC) transfer function and logic thresholds are essentially the same as for another logic gate (30,32) which is not altered by FIB implants, but the switching speed is greatly reduced. This causes the altered gate (34,36) to switch in an apparently normal manner when tested under DC or low speed conditions, but to not switch at normal operating speed. The altered or disguised gate (34,36) is thereby always on or always off at the normal operating speed, whereas the unaltered gate (30,32) switches in the normal manner. This impedes attempts at reverse engineering since the circuit (31) operates differently under test and operating conditions, and the true logic functions of the gate (34,36) cannot be determined by known low speed test procedures.
Metadata
Assignee
- Hughes Aircraft Company
Inventor
- Robert H. Walden
Application Information
Application Number:US 7427999
Filing Date:1991-08-09
Priority Date:1991-08-09
Art Unit:259
Classifications
IPC:
H03K 1716H03K 1920
Field of Search:
307450;465;468;443
Patent Drawings (5 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a method for disguising a microelectronic integrated digital logic circuit which deters attempts to analyze the logical structure of the circuit by reverse engineering.
2. Description of the Related Art
A method for protecting hardware integrated circuits or microcircuits against unauthorized copying and/or use is described in U.S. Pat. No. 4,766,516, entitled "Method and Apparatus for Securing Integrated Circuits from Unauthorized Copying and Use", issued Aug. 23, 1988, to F. Ozdemir et al, and assigned to Hughes Aircraft Company, the assignee of the present invention. According to this technique, at least one additional circuit element that does not contribute towards the function of an integrated circuit (IC), but rather inhibits the proper functioning of the IC in case of an attempted copying, analysis, or other unauthorized use, is fabricated along with the overall IC.
The identities of the additional circuit elements are disguised by forming them with the visible appearance of apparent elements, but with physical modifications that are not readily visible to a copyist but cause them to function in a different manner. Such modifications include very narrow open circuit cuts in metallized connection lines, preferably made with a focused ion beam (FIB) or laser beam; disordering the lattice structure or changing the doping level of a semiconductor region, preferably with a FIB; and injecting electrical charge into a semiconductor region, preferably with an electron beam.
The FIB modifications include implantation of ions into the channel regions of field effect transistors (FETs) to change the threshold voltages thereof and cause them to be always on or always off. The modifications themselves are virtually undetectable. However, it is at least theoretically possible to analyze the actual logical functions of the altered FETs using digital computers programmed to perform sophisticated permutational analysis algorithms.
Summary of the Invention
Reverse engineering utilizes internal probing which adds capacitance to the circuit nodes under test. This requires that the testing be performed at DC or very low clock speeds to enable the added capacitance to charge sufficiently that the logic gates themselves will not function erroneously. The present invention provides a method for using FIB implants to set the threshold voltages of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) in selected logic gates in a microelectronic integrated digital logic circuit such that the direct current (DC) transfer function and logic thresholds are essentially the same as for the other logic gates (not altered by FIB implants), but the switching speeds are greatly reduced (preferably by a factor of at least ten). This causes the altered gates to switch in an apparently normal manner when tested under DC or low speed conditions, but to not switch at normal operating speed. The altered gates are thereby always on or always off at the normal operating speed.
Altering some of the FETs in this manner deters attempts at reverse engineering since the circuit operates differently under test and operating conditions, and the true logic functions of the gates cannot be determined by known low speed test procedures.
A microelectronic integrated digital logic circuit embodying the present invention comprises a first microelectronic digital logic switching element having a first maximum switching speed which is higher than a predetermined switching speed at which the circuit is designed to operate. A second microelectronic digital logic switching element is logically associated with the first switching element and has a second maximum switching speed which is lower than the predetermined switching speed such that the first and second switching elements both switch at switching speeds lower than the second switching speed, and only the first switching element switches at the predetermined switching speed.
In a preferred embodiment of the invention, the switching elements include n-channel metal-oxide-semiconductor (NMOS) FETs connected in a depletion mode active load configuration. In another preferred embodiment of the invention, the switching elements include complementary metal-oxide-semiconductor (CMOS) FETs connected in a symmetrical configuration.
In a method of fabricating a microelectronic integrated digital logic circuit embodying the present invention, the threshold voltages of the FETs in the second switching element are altered by FIB implantation to be closer to the switching voltage thereof than in the first switching element, thereby causing the second switching speed to be lower than the first switching speed. The switching voltages of the first and second switching elements are preferably equal, causing the DC transfer functions and logical thresholds of the switching elements to be essentially similar.
These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.
Description of the Drawings
FIG. 1 is an electrical schematic diagram illustrating an known NMOS depletion mode load inverter configuration for the purpose of describing the principles of the present invention;
FIG. 2 is a graph illustrating the voltage transfer function for the inverter of FIG. 1;
FIG. 3 is a graph illustrating how the voltage transfer function for the inverter of FIG. 1 is altered in accordance with the present invention;
FIG. 4 is a graph illustrating the switching times for the unaltered and altered inverters;
FIG. 5 is an electrical schematic diagram illustrating an NMOS logic gate arrangement embodying the present invention;
FIG. 6 is an electrical schematic diagram illustrating an known CMOS inverter configuration for the purpose of describing the principles of the present invention;
FIG. 7 is an electrical schematic diagram illustrating an exemplary CMOS logic gate arrangement embodying the present invention;
FIGS. 8a to 8d are simplified diagrams illustrating a method of fabricating an NMOS microelectronic integrated digital logic circuit embodying the present invention; and
FIGS. 9a to 9d are simplified diagrams illustrating a method of fabricating a CMOS microelectronic integrated digital logic circuit embodying the present invention.
Detailed Description of the Invention
Referring to FIG. 1 of the drawing, a known inverter circuit 10 includes an n-channel enhancement mode (NMOS) driver FET M1 connected in series circuit with an n-channel depletion mode NMOS load FET M2 between a drain supply V.sub.DD and ground. The gate of the load FET M2 is connected to the junction of the FETs M1 and M2 to provide an active load configuration. The driver FET M1 has a threshold voltage V.sub.TDR which is more positive than zero, whereas the load FET M2 has been altered by ion implantation to have a threshold voltage V.sub.TLD which is more negative than zero. The output capacitance of the inverter circuit 10 and the capacitances of the following logic circuits (not shown) are lumped together and symbolically illustrated as a capacitor C.
The DC transfer function of the inverter circuit 10 is illustrated in FIG. 2 as a curve 12. The output voltage V.sub.OUT is approximately equal to the drain supply voltage V.sub.DD for an input voltage V.sub.IN of zero, and approaches zero as the input voltage V.sub.IN increases toward V.sub.DD. Both FETs M1 and M2 are in saturation in a region 14 of the curve 12 between the values of V.sub.OUT =V.sub.DD +V.sub.TLD and V.sub.OUT =V.sub.IN -V.sub.TDR. A line representing V.sub.OUT =V.sub.IN intersects the curve 12 at a point V.sub.IN0 which is designated as a switch point or switching voltage of the inverter circuit 10. It will be noted that the threshold voltage V.sub.TDR of the driver FET M1 is measured in the positive direction from zero, whereas the threshold voltage V.sub.TLD of the load FET M2 is measured in the negative direction from V.sub.DD.
The output voltage V.sub.OUT begins to transition from high to low as the input voltage V.sub.IN increases from zero through the voltage V.sub.TDR, and begins to transition from low to high as the input voltage V.sub.IN decreases from V.sub.DD through the voltage V.sub.DD -V.sub.TLD. The switch from high to low and vice-versa is approximately centered on the switching voltage V.sub.IN0. The absolute values of the threshold voltages V.sub.TDR and V.sub.TLD are approximately equal, but will not be exactly equal due to non-linearities in the transfer curve 12, and are different from the switching voltage V.sub.IN0 by approximately equal voltages. In other words, the voltages V.sub.TDR and V.sub.DD -V.sub.TLD are spaced approximately symmetrically about the switching voltage V.sub.IN0.
The current I.sub.LD through the load FET M2 in the saturation region 14 is given as ##EQU1## where W.sub.LD is the channel width of the load FET M2. L is the channel length, K.sub.N is the transconductance parameter, and .lambda. is the channel-length modulation parameter of the FETs M1 and M2 (assumed to be equal).
The current I.sub.DR through the driver FET M1 in the saturation region 14 is given as ##EQU2## where W.sub.DR is the channel width of the driver FET M1. equating the currents I.sub.LD =I.sub.DR gives ##EQU3## where V.sub.IN -V.sub.TDR .ltoreq.V.sub.OUT .ltoreq.V.sub.DD +V.sub.TLD.
Setting V.sub.OUT =V.sub.V.sub.IN =V.sub.IN0 produces the relationship between V.sub.TDR and V.sub.TLD which keeps the switching voltage V.sub.IN0 constant. This may be expressed as ##EQU4##
The switching speed of the inverter circuit 10 may be approximated in terms of the rise time T.sub.R, based on the differential relationship .DELTA.V/.DELTA.T=I.sub.LD /C, where T.sub.R =.DELTA.T and the channel-length modulation .lambda. is taken as zero. ##EQU5##
This may be rewritten as ##EQU6##
Equation (6) shows that T.sub.R is inversely proportional to the square of the threshold voltage V.sub.TLD of the load FET M2. Thus, the value of V.sub.TLD which produces a selected rise time T.sub.R (and corresponding switching speed) may be approximated by ##EQU7##
The corresponding value of the threshold voltage V.sub.TDR of the driver FET M1 which maintains the switching voltage V.sub.IN0 approximately constant is given as ##EQU8##
FIG. 3 illustrates how the inverter circuit 10 can be modified or altered in accordance with the present invention to switch only below a maximum switching speed which is lower, preferably at least ten times lower, than the maximum switching speed of the unaltered circuit 10. A disguised microelectronic integrated digital logic circuit embodying the present invention which incorporates an unaltered inverter and an altered inverter is designed to normally operate at a predetermined operating switching (clock) speed which is higher than the maximum switching speed of the altered inverter, and lower than the maximum switching speed of the unaltered inverter. In addition, the maximum switching speed of the altered inverter is higher than a maximum test switching speed at which the circuit is capable of being tested using known low speed test procedures. The transfer curve 12 of the inverter circuit 10 in unaltered form is presented again in FIG. 3.
Further illustrated in FIG. 3 is a transfer curve 16 which is approximately centered on the switching voltage V.sub.IN0, but has a much steeper shape. The curve 16 is produced by altering the values of T.sub.R, V.sub.TLD and V.sub.TDR in accordance with equations (7) and (8) such that the rise time T.sub.R is much longer than for the curve 12. As a result, the curve 16 has altered values of the threshold voltages V.sub.TDR and V.sub.TLD, designated as V.sub.TDR' and V.sub.TLD' respectively, which are shifted from the corresponding values for the curve 12 toward the switching voltage V.sub.IN0. The altered threshold voltages for the curve 16 are approximately symmetrical about the switching voltage V.sub.IN0 as with the curve 12.
As the voltage difference between the threshold points V.sub.TDR' and V.sub.DD -V.sub.TLD2' of the curve 16 is much smaller than that between the threshold points V.sub.TDR and V.sub.DD -V.sub.TLD for the curve 12, the altered inverter circuit will require substantially more time for the capacitance C to charge and discharge than with the unaltered inverter circuit, as expressed by equation (5). Thus, if an attempt is made to switch the altered inverter circuit at a speed which is higher than a value corresponding to the increased rise time, the capacitor C will not charge or discharge sufficiently for the output voltage V.sub.OUT to transition through the switching voltage V.sub.IN0, and the circuit will not switch. Instead, the inverter will remain in whichever state (logically high or low) it was in before the switching attempt was made.
The alteration further illustrated in FIG. 4. The output voltage of the inverter circuit as a function of time is plotted for the unaltered circuit as a curve 18, and for the altered circuit as a curve 20. Assuming that the input voltage V.sub.IN is switched from V.sub.DD to zero, the output voltage V.sub.OUT for the unaltered circuit will reach the switching voltage V.sub.IN0 in a time T1, whereas the output voltage V.sub.OUT for the altered circuit will require a substantially longer time T2 to reach the switching voltage V.sub.IN0. Assuming a switching speed for normal operation having a corresponding time switching time T3 which is intermediate between T1 and T2, the unaltered circuit will switch whereas the altered circuit will not switch.
The threshold voltages V.sub.TLD and V.sub.TDR are preferably altered by implanting the channels of the FETs M2 and M1 respectively using an FIB, although the threshold voltages may be altered using other means within the scope of the invention. Where the inverter circuit 10 is fabricated on a silicon substrate, the threshold voltage V.sub.TDR of the driver FET M1 may be made more positive by implantation of an acceptor (p-type) ion species such as boron, whereas the threshold voltage V.sub.TLD may be made more negative by implantation of a donor (n-type) ion species such as arsenic. The fabrication of FETs with threshold voltages altered by ion implantation is well known in the art per se, such as described in a textbook entitled "ANALYSTS AND DESIGN OF DIGITAL INTEGRATED CIRCUITS" SECOND EDITION, by D. Hodges et al, McGraw Hill 1988, in section 2.3, pp. 29-35, entitled "THRESHOLD VOLTAGE OF THE MOS TRANSISTOR".
An example of how the present invention may be applied to dynamically disguise a microelectric integrated digital NMOS logic circuit 22 is illustrated in FIG. 5. The output V.sub.OUT1 of the inverter circuit 10 is applied as one input to a NAND gate 24 which includes a depletion mode active load FET M4 connected in series circuit with driver FETs M3 and M5. A first input voltage V.sub.IN1 is applied to the gate of the FET M1, whereas the output V.sub.OUT1 of the inverter circuit 10 is applied to the gate of the FET M3. A second input V.sub.IN2 is applied to the gate of the FET M5.
If none of the FETs in the logic circuit 22 are altered, the circuit 22 will produce a logically low output V.sub.OUT2 when V.sub.IN1 is low and V.sub.IN2 is high, and produce a logically high output for all other combinations of V.sub.IN1 and V.sub.IN2.
The circuit 22 can be disguised, for example, by altering the FETs M1 and M2 as described above such that they will switch only at low speed, and designing the overall circuit logic such that the input V.sub.IN1 will be high when the drain supply V.sub.DD is initially applied to the circuit 22. Although the circuit 22 will function in the normal manner described above at low speed, the FETs M1 and M2 will not switch at high speed. Thus, the FET M1 will be always on, the output V.sub.OUT1 will be always low, the FET M3 will be always off, and the circuit 22 will produce a logically high output V.sub.OUT2 for all combinations of inputs V.sub.IN1 and V.sub.IN2.
The circuit 22 may also be altered to produce a logically high output for all combinations of inputs V.sub.IN1 and V.sub.IN2 by altering the FETs M4 and M5 such that they will not switch at high speed, and designing the overall circuit logic such that the input V.sub.IN2 will be low when the drain supply is initially applied to the circuit 22. The FET M5 will remain always off if an attempt is made to switch the circuit 22 at high speed.
The altered and unaltered FETs are logically associated with each other in a predetermined manner within the overall logic of the microelectronic integrated digital logic circuit in which they are incorporated. The altered and unaltered FETs may be elements of the same gate, elements of different gates which are connected to each other to perform a composite logic function, or elements of unconnected gates (one or both of which may be dummy gates).
FIG. 6 illustrates an inverter circuit 26 implemented with CMOS FETs in a symmetrical configuration. An NMOS FET M6 is connected in series circuit with a p-channel enhancement mode (PMOS) FET M7 across the drain supply V.sub.DD and ground. An input V.sub.IN is applied to the gates of both FETs M6 and M7. The output V.sub.OUT is taken at the junction of the FETs M6 and M7.
The FET M6 has a threshold voltage V.sub.TN which is more positive than zero, whereas the FET M7 has a threshold voltage V.sub.TP which is more negative than zero. When V.sub.IN is logically high, the FET M6 is turned on and the FET M7 is turned off, producing a logically low output V.sub.OUT. For a logically low input V.sub.IN, the FET M7 is turned on and the FET M6 is turned off, producing a logically high output V.sub.OUT. The voltage transfer curves for the inverter circuit 26 are similar to the curve 12 (unaltered circuit) illustrated in FIGS. 2 and 3, and the curve 16 (altered circuit) illustrated in FIG. 3 respectively. The threshold voltage V.sub.TN of the FET M6 of FIG. 6 corresponds to the threshold voltage V.sub.TDR of the driver FET M1 of FIG. 1, whereas the threshold voltage V.sub.TP of the FET M7 of FIG. 6 corresponds to the threshold voltage V.sub.TLD of the load FET M2 of FIG. 1.
The threshold voltages V.sub.TN and V.sub.TP of the FETs M6 and M7 of the CMOS inverter circuit 26 may be altered in a manner which is similar to that described above with reference to the NMOS inverter circuit 10 illustrated in FIG. 1 to make the maximum switching speed of the altered inverter circuit 26 much slower than that of the unaltered inverter circuit.
More specifically, the current I.sub.P through the PMOS FET M7 in the saturation region is given as ##EQU9##
The current I.sub.N through the NMOS FET M6 in saturation is given as ##EQU10##
Assuming for simplicity that the channel-length modulation .lambda. is the same for the FETs M6 and M7, equating the currents I.sub.N =I.sub.P produces ##EQU11##
Setting V.sub.IN =V.sub.DD /2 (where V.sub.DD /2 is the switching voltage corresponds to the voltage V.sub.IN0 in the NMOS case), gives ##EQU12##
The rise time T.sub.R is approximated as ##EQU13##
The threshold voltage V.sub.TP for the PMOS FET M7 which produces a selected rise time T.sub.R is ##EQU14## whereas the corresponding threshold voltage V.sub.TN for the NMOS FET M6 is ##EQU15##
The switching speed can be slowed down by an even greater extent by operating the altered CMOS inverter circuit 26 in the subthreshold region. For example, where .beta..sub.R =1, equation (12) reduces to V.sub.TN =-V.sub.TP, and subthreshold operation requires that V.sub.TN +.vertline.V.sub.TP .vertline.>V.sub.DD.
An example of how the present invention may be applied to dynamically disguise a microelectronic integrated digital CMOS logic circuit 28 is illustrated in FIG. 7. The output V.sub.OUT1 of the inverter circuit 26 is applied as one input to a NOR gate 29 which includes PMOS FETs M9 and M11 connected in series circuit with an NMOS FET M8 between the drain supply V.sub.DD and ground. An NMOS FET M10 is connected in parallel circuit with the FET M8. A first input voltage V.sub.IN1 is applied to the gates of both FETs M6 and M7, whereas the output V.sub.OUT1 of the inverter circuit 26 is applied to the gates of both FETs M8 and M9. A second input V.sub.IN2 is applied to the gates of both FETs M10 and M11.
If none of the FETs in the logic circuit 28 are altered, the circuit 28 will produce a logically high output V.sub.OUT2 when V.sub.IN1 is high and V.sub.IN2 is low, and produce a logically low output for all other combinations of V.sub.IN1 and V.sub.IN2.
The circuit 28 can be disguised, for example, by altering the FETs M6 and M7 as described above such that they will switch only at low speed, and designing the overall circuit logic such that the input V.sub.IN1 will be low when the drain supply V.sub.DD is initially applied to the circuit 28. Although the circuit 28 will function in the normal manner described above at low speed, the FETs M6 and M7 will not switch at high speed. Thus, the FET M6 will be always off, the FET M7 will be always on, the output V.sub.OUT1 will be always high, the FET M8 will be always on, the FET M9 will be always off, and the circuit 28 will produce a logically low output V.sub.OUT2 for all combinations of inputs V.sub.IN1 and V.sub.IN2.
The circuit 28 may also be altered to produce a logically low output for all combinations of inputs V.sub.IN1 and V.sub.IN2 by altering the FETs M10 and M11 such that they will not switch at high speed, and designing the overall circuit logic such that the input V.sub.IN2 will be high when the drain supply is initially applied to the circuit 28. The FET M10 will remain always on and the FET M11 will remain always off if an attempt is made to switch the circuit 28 at high speed.
FIGS. 8a to 8d are simplified diagrams illustrating a method of fabricating an NMOS microelectronic integrated digital logic circuit 31 embodying the present invention. In FIG. 8a, NMOS FETs 30, 32, 34 and 36 are partially formed in the surface of a p-type silicon substrate 38, including sources 30a, 32a, 34a and 36a and drains 30b, 32b, 34b and 36b which are formed by implantation of n-type ions in a conventional manner.
The FETs 32 and 36 are driver FETs, whereas the FETs 30 and 34 are depletion mode active load FETs which are logically associated with the FETs 32 and 34 respectively. For example, the FETs (30,32) and the FETs (34,36) may be interconnected to constitute an inverter circuits such as described with reference to FIG. 1. The FETs 30 and 34 further include channels 30c and 34c respectively which are conventionally doped with an n-type impurity to produce depletion mode operation. The FETs 32 and 36 have channels 32c and 36c which are not implanted to produce enhancement mode operation. The FETs 30, 32, 34 and 36 in the partially fabricated NMOS microelectronic integrated digital logic circuit of FIG. 8a would operate normally as illustrated in FIG. 2 if the fabrication were completed in the conventional manner.
In the next step as illustrated in FIG. 8b, the channel 34c of the depletion load FET 34 is implanted using an FIB as indicated by arrows 38 with n-type ions to alter the doping of the channel 34c and thereby change the threshold voltage of the FET 34 from V.sub.TLD to V.sub.TLD' as illustrated in FIG. 3. Then, as illustrated in FIG. 8c, the channel 36c of the driver FET 36 is implanted using an FIB as indicated by arrows 40 with p-type ions to alter the doping of the channel 36c and thereby change the threshold voltage of the FET 36 from V.sub.TDR to V.sub.TDR' as illustrated in FIG. 3.
FIG. 8d illustrates how the NMOS microelectronic integrated digital logic circuit is further processed using conventional steps to form source metal contacts 30d, 32d, 34d and 36d, drain metal contacts 30e, 32e, 34e and 36e, gate oxide layers 30f, 32f, 34f and 36f, and gate metal contacts 30g, 32g, 34g and 36g on the substrate 38. In the finished circuit, the inverter circuit including the FETs 30 and 32 will operate in the normal manner, whereas the inverter circuit including the FETs 34 and 36 will only switch at low speed in the manner described above.
FIGS. 9a to 9d are simplified diagrams illustrating a method of fabricating a CMOS microelectronic integrated digital logic circuit 41 embodying the present invention. In FIG. 9a, NMOS FETs 42, 44, 46 and 48 are partially formed in the surface of an n-type silicon substrate 50. The FETs 42 and 44 are PMOS FETs, and include sources 40a, and 44a, and drains 40b and 44b respectively which are formed by implantation of p-type ions in a conventional manner.
The FETs 44 and 48 are NMOS FETs, and are formed in p-type wells 50a and 50b respectively which are implanted in the surface of the substrate 50. The FETs 44 and 48 include n-type implanted sources 44a and 48a, and drains 44b and 48b respectively. Channels 42c, 44c, 46c and 48c are defined between the sources and drains of the respective FETs.
The FETs (42,44) and the FETs (46,48) may be interconnected to constitute inverter circuits such as described with reference to FIG. 6. The FETs 42, 44, 46 and 48 in the partially fabricated CMOS microelectronic integrated digital logic circuit of FIG. 8a would operate normally if the fabrication were completed in the conventional manner.
In the next step as illustrated in FIG. 9b, the channel 46c of the PMOS FET 46 is implanted using an FIB as indicated by arrows 52 with n-type ions to alter the doping of the channel 46c and thereby make the threshold voltage of the FET 46 more negative. Then, as illustrated in FIG. 9c, the channel 48c of the NMOS FET 48 is implanted using an FIB as indicated by arrows 54 with p-type ions to alter the doping of the channel 48c and thereby make the threshold voltage of the FET 48 more positive.
FIG. 9d illustrates how the CMOS microelectronic integrated digital logic circuit is further processed using conventional steps to form source metal contacts 42d, 44d, 46d and 48d, drain metal contacts 42e, 44e, 46e and 48e, gate oxide layers 42f, 44f, 46f and 48f, and gate metal contacts 42g, 44g, 46g and 48g on the substrate 50. In the finished circuit, the inverter circuit including the FETs 42 and 44 will operate in the normal manner, whereas the inverter circuit including the FETs 46 and 48 will only switch at low speed in the manner described above.
While several illustrative embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art, without departing from the spirit and scope of the invention. Accordingly, it is intended that the present invention not be limited solely to the specifically described illustrative embodiments. Various modifications are contemplated and can be made without departing from the spirit and scope of the invention as defined by the appended claims.
Claims
I claim:
1. A microelectric integrated digital logic circuit, comprising: at least one input terminal; an output terminal; a first microelectric digital logic switching element having a first maximum switching speed which is higher than a predetermined operating switching speed at which the circuit is designed to operate; and a second microelectric digital logic switching element which is connected with the first switching element to provide a predetermined logical function between said at least one input terminal and said output terminal and has a second maximum switching speed which is lower than the operating switching speed and higher than a predetermined maximum test switching speed at which the circuit is capable of being tested; the first and second switching elements both switching at switching speeds lower than the test switching speed, and only the first switching element switching at the operating switching speed, such that the circuit operates differently at the test switching speed than at the operating switching speed.
2. A circuit as in claim 1, in which: the first switching element comprises a first field-effect transistor (FET) which has a first threshold voltage and is connected in circuit to have a first switching voltage; the second switching element comprises a second FET which has a second threshold voltage and is connected in circuit to have a second switching voltage which is approximately equal to the first switching voltage; and the second threshold voltage is closer to the second switching voltage than the first threshold voltage is to the first switching voltage, thereby causing the second switching speed to be lower than the first switching speed.
3. A circuit as in claim 2, in which: the first switching element further comprises a third (FET) which has a third threshold voltage and is connected in series with the first FET to constitute a first active load; the second switching element further comprises a fourth FET which has a fourth threshold voltage and is connected in series with the second FET to constitute a second active load; the fourth threshold voltage is closer to the second switching voltage than the third threshold voltage is to the first switching voltage, thereby causing, in combination with the second and first threshold voltages respectively, the second switching speed to be lower than the first switching speed.
4. A circuit as in claim 3, in which: the first and third threshold voltages are different from the first switching voltages by opposite and approximately equal voltages respectively; and the second and fourth threshold voltages are different from the second switching voltage by opposite and approximately equal voltages respectively.
5. A circuit as in claim 3, in which: the third FET is further connected in series with the first FET such that the first active load is a first depletion mode load; and the fourth FET is further connected in series with the second FET such that the second active load is a second depletion mode load.
6. A circuit as in claim 5, in which the first, second, third and fourth FETs are n-channel metal-oxide-semiconductor (NMOS) FETs.
7. A circuit as in claim 2, in which: the first FET is a complementary metal-oxide-semiconductor (CMOS) FET of a first conductivity type; the first switching element further comprises a third FET which is a CMOS FET of a second conductivity type which is opposite to the first conductivity type, has a third threshold voltage, and is connected in circuit with the first FET such that the first switching element is a first CMOS switching element; the second FET is a CMOS FET of the first conductivity type; the second switching element further comprises a fourth FET which is a CMOS FET of the second conductivity type, has a fourth threshold voltage, and is connected in circuit with the second FET such that the second switching element is a second CMOS switching element; and the fourth threshold voltage is closer to the second switching voltage than the third threshold voltage is to the first switching voltage, thereby causing, in combination with the second and first threshold voltages respectively, the second switching speed to be lower than the first switching speed.
8. A circuit as in claim 7, in which: the first and third threshold voltages are different from the first switching voltage by opposite and approximately equal voltages respectively; and the second and fourth threshold voltages are different from the second switching voltage by opposite and approximately equal voltages respectively.
9. A circuit as in claim 2, in which: the second switching element further comprises a third FET which has a third threshold voltage and is connected in circuit with the second FET to constitute an active load; and the second and third threshold voltages are different from the second switching voltage by opposite and approximately equal voltages respectively.
10. A circuit as in claim 9, in which: the third FET is further connected in series with the second FET such that the active load is a depletion mode load.
11. A circuit as in claim 10, in which the second and third FETs are n-channel metal-oxide-semiconductor (NMOS) FETs.
12. A circuit as in claim 2, in which: the second FET is a complementary metal-oxide-semiconductor (CMOS) FET of a first conductivity type; the second switching element further comprises a third FET which is a CMOS FET of a second conductivity type which is opposite to the first conductivity type, has a third threshold voltage, and is connected in circuit with the second FET such that the second switching element is a CMOS element; and the second and third threshold voltages are different from the second switching voltage by opposite and approximately equal voltages respectively.
13. A circuit as in claim 2, in which: the second FET is a complementary metal-oxide-semiconductor (CMOS) FET of a first conductivity type; the second switching element further comprises a third FET which is a CMOS FET of a second conductivity type which is opposite to the first conductivity type, has a third threshold voltage, and is connected in circuit with the second FET such that the second switching element is a CMOS element; and the second and third threshold voltages are selected to cause subthreshold operation of the second and third FETs.
Patent Citations (5)
Non-Patent Literature (1)
- Patent Abstracts of Japan, vol. 014, No. 463, Oct. 8, 1990, & JP-A-21 88 944 (Sharp K.K.) Jul. 25, 1990 abstract.