US 5,201,992 AGrant

Method for Making Tapered Microminiature Silicon Structures

Issue Date:1993-04-13

•13 Claims

•4 Drawing Sheets

Abstract

Tapered silicon structures, of interest for use, e.g., in atomic force microscopes, in field-emission devices, and in solid state devices are made using silicon processing technology. Resulting tapered structures have, at their tip, a radius of curvature of 10 nanometers or less. Such preferred silicon structures are particularly suited as electron emitters in display devices.

Metadata

Assignee

Bell Communications Research, Inc.

Inventors

Nicholas C. Andreadakis
Robert B. Marcus

Application Information

Application Number:US 7743610

Filing Date:1991-10-08

Priority Date:1990-07-12

Art Unit:114

Classifications

IPC:

H01L 21306B44C 122C03C 1500C03C 2506

Field of Search:

156313427643;651;657;659.1;662;647;654309;310;33664;66;77;226;399

Patent Drawings (4 sheets)

Description

Technical Field

The invention is concerned with devices comprising a tapered microminiature structure and with the fabrication of such structures.

Background of the Invention

Microminiature pointed, conical or pyramid-shaped tapered structures have been suggested for use, e.g., in scanning tunneling microscopes, in atomic force microscopes, as biological probes, and in vacuum-microelectronic devices. Also, more specifically with respect to the latter, wedge- or ridge-shaped structures have been suggested, e.g., as disclosed by R. B. Marcus et al., "A Novel Vacuum Microelectronics Electron Field Emitter", The First International Vacuum Microelectronics Conference, Jun. 13-15, 1988, sponsored by The Electron Device Society of the IEEE.

With regard to specific electronic devices, micro-miniature tapered structures are receiving attention for use as cathodes in specialized applications; for example, as described by C. E. Holland et al., "Spindt Cold Cathode Vacuum Fluorescent Display", EuroDisplay 87, pp. 1-3, resulting structures are suggested for use as cathodes in matrix cathodoluminescent displays. Further use is contemplated, e.g., in transducers, in slow-wave structures for coherent terahertz electromagnetic sources, as cathodes for free-electron lasers, and in integrated electron gun structures for traveling wave tubes; see R. Greene et al., "Vacuum Integrated Circuits", IEDM 85, pp. 172-175. Proposed further are three-terminal field-emission devices for very-high-speed microelectronic circuits; see, e.g., U.S. Pat. No. 4,721,885, issued Jan. 26, 1988 to I. Brodie.

Since, unlike solid-state devices, field-emission devices rely on electrons traveling in free space, miniaturization of such devices poses challenges not encountered at present in the fabrication of solid-state devices. One fabrication method, disclosed by C. A. Spindt et al., "Physical Properties of Thin-film Field Emission Cathodes with Molybdenum Cones", Journal of Applied Physics, Vol. 47 (1976), pp. 5248-5263, involves the formation of cone-shaped emitter structures by molybdenum metal deposition in the presence of a suitable mask. Proposed also is a method involving selective etching of (doped) silicon; see U.S. Pat. No. 3,970,887, issued Jul. 20, 1976 to D. O. Smith et al. And, for yet other methods, involving molding of metal or semiconductor material, see U.S. Pat. No. 4,307,507, issued Dec. 29, 1981 to H. F. Gray et al., and U.S. Pat. No. 4,685,996, issued Aug. 11, 1987 to H. H. Busta et al.

For the fabrication of miniaturized tapered structures, and especially of arrays of such structures for use as field-emission cathodes, silicon technology is considered particularly advantageous; see, e.g., J. B. Warren, "Control of Silicon Field Emitter Shape with Isotropically Etched Oxide Masks", Second International Conference on Vacuum Microelectronics, July 1989, pp. 37-40 and D. Stephani et al., "Fabrication of Densely Packed Sharp Silicon Field Emitters Using Dry Etching Techniques", Second International Conference on Vacuum Microelectronics, July 1989, p. 18.

In the context of silicon processing--and, e.g., in the interest of maximizing field-emission efficiency in field-emission devices, or in the interest of increased resolution in scanning microscopes--it is desired to enhance the sharpness of micro-miniature tapered structures or protuberances. Also, where an array of such structures is included as, e.g., in a display device, high uniformity of sharpened protuberances is desirable. Uniformity is similarly desirable in the fabrication, by wafer processing, of device chips comprising protuberances. It is such twin aims of sharpness and uniformity which motivate the invention described below.

Summary of the Invention

For incorporation, e.g., in electronic display and semiconductor devices, tapered silicon protuberances are sharpened to terminate in an apex having a preferred radius of curvature not exceeding approximately 10 nanometers, and radii of curvature not exceeding 1 nanometer can be achieved. Optionally, without appreciable effect on sharpness, another material, e.g., tungsten may replace silicon at the surface of a sharpened protuberance; also, thin films of other materials, e.g., gold may be deposited.

A preferred sharpening treatment comprises surface oxidation at relatively low temperature and applied to protuberances which are sufficiently slender and which have sufficient initial taper. Preferably, in the interest of apex uniformity in an array of protuberances, such oxidation treatment is repeated once or several times.

In cases where resulting uniform apices have radius of curvature less than a desired value, further oxidation processing at elevated temperature may be used to produce protuberances with desired increased radius.

Brief Description of the Drawing

FIG. 1 is a transmission electron micrograph of the of tip a silicon protuberance in accordance with a preferred embodiment of the invention;

FIG. 2 is a schematic, enlarged cross section of a representative portion of a field-emission display device in accordance with a preferred device embodiment of the invention;

FIG. 3 is a schematic, enlarged cross section of a metal-oxide-semiconductor or tunnel-diode structure in accordance with a preferred further device embodiment of the invention;

FIG. 4 is a schematic, enlarged cross section of a Schottky-barrier structure in a accordance with a preferred further device embodiment of the invention;

FIG. 5 is a schematic, enlarged cross section of a p-n-junction structure in accordance with a preferred further device embodiment of the invention;

FIG. 6-10 are schematic, enlarged elevations of a structure, progressively at initial, intermediate, and final stages of preferred processing of the invention; and

FIG. 11 is a schematic, enlarged elevation of a portion of the structure shown in FIG. 9, further showing preferred initial taper.

For the sake of clarity and ease of appreciation, structural features are not drawn to scale in the Figures.

Detailed Description

In the Figures, like features are designated by the same numeral; in the following, physical dimensions and measurements are understood to be nominal or approximate. Devices and structures in accordance with FIG. 2-5 are representative of vacuum-electronic and solid-state devices incorporating tapered silicon protuberances or structures in accordance with an aspect of the invention. FIG. 6-11 illustrate preferred processing in the fabrication of such structures.

FIG. 1 shows the tip of a preferred silicon needle, magnified as reflected in the 5-nanometer scale segment; electrons at 400 keV were used for imaging. The tip has an apex with radius of curvature of approximately 0.5 nanometer. (The structure is covered with an amorphous layer, 1.5 to 2.0 nanometers thick, understood to be due to polymerization of hydrocarbon by the electron beam.)

FIG. 2 shows the general design of an illustrative device comprising an array of three-terminal components, as may function as a display device. Specifically shown are single-crystal doped-silicon substrate 10 comprising electron field-emission cathode structures 101 with preferred sharpened tips, first dielectric layer 11, metallic gate electrodes 12, second dielectric layer 13, phosphor layer 14, transparent conductive anode layer 15, and glass plate 16.

Dielectric layers 11 and 13 may consist of silicon dioxide, polyimide, or a combination of silicon dioxide and polyimide, 1.5 micrometer thick, for example. Gate electrodes 12 may consist of titanium, titanium-nickel, titanium-gold, or polycrystalline silicon, 0.5 micrometer thick; anode layer 15 may be made of indium-tin oxide. Choice of phosphor material depends on desired color; for example, zinc silicate, doped with manganese produces green light when exposed to electrons emitted from the tips of structures 101. Alternatively, a red display is obtained by inclusion of europium-doped yttrium-phosphorus-vanadium oxide. These and other choices, and basic device fabrication methods are well-known in the art; see, e.g., the patents to I. Brodie and to D. O. Smith et al. and the papers by C. A. Spindt et al. and by C. E. Holland et al. cited above; see also D. J. Elliott, "Integrated Circuit Fabrication Technology", Second Edition, McGraw-Hill Publishing Company, 1989.

Structures 101 may be arranged in one- or two-dimensional arrays; in display devices intended for direct viewing, cathodes typically may have a height of 1 to 10 micrometers and may be spaced from 2 to 20 micrometers apart. Typical spacing between the tips of cathodes 101 and phosphor layer 14 may be from 5 to 100 micrometers. For a preferred method of producing cathodes 101 having preferred sharpness, see the description below with reference to FIG. 6-11.

Localized phosphorescence may be produced in layer 14 upon application of a suitable voltage between substrate 10 and a gate electrode 12, while another, constant voltage is applied between substrate 10 and anode layer 15. Alternatively, anode layer 15 may be patterned into a plurality of segments, and control voltages may be applied between substrate 10 and such segments, while gate electrodes 12 (or a corresponding contiguous electrode) are held at a constant voltage. Contemplated also are two-terminal devices, as well as devices in which luminosity is due, not to a phosphor stimulated by electrons field-emitted in a vacuum, but to a luminescent microplasma near electrode structures 101 which may be anodic or cathodic. Yet another design involves luminosity stimulated in a phosphor layer 14 by ultraviolet light emitted by a plasma near electrodes 101. (Exemplary green and red phosphors mentioned above are sensitive not only to electrons but also to ultraviolet light; suitable as a gas for an ultraviolet-emitting plasma is xenon-doped helium, including 0.1 volume-percent xenon, for example.)

While preferred devices in accordance with FIG. 2 involve structures with high-curvature tips for locally producing high electric fields in a vacuum or in a gas, production of such fields is of interest also in solid-state structures, e.g., to produce highly localized semiconductor devices as illustrated by FIG. 3-5.

FIG. 3 shows silicon substrate 10 with protuberance 101, silicon oxide layer 21 covering the tip of protuberance 101, dielectric layer 22 on the remainder of protuberance 101 and on substrate 10, and metal electrode layer 23 on oxide layer 21 and dielectric layer 22, forming a metal-oxide-semiconductor structure or a tunnel-diode structure depending on layer-21 thickness, chosen in a general range from 1.5 to 100 nanometers. Layer 21 may be formed by thermal oxidation, layer 22 by wet oxidation or deposition, and layer 23 by evaporation (of titanium-gold or nickel-gold, for example.) For further details with respect to basic device fabrication methods see the references mentioned above with respect to FIG. 2; for a preferred method of producing protuberances 101 having preferred sharpness, see the description below with reference to FIG. 6-11.

FIG. 4 shows silicon substrate 10 with protuberance 101, dielectric layer 31 disposed on substrate 10 but leaving the tip of protuberance 101 uncovered, and metal electrode layer 32 in part on dielectric layer 31 and in part on the tip of protuberance 101, forming a Schottky-barrier structure. Layers 31 and 32 may be formed as discussed above with respect to layers 22 and 23, for example. For further details with respect to basic device fabrication methods see the references mentioned above with respect to FIG. 2; for a preferred method of producing protuberances 101 having preferred sharpness, see the description below with reference to FIG. 6-11.

FIG. 5 shows substrate 10 with doped protuberance 101 (n-type, for example), dielectric layer 41 on substrate 10, which leaves the tip of protuberance 101 uncovered, and complementary (p-type) silicon material 42 covering the tip of protuberance 101 and the dielectric 41, forming a p-n- or n-p-junction structure. Layer 41 may be formed as discussed above with respect to layer 22, and layer 42 may be formed by vapor-phase epitaxial deposition, resulting in epitaxial silicon on the tip of protuberance 101 and in polysilicon on layer 41. For further details with respect to basic device fabrication methods see the references mentioned above with respect to FIG. 2; for a preferred method of producing protuberances 101 having preferred sharpness, see the description below with reference to FIG. 6-11.

FIG. 6 shows an initial structure comprising single-crystal silicon substrate 10, a deposited mask layer 51 (consisting, e.g., of silicon oxide or nitride), and a deposited resist layer 52, consisting of a radiation-sensitive material--sensitive, e.g., to light, x-rays, electrons, or ions. Such structure may be produced by methods well known in the art of semiconductor device processing; in this respect, as well as with respect to further standard processing details in connection with FIG. 7-9, see, e.g., the book by D. J. Elliott cited above.

FIG. 7 shows the structure of FIG. 6 after further processing by patterning of resist layer 52 by exposure and development. In the fabrication of cone- or pyramid-shaped tapered structures a resulting mask pattern may comprise one or several circular or square-shaped regions or "islands" having a diameter or width of 1-30 micrometers. Other patterns may be used: for example, when making linear or curvilinear wedge-shaped tapered structures, use of a corresponding strip pattern is indicated. Alternatively, for circular or other closed-curve patterns, a larger island may be used such that the desired pattern is delineated by the edge of the island; see the paper by R. B. Marcus et al. cited above.

FIG. 8 shows the structure of FIG. 7 after further processing by transfer of the resist pattern to mask layer 51 by etching, followed by stripping of resist remnants. (In the case of silicon dioxide as a mask-layer material, plasma etching by means of a mixture of carbon tetrafluoride and hydrogen can be used for etching; in the case of silicon nitride, a mixture of carbon tetrafluoride and oxygen can be used.)

FIG. 9 shows the structure of FIG. 8 after suitable silicon processing to form protuberances 101 below the mask islands, e.g., by isotropic etching (by means of a mixture of nitric and hydrofluoric acids, for example), by reactive ion etching, or by ion milling. Preferably, in order to prevent the formation of protuberances having blunt, rounded tips, etching is terminated before mask islands become detached. Resulting protuberances comprise a small, essentially flat top portion 102, and a straight or concave sidewall 103. Preferably, in the interest of expeditious preferred processing as described below with reference to FIG. 10, the width of portion 102 does not exceed 500 nanometers. After etching, mask-layer remnants may be stripped; alternatively, stripping may be omitted as mask remnants are removed upon subsequent oxidation processing.

FIG. 10 shows the structure of FIG. 9 after oxidation processing. A preferred oxidation procedure in accordance with an aspect of the invention involves exposure of the structure of FIG. 9 to a dry-oxygen environment, preferably at a temperature not exceeding 1050 degrees C., and preferably with oxygen contributing at least 50 percent, and water vapor at most 1 percent of total pressure. Contemplated as diluents or carrier gases are, e.g., helium, argon, or nitrogen. In the interest of adequate reaction rate for processing times of 2 to 6 hours at ambient pressure, preferred processing temperature is at least 900 degrees C. The use of higher or lower pressures is not precluded; preferred processing times are inversely related to pressure and temperature.

From the resulting oxidized structure, surface oxide is stripped, e.g., in concentrated hydrofluoric acid or a buffered hydrofluoric solution. For enhanced sharpness, preferred oxidation processing and stripping may be repeated one or several times, the preferred number of repetitions being directly related to the width of the flat portion 102.

Optionally, in case protuberances in an initial array illustrated in FIG. 9 are of highly nonuniform shape, processing as described above may be preceded by exposure to a humid environment at a preferred temperature above 1050 degrees C. for times longer than 3 minutes, resulting in more uniform morphology.

In addition to structural features 101, 102, and 103 in accordance with FIG. 9, FIG. 11 shows the width of flat portion 102 as delta, and a taper angle phi as determined by tangents to facing, concave sidewalls 103. Tangents are placed at points spaced a distance from surface 102, such distance being equal to delta, the same as the width of flat portion 102. In the absence of a protective cover on surface 102, efficacy of preferred sharpening as described above depends on sufficient slenderness of protuberance 101, characterized by a sufficiently small angle phi; specifically preferred are angles phi not exceeding approximately 30 degrees. Alternatively, and especially when an initial protuberance is formed by anisotropic etching, such condition may not be met, in which case oxidation sharpening may still be applied so long as surface 102 remains covered--by mask 51, for example.

Repeated preferred oxidation treatments enhance sharpness and also uniformity of apices in an array of protuberances. This is desirable indeed as, in most instances, enhanced uniformity may be sought in combination with enhanced sharpness. However, in accordance with a further aspect of the invention, once a sharpened, highly uniform array has been produced it is possible, without loss of uniformity, to decrease apex sharpness by a further, high-temperature oxidation treatment. Suitable for this purpose are wet or dry oxidizing environments, preferably at a temperature which exceeds 1050 degrees C. For example, when protuberances with one-nanometer radius of curvature are exposed to water vapor at a temperature of 1100 degrees C. for 3 minutes, radius of curvature will increase uniformly to approximately 2.5 nanometers.

Depending on intended use of a sharpened silicon structure, the final surface may be passivated, e.g., by rinsing with concentrated hydrofluoric acid, thereby producing an essentially oxide-free silicon surface (see E. Yablonovitch et al., "Unusually Low Surface-Recombination Velocity on Silicon and Germanium Surfaces", Physical Review Letters, Vol. 57 (1986), pp. 249-252.) Such passivation is of interest, e.g., when a sharpened tip is subsequently covered with a metal, e.g., gold. Alternatively, passivation may be omitted, e.g., when a surface oxide layer is desired (see FIG. 3, for example.) Of particular interest is processing, subsequent to stripping of surface oxide, by chemical replacement of surface silicon by another material, e.g., tungsten; for processing details see the above-identified patent to H. H. Busta et al. In accordance with an aspect of the invention, such replacement can be carried out while essentially maintaining preferred sharpness of a sharpened silicon structure.

The sharpness of resulting tapered structures, e.g., needles, cones, pyramids, wedges, and ridges can be characterized by a radius of curvature at an apex of the tapered structure. In the case of needles, cones, and pyramids such termination is approximately spherical, with a well-defined radius of curvature; in the case of wedges or ridges, straight or curvilinear, curvature may be determined in a plane perpendicular to a wedge or ridge. Thus, in structures of interest, there is at least one cross section in which radius of curvature is defined in this fashion.

Tapered structures of the invention can be used in vacuum-microelectronic devices, e.g., field-emission and plasma display devices, and as electron sources for other applications, e.g., scanning electron microscopes, scanning tunneling microscopes, and cathode ray tubes. Also contemplated is their use in atomic force microscopes, as biological probes, and in solid state devices as exemplified.

Claims

We claim:

1. A method of making a tapered silicon structure which terminates in an apex whose radius of curvature is less than 10 nanometers comprising the steps of providing a silicon protuberance having a tapered shape comprising an essentially flat top portion whose width is of the order of 500 nanometers or less and having concave sidewalls such that, at a distance equal to said width from said flat top portion, tangents to first and second facing sidewalls form an angle of the order of 30 degrees or less, and exposing said silicon protuberance to an essentially dry oxidizing environment at a temperature not exceeding 1050 degrees C.

2. The method of claim 1 wherein said environment consists essentially of an atmosphere in which oxygen pressure is at least 50 percent and water vapor pressure is less than 1 percent of total pressure and comprising the further steps of removing oxide formed by exposing said protuberance to said environment and again exposing said protuberance to said environment subsequent to said removing.

3. The method of claim 2 further comprising the step of exposing said protuberance to a second oxidizing environment at a temperature greater tan 1050 degrees C.

4. A method of making a silicon structure comprising an array of a plurality of apices of uniform sharpness having radii of curvature of less than 10 nanometers comprising the steps of exposing an array of silicon protuberances to an essentially dry oxidizing environment at a temperature not exceeding 1050 degrees C., stripping surface oxides from said protuberances, and subsequently repeating said steps of exposing and stripping to attain the enhanced sharpness and uniformity of said apices in said array.

5. The method of claim 4 further comprising the step of exposing said array of protuberances to a humid oxidizing environment at a temperature above 1050 degrees centigrade prior to said dry oxidizing exposure step to provide an initial uniformity of said protuberances in said array.

6. The method of claim 4 comprising the further step of decreasing apex sharpness without loss of uniformity of said apices in said array be exposing said array to an oxidizing environment at a temperature which exceeds 1050 degrees C.

7. A method for making a tapered silicon structure, comprising a step of exposing a silicon protuberance to a first, essentially dry oxidizing environment at a temperature not exceeding 1050 degrees C., said silicon protuberance, prior to said step, having a tapered shape comprising an essentially flat top portion whose width, here called delta, is of the order of 500 nanometers or less, and said silicon protuberance having concave sidewalls such that, at a distance delta from said flat top portion, tangents to first and second facing sidewalls form an angle of the order of 30 degrees or less.

8. The method of claim 7, wherein said environment consists essentially of an atmosphere in which oxygen pressure is greater than or equal to 50 percent and water-vapor pressure is less than 1 percent of total pressure.

9. The method of claim 7, further comprising a step of removing oxide formed by exposing said protuberance to said first environment.

10. The method of claim 9, comprising a further step of exposing said protuberance to said first environment subsequent to said removing.

11. The method of claim 10 wherein said steps of exposing and removing are repeated.

12. The method of claim 9, further comprising a step of replacing surface silicon by tungsten.

13. The method of claim 9, further comprising a step of exposing said protuberance to a second oxidizing environment at a temperature greater than 1050 degrees C.

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Non-Patent Literature (8)

R. B. Marcus et al, "A novel vacuum microelectronics electron field emitter," The First International Vacuum Microelectronics Conference Proceedings, Jun. 13-15, 1988, sponsored by The Electron Device Society of the IEEE.
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Abstract

Description