Liquid-Crystal Display Apparatus

In general, a liquid-crystal display element has a drawback that the response speed is relatively low. Therefore, there have been made various improvements in methods of driving the liquid-crystal display element and also there have been developments of liquid-crystal materials and liquid-crystal cells for increasing the response speed. In a conventional liquid-crystal display-panel driving circuit for driving a liquid-crystal display panel which has scanning electrodes and signal electrodes disposed in a matrix arrangement, a scanning-electrode driving signal Xn and a signal-electrode driving signal Ym having waveforms shown in FIGS. 1-A to 1-D are used to drive the liquid-crystal display-panel. The scanning-electrode driving signal Xn is composed of pulse signals having a bias voltage V0 or V4, which are developed in response to a frame signal .phi.F and are sequentially applied to the scanning electrodes. The signal-electrode driving signal Ym is composed of pulse signals having a bias voltage V1 or V3, which are selectively applied to the signal electrodes in response to a video signal. As a result, a composite signal "Xn-Ym" shown in FIG. 1D is applied between the scanning electrodes and the signal electrodes, and the signal electrodes corresponding to the scanning electrodes selected by the scanning-electrode driving signal are driven.

The liquid-crystal display panel is driven in the above described manner, however the above method of driving the liquid crystal display panel still has a problem that the response speed of the liquid crystal has not been sufficiently improved.

The present invention has been made in the light of the above affairs, and its object is to provide a liquid-crystal display which is capable of increasing the response speed of liquid crystal.

As described above, one or both of the scanning-electrode driving signal and the signal-electrode driving signal during the respective divided periods have different wave levels, so that the peak voltage during the scanning electrode period becomes higher than conventional voltage level and thereby the response speed of the liquid crystal increases.

FIGS. 1A to 1D, each, are a timing chart illustrating waveforms of signals used in a conventional liquid-crystal display-panel driving system;

FIGS. 2 to 7 are views illustrating embodiments of the present invention;

FIG. 2 is a block diagram illustrating a construction of the first embodiment of the present invention;

FIGS. 3A, 3B, 3C, 3D and 3E, each, are a timing chart representing the operation of the first embodiment;

FIG. 4 is a block diagram illustrating a construction of the second embodiment of the present invention;

FIGS. 5A, 5B, 5C, 5D and 5E, each, are a timing chart illustrating the operation of the second embodiment;

FIG. 6 is a block diagram illustrating a construction of the third embodiment of the present invention;

FIGS. 7A, 7B, 7C, 7D and 7E, each, are a timing chart illustrating the operation of the third embodiment;

FIG. 8 is a view illustrating concept of a matrix display-panel, which is effective to compare the third embodiment to a conventional example;

FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G and 9H, and FIGS. 10A, 10B, 10C, 10D, 10E and 10F, each, are a view illustrating an example of a waveform of a driving signal employed in the third embodiment.

Embodiments of the present invention will be described with reference to the accompanying drawings. Referring to FIG. 2, reference numeral 10 denotes a scanning-electrode driving circuit, reference numeral 20 denotes a signal-electrode driving circuit and reference numeral 30 denotes a liquid-crystal display panel which has N units of scanning electrodes and M units of signal electrodes. The above scanning electrodes and signal electrodes are disposed in a matrix arrangement. The above scanning-electrode driving circuit 10 is composed of a scanning-electrode shift register 11 and a multiplexer 12. The scanning-electrode shift register 11 sequentially reads and shifts vertical timing signals delivered from a control section (not shown) in accordance with horizontal synchronizing signals and it outputs the vertical timing signals thus shifted to the multiplexer 12. Note that the above vertical timing signals are generated in synchronism with vertical synchronizing signals. Meanwhile, the multiplexer 12 is directly supplied with a bias voltage V2 and also supplied with bias voltages V01, V02, V41 and V42 through gate circuits 13a to 13d. The bias voltages V01, V02 (V41, V42) are set to values which are obtained by adding a fixed voltage "+V" or "- V" to a bias voltage V0 (V4) conventionally employed. The above gate circuits 13a through 13d are controlled by a frame signal .phi.F and a timing signal s supplied through AND gates 14a through 14d. More specifically, the frame signal .phi.F is directly supplied to AND gates 14a, 14b and supplied to AND gates 14c, 14d through an invertor 15. Meanwhile, the timing signal .phi.s is directly supplied to and gates 14a, 14c and supplied to AND gates 14b, 14d through an invertor 16. The gate circuits 13a to 13d are ON/OFF controlled by output signals of the above AND gates 14a to 14d and thereby bias voltages V01, V02, V41 and V42 are selectively applied to the multiplexer 12. The number m of division of respective scanning-electrode selection period determines the frequency of the above timing signal .phi.s. For example, in case that the number m of the division is "2", the frequency of the timing signal .phi.s is set to be two times that of the frame signal .phi.F. The above multiplexer 12 selects the above bias voltages in accordance with signals from the scanning electrode shift register 11 and supplies the selected bias voltages as scanning-electrode driving signals x1, x2, to xn to the liquid-crystal display panel 30.

In the meantime, the signal electrode driving circuit 20 is composed of a signal-electrode driving shift register 21, a latch and gradient signal generator circuit (PWM circuit) 22 and a multiplexer 23. The latch and gradient signal generator circuit 22 is supplied with the frame signal .phi.F and the multiplexer 23 is supplied with bias voltages V1, V3. The above signal-electrode driving shift register 21 sequentially reads and shifts display data, e.g., video data of 4 bits which are successively transferred from a preceding circuit. After reading data for one line, the shift register 21 transfers the data to the latch and gradient signal generator circuit 22. The latch and gradient signal generator circuit 22 latches data transferred from the signal electrode driving shift register 21 and generates a gradient signal in accordance with the latched data. Further, the latch and gradient signal generator circuit 22 inverts the gradient signal every time when the signal level of the frame signal .phi.F is changed and outputs the gradient signal thus inverted to the multiplexer 23. In this case, the latch and gradient signal generator circuit 22 divides respective selection periods of the scanning electrodes by m (m is an integer equal to or greater than 2) and generates m gradient signals with respect to the same display data (video data) and the circuit 22 supplies the gradient signals to the multiplexer 23. In the present embodiment, "m" is set to "2", that is, "m=2". Hereinafter, the embodiment where "m=2" is selected will be described. The multiplexer 23 selects bias voltages V1, V3 according to the gradient signals delivered from the latch and gradient signal generator circuit 22 and outputs the selected bias voltages as signal-electrode driving signals Yl through YM to the liquid-crystal display panel 30.

Now, the operation of the above embodiment will be described with reference to timing charts of FIGS. 3A to 3E. In the scanning-electrode driving circuit 10, the gate circuits 13a through 13d are ON/OFF controlled in accordance with the frame signal .phi.F and the timing signal .phi.s, and thereby bias voltages V01, V02, V41, V42 are selectively applied to the multiplexer 12. More particularly, in case that the frame signal .phi.F is high, AND gates 14a and 14b are selected. Therefore, when the timing signal .phi.s is high, the output of AND gate 14a becomes "1", causing the gate circuit 13a to open. Then the bias voltage V01 is selected by the gate circuit 13a and is applied to the multiplexer 13. When the timing signal .phi.s is low. The output of AND gate 14b becomes "1", causing the gate circuit 13b to open. Accordingly, the bias voltage V02 is selected by the gate circuit 13b and is applied to the multiplexer 13. In this case, the frequency of the timing signal .phi.s is set in accordance with the number of division of selection period during which each scanning electrode is operated. When the number of division of the selection period m is "2", the timing signal .phi.s has a frequency which is twice that of the frame signal .phi.F and its level is set high during the first half period of each frame and is set low during the latter half period of the frame. Therefore, when the frame signal .phi. is high, the bias voltage V01 is selected and applied to the multiplexer 12 during the first half period of the frame and the bias voltage V02 is selected and applied to the multiplexer 12 during the latter half period of the frame. In case that the frame signal .phi.F is low, AND gate 14c and 14d are selected. Therefore, the bias voltage V41 is selected and applied to the multiplexer 12 during the first half period of the frame in which the frame signal .phi.s is high, while the bias voltage V42 is selected and applied to the multiplexer 12 during the latter half period of the frame in which the timing signal .phi.s is low. The multiplexer 12 supplies the scanning electrodes selected by the scanning-electrode shift register 11 with the bias voltages supplied through the above gate circuits 13a to 13d. More specifically, when the frame signal .phi.F is high, the multiplexor 12 selects the bias voltage V01 during the first half period of the frame and the bias voltage V02 during the latter half period of the frame, and outputs these bias voltages V01, V02 as a scanning-electrode driving signal Xn to the liquid-crystal display panel 30. When the frame signal .phi.F is low, the multiplexer 12 selects the bias voltage V41 during the first half period of the frame and the bias voltage V42 during the latter half period, and outputs these voltages V41 and V42 as a scanning-electrode driving signal Xn to the liquid-crystal display panel 30. The multiplexer 12 also supplies bias voltage V2 to the scanning electrodes other than the scanning electrodes selected by the shift register 11.

Meanwhile, in the signal-electrode driving circuit 20, the latch and gradient-signal generator circuit 22 generates a gradient signal on the basis of the video signal delivered to the signal-electrode driving shift register 21. In this case, the latch and gradient-signal generator circuit 22 latches video data delivered from the signal-electrode driving shift register 21 and produces the same gradient signal corresponding to the data thus latched for m times, for example, two times during each selection period during which the scanning electrodes are operated and the shift register 21 supplies the gradient signal to the multiplexer 23. The multiplexer 23 selects the bias voltages V1 and V3 in accordance with the gradient signal from the latch and gradient signal generator circuit 22 as shown in FIG. 3 and provides these bias voltages V1 and V3 as the signal-electrode driving signal Ym to the liquid-crystal display panel 30. In FIGS. 3A to 3E, signal waveforms at a gradient rate of 50% to video data are shown.

The above liquid-crystal display panel 30 is driven by the composite signal "Xn-Ym", which are composed of the scanning-electrode driving signal Xn delivered from the scanning-electrode driving circuit 10 and the signal-electrode driving signal Ym delivered from the signal-electrode driving circuit 20.

The peak voltages of the above composite signal "Xn-Ym" will be given by ".vertline.V01+1 .vertline." during the period of high level frame of the frame signal .phi.F and also by "-.vertline.V01+V1.vertline." during the period of low level frame of the frame signal .phi.F. In this case, the scanning-electrode driving signal Xn is set so as to be different in level in every division period. But, if liquid crystal material is the same, the effective liquid-crystal driving-voltage is equal to that, for conventional liquid crystal material, and the relationship between the bias voltages V01 and V0 is given by "V0<V01". Accordingly, as shown in FIG. 3E, the peak voltage .vertline.V01+V1.vertline. of the composite signal "Xn-Ym" during the selection period in which the scanning electrodes operate will be higher than a conventional value. In general, liquid crystals are driven by the effective voltage but in a microscopic sense, molecules in the liquid crystal are excited by the voltage instantaneously applied thereto. Therefore, a high peak voltage applied to liquid crystals increases the response speed.

The second embodiment of the present invention will be described with reference to FIG. 4. In the above first embodiment, the peak level of the scanning-electrode driving signal is changed. On the contrary, the peak level of the signal electrode driving signal is changed in the second embodiment. More particularly, as shown in FIG. 4, the scanning-electrode driving circuit 10 is mainly composed of a scanning-electrode shift register 11 and a multiplexer 12. The multiplexer 12 is directly supplied with bias voltage V2 and is supplied with bias voltages V0 and V4 through gate circuits 17a and 17b, respectively. The gate circuit 17a is directly supplied with a frame signal .phi.F at its gate terminal and the gate circuit 17b is supplied with the frame signal .phi.F through an invertor 18. Accordingly, when the frame signal .phi.F is high, the bias voltage V0 is selected by the gate circuit 17a and then supplied to the multiplexer 12, and when the frame signal .phi.F is low, the bias voltage V4 is selected by the gate circuit 17b and supplied to the multiplexer 12. The multiplexer 12 selects the bias voltage V2 and the bias voltages V0 and V4 on the basis of an electrode selection signal delivered from the scanning-electrode shift register 11 and supplies the selected bias voltage as scanning-electrode driving signals Xl through XN to a liquid-crystal display panel 30. More particularly, the multiplexer 12 supplies the bias voltage V0 or V4 to the scanning electrodes selected by the scanning-electrode shift register 11 and supplies the bias voltage V2 to the electrodes other than the above selected electrodes.

Meanwhile, the signal-electrode driving circuit 20 is composed of a signal-electrode driving shift register 21, a latch and gradient signal generator circuit 22 and a multiplexer 23. The multiplexer 23 is supplied with bias voltages V11, V12, V31 and V32 through gate circuits 24a through 24d. The above bias voltage V11 is set to a value determined by adding a fixed voltage V to the bias voltage V1 and the bias voltage V12 is set to a value determined by subtracting the fixed voltage V from the bias voltage V1. In the same manner, the bias voltage V31 is set to a value determined by adding the fixed voltage V to the bias voltage V3 and the bias voltage V32 is set to a value determined by subtracting the fixed voltage V from the bias voltage V3. The above gate circuit 24a, 24c are directly supplied with a timing signal .phi.s and the gate circuit 24b, 24d are supplied with the timing signal .phi.s through an invertor 25. Accordingly, when the frame signal .phi.F is high, the bias voltages V11, V31 are supplied to the multiplexer 23 through gate circuits 24a, 24c and when the frame signal .phi.F is low, the bias voltages V12, V32 are supplied to the multiplexer 32 through the gate circuit 24b, 24d. The multiplexer 32 selects the above bias voltages on the basis of a gradient signal delivered from the latch and gradient signal generator circuit 22 and supplies the selected voltage as signal-electrode driving signals Yl to YM to the liquid-crystal display panel 30.

FIGS. 5A through 5E, each are a timing chart illustrating the operation of the second embodiment. In the scanning-electrode driving circuit 10 shown in FIG. 4, the gate circuits 17a, 17b are ON/OFF controlled in accordance with the frame signal .phi.F supplied thereto and thereby the bias voltages V0, V4 are selected and supplied to the multiplexer 12. More particularly, when the frame signal .phi.F is high, the gate circuit 17a becomes open and thereby the bias voltage V0 is supplied to the multiplexer 12. When the frame signal .phi.F is low, the gate circuit 17b becomes open and thereby the bias voltage V4 is supplied to the multiplexer 12. Accordingly, the multiplexor 12 supplies the bias voltage V0 or V4 to the scanning electrodes selected by the scanning-electrode shift register 11, as shown in FIG. 5C, and a supplies the bias voltage V2 as scanning-electrode driving signal Xl through XN to the electrodes other than the above selected electrodes.

Meanwhile, in the signal-electrode driving circuit 20, the bias voltages V11, V12, V31, V32 are selected by the gate circuits 24a to 25d in accordance with the timing signal .phi.s and are supplied to the liquid-crystal display panel 30. More particularly, when the timing signal .phi.s is high, the gate circuits 24a and 24c become open and thereby the bias voltages V11 and V31 are selected and supplied to the liquid-crystal display panel 30. When the timing signal .phi.s is low, the gate circuits 24b and 24d become open and thereby the bias voltages V12 and V32 are selected and supplied to the liquid-crystal display panel 30. Accordingly, a composite signal "Xn-Ym" having a waveform shown in FIG. 5E is applied between the scanning electrodes and the signal electrodes of the liquid-crystal display panel 30. The peak voltage of the composite signal "Xn-Ym" will be .vertline.V0+V11.vertline.". As a result, the peak voltage ".vertline.V0+V11.vertline." of the composite signal "Xn-Ym" during the selection period in which the scanning electrodes are selected to operate become higher than usual in the similar manner to that in the first embodiment, and thereby the response speed of the liquid crystal is improved.

FIG. 6 is a view illustrating the third embodiment of the present invention. The third embodiment is a combination of the first and second embodiments, and has the same scanning-electrode driving circuit 10 as that in the first embodiment and the same signal-electrode driving circuit 20 as that in the second embodiment. Accordingly, as shown in timing charts of FIGS. 7A to 7E, the signal waveforms of the scanning-electrode driving signal and the signal-electrode driving signal change in synchronism with the timing signal .phi.s, respectively. The composite waveform "Xn-Ym" of the scanning-electrode driving signal and the signal-electrode driving signal will have the peak voltage ".vertline.V01+V11.vertline." during the selection period in which the scanning electrodes are selected to operate. Hence the above peak voltage ".vertline.V01+V11.vertline." is higher than those in the first and second embodiments, and thereby the response characteristic of the liquid crystal can be highly improved.

Now, the third embodiment will be compared with a conventional example in terms of a margin of voltage for driving the liquid-crystal display.

FIG. 8 is a view illustrating a 5.times.4 matrix panel. FIGS. 9A to 9H and 12A to 10F, each are a view illustrating an example of a driving waveform, corresponding to that in the third embodiment, to display a pattern shown in FIG. 8. Examples of driving waveforms of the scanning electrodes and the signal electrodes when a common selection period is divided by two, are shown in FIGS. 9A to 9H. Gradient is given by 4 bits and therefore is represented in 16 levels. When the gradient is "0", the liquid crystal is turned off, and when the gradient is "15", the liquid crystal is turned on. As illustrated in FIGS. 9A to 9H, gradient signals given by display data are displayed in the first and latter half periods of the divided selection period, respectively. In each half period, bias voltage/scanning voltage or V11/V01, V12/V02 is changed FIGS. 10a to 10F each are a view illustrating a driving waveform when the selection period is divided by three (m=3) in the third embodiment.

Hereinafter, effective voltages V.sub.ON, V.sub.OFF and the margin .alpha. defined by V.sub.ON /V.sub.OFF will be described with reference to the third embodiment.

It is assumed that

VO=(a-1)V1

V3=-V1

V4=-V0

Then, voltage V.sub.ON, V.sub.OFF applied to selected picture elements and non-selected picture elements are given by ##EQU1## Hence, the driving margin .alpha. is given by ##EQU2## The maximum margin .alpha..sub.max at a=.sqroot.N+1 is calculated from ##EQU3##

It is assumed that ##EQU4## Then, the voltages V.sub.ON, V.sub.OFF are given by ##EQU5## Hence, the driving margin .alpha. is given by ##EQU6## If a=b, V.sub.ON, V.sub.OFF and .alpha. would be ##EQU7##

As seen from Eq.(10), the driving margin .alpha. is given by Eq.(3), independently of voltages V11 and V12.

If same liquid crystal is used in the conventional example and the third embodiment, Eqs. (2) and (9) would have an equal value since Vth of both liquid crystals are equal to each other. Hence, if voltages V11 and V12 are selected so as to satisfy the following Equation (11). ##EQU8## the effective voltages V.sub.ON, V.sub.OFF, and the margins .alpha. in the conventional example and the third embodiment would be equal to each other.