Read/Write Memory Having an on-Chip Input Data Register, Having Pointer Circuits Between a Serial Data Register and Input/Output Buffer Circuits

The subject invention is in the field of memory devices, specifically dual-port random access semiconductor memory devices as used in graphics applications.

With the advent of less expensive semiconductor memory, modern computer and microcomputer systems have been able to use bit-mapped video displays for the output of data from the system. As is well known, a bit-mapped video display requires a bit-mapped memory which can store at least one binary digit (bit) of information for each picture element (pixel) of the display device. Additional bits stored for each pixel provide the capability of the system to render complex images on the video display, such as multi-color images, and background and foreground images, such as a graphics background with textual information overlaid thereupon. The use of bit-mapped memory for storing image information also allows for data processing operations to easily generate and modify the stored image.

Modern video display devices are often of the raster-scan type, where an electron gun traces horizontal lines across the display screen in order to generate the desired image. In order for a raster scan image to continue to be displayed on the video screen, the image must be refreshed at periodic intervals. A common refresh rate for the cathode ray tube video display devices is 1/60 of a second, since the refresh operation carried out at that speed is not noticable to the human user of the system. However, as the number of pixels displayed on a screen increases, in order to increase the resolution of the displayed image, more and more bits of information must be accessed from the bit-mapped memory during the refresh interval. If the bit-mapped memory has but a single input and output port, the percentage of time during which the data processing unit can access the bit-mapped memory varies inversely with the number of bits per pixel for the display so long as the refresh interval remains constant. In addition, the speed of the memory must increase with the number of bits per pixel, since more bits must be output during a fixed period of time.

Multiport random access memories have been developed which provide for high-speed output of data to the video display and also for increased accessability of the memory contents to the data processing device. The multiport memories accomplish this by having a first port for random access and update of the memory by the data processing unit of the computer system and a second port for serial output of the memory contents to the video display independent from and asynchronous with the first port, thereby allowing access to the memory contents during output of data to the video display terminal. Examples of multiport random access memories are described in U.S. Pat. No. 4,562,435 (issued Dec. 31, 1985), U.S. Pat. No. 4,639,890 (issued Jan. 27, 1987), and U.S. Pat. No. 4,636,986 (issued Jan. 13, 1987), all assigned to Texas Instruments Incorporated.

The multiport random access memory described in said U.S. Pat. No. 4,636,986 has four random access input/output terminals, and four serial access input/output terminals, so that the single memory device appears to have four memory arrays. This allows a single random access to read or write four data bits simultaneously, with a single address value, and also allows a by-four serial output for purposes of data communication to the video display. An external parallel-to-serial register can then receive the by-four serial output bits, and shift them one at a time to the video display at the display refresh rate; this allows the memory serial register to shift at one-fourth the rate of the video display, reducing the speed requirements of the semiconductor memory.

Other uses of the by-four organization provide for enhanced image display capabilities. For example, the by-four organization is useful in multi-color displays, since the four bits associated with each address can be associated with a common display picture element ("pixel"). This configuration provides for the storage of a four bit binary code representative of color for each corresponding pixel of the video display. Another use of the four bits is to assign one of the bits for representing text, and the other three bits for representing color for a graphical background. The by-four memory thus facilitates the overlaying of a text message on a graphics image.

In such applications, where the image information is stored by multi-bit color codes in a bit-mapped system, often a large number of memory addresses, or pixel locations, contain the identical color code information. Such is the case where a large portion of the image is filled with a given color. In prior dual-port memory devices, such as those in the above-referenced U.S. patents, the operation required to perform such a "fill" would be repeated write operations to the necessary number of memory locations, applying the same input data for each write cycle. In addition, the representation of data points in such a filled image often results in the same color data being stored in a multiple of memory locations in close proximity to one another.

It is therefore an object of this invention to provide a dual-port memory device having an on-chip data register, for the storage of a data pattern which may be written into a number of memory locations without requiring the application of input data to the data pins of the memory.

It is another object to provide such a dual-port memory with such an on-chip data register which can either select the data in the data register or data at its input terminals to be written to the selected memory location on a cycle-by-cycle basis.

It is another object of this invention to provide such a dual-port memory to which the contents of the data register may be written to a number of adjacent memory locations during the same write cycle.

It is therefore yet another object of this invention to provide such a dual-port memory where certain information stored in the data register may be inhibited from being written into the memory while other bits stored in that register are written into the memory during a given write cycle.

Other objects and advantages of the instant invention will become apparent to those of ordinary skill in the art having reference to the following specification, in combination with the drawings.

The invention may be incorporated into a random access memory having multiple random access inputs. A data register is provided which is written into from the inputs as during a normal write cycle, but with the data register, rather than the memory array, being selected to receive the data. This selection is enabled by way of an additional special function input, in combination with other signals presented to the device. The data register stores multiple bits of data, corresponding to the number of inputs to the memory device, which can be applied as input data during subsequent write cycles. A multiplexer selects between the application of the data in the data register and the application of the data at the data inputs, such selection also made by way of the special function input in combination with other signals presented to the device. A write mask register is also provided so that certain bits of the data register can be selectively blocked from writing to the memory array. The device further includes a circuit for selectively disabling the final column decode stage of the device, so that the contents of the data register may be written to a plurality of columns for each of the input/outputs, providing for multiple bits to be written during a single write cycle.

FIG. 1 illustrates a schematic block diagram of the preferred embodiment of a dual-port memory constructed according to the invention.

FIG. 2 illustrates a schematic block diagram of the special function logic of the dual-port memory of FIG. 1.

FIGS. 3a and 3b illustrate schematic diagrams of circuitry for generating clock signals used by the logic of FIG. 2.

FIG. 4 illustrates a schematic diagram of combinational logic within the special function logic of FIG. 2.

FIG. 5a illustrates a timing diagram of a memory cycle for loading the write mask register during the early portion thereof.

FIG. 5b illustrates a timing diagram of a memory cycle for loading either the write mask register or the color register during a latter portion thereof.

FIG. 5c illustrates a timing diagram of a memory write cycle utilizing the contents of the write mask register loaded in a previous cycle.

FIG. 5d illustrates a timing diagram of a memory write cycle ignoring the contents of the write mask register without destroying its contents.

FIG. 6 is a register level illustration of a masked write operation.

FIG. 7 is a schematic diagram of a column decoder which incorporates the addition of a block write feature to the memory of FIG. 1.

FIG. 8 is a timing diagram of the operation of a block write cycle, using the circuitry of FIG. 7.

FIG. 9 is a register level illustration of a block write cycle, using the circuitry of FIG. 7.

FIG. 10 is a schematic block diagram of the dual-port memory of the invention in a computer system.

Referring now to FIG. 1, a functional block diagram of a dual port memory 1 constructed according to the instant invention, and containing an improved write mask feature, is illustrated. Similarly as the memory of said U.S. Pat. No. 4,636,986, incorporated herein by this reference, dual-port memory 1 receives and latches initial serial access address signals and random access address signals occurring on lines A0 through A8, clock signals RAS.sub.--, CAS.sub.-- and SCLK, write enable signal WE.sub.--, transfer enable signal TR.sub.--, and serial output enable signal SOE. It should be noted that only a single column address strobe CAS.sub.-- is received and utilized by dual-port memory 1 as the write mask feature is included therein. Dual-port memory 1 has eight random access input/output lines D0 through D7, rather than the four such input/output terminals of the memory of said U.S. Pat. No. 4,636,986; the invention to be described herein will of course be applicable to either organization, or other organizations of a dual-port memory. Accordingly, dual-port memory 1 contains eight arrays 2, each of which in this embodiment contains 128 kbits of storage organized in 512 rows and 256 columns. Accordingly, dual-port memory 1 of FIG. 1 contains 1 Mbit storage capability. Associated with each of the arrays 2 are sense amplifier banks 4, containing 256 sense amplifiers as are well known in the art for the sensing, restoring and writing of data from and into the dynamic memory cells of the arrays 2. There are eight serial data access input/output lines SD0 through SD7.

Looking to the serial side of dual-port memory 1, transfer gates 6 are connected to each of the bit lines in the arrays 2, similarly as in the dual-port memory of said U.S. Pat. No. 4,636,986, for transferring data from the arrays 2 into data registers 8, or vice versa. In this example, data registers 8 are 256-bit registers, so 256 bits of data are transferred by each bank of transfer gates 6; i.e., in each transfer cycle, 2048 bits of data are transferred. Serial logic 14 receives the serial clock signal on line SCLK, a serial output enable on line SOE and the transfer signal on line TR.sub.--, as well as signals from RAM logic 16, so that the transfer of data may be effected at the proper time, as in the memory of said U.S. Pat. No. 4,636,986.

Toggle counter/decoder 22 contains a counter and a decoder for selection of a storage element in each of data registers 8 to or from which serial input/output is to begin. Accordingly, toggle counter/decoder 22 receives the latched initial serial access address signal from RAM logic 16 on lines 21 which, as for the memory of said U.S. Pat. No. 4,636,986, selects the storage element position from which serial input or output is to begin. Serial logic 14 controls toggle counter/decoder 22 to load the latched initial serial access address value in a transfer cycle, as above, and also provides a signal to toggle counter/decoder 22 for each cycle of the clock signal on line SCLK so that the value of the counter in toggle counter/decoder 22 is incremented for each serial cycle. Toggle counter/decoder 22 provides the decoded value stored in its counter to each of pointers 10, one such pointer 10 associated with each of the data registers 8. The contents of data registers 8 are not shifted therewithin in each serial cycle as in the memory of said U.S. Pat. No. 4,636,986, but pointer 10 instead points to a bit position therewithin. The pointer is incremented to another bit position as each cycle of the clock signal on line SCLK increments the contents of the counter in toggle counter/decoder 22. In each of the data registers 8, the storage element, which is pointed to by the associated one of pointer 10, is connected for input and output purposes to the associated one of serial input/output buffers 12, one of said serial input/output buffers being associated with each of the eight arrays 2 and data registers 8. Serial input/output buffers 12 communicate data between the associated serial input/output terminal SD0 through SD7 and the storage element of its associated data register 8 which is pointed to by pointer 10. The signal on line SOE, as before, indicates to serial logic 14 whether the serial operation is a write or a read operation, and serial logic 14 controls the serial input/output buffers 12 accordingly. Serial input and output therefore occurs functionally in a fashion similar as that for the memory of said U.S. Pat. No. 4,636,986 for eight serial input/outputs, except that the serial register function is accomplished by a non-shifting data register 8 from which a storage element therewithin is selected in an incrementing manner.

On the random access side, RAM logic 16 performs the address latching and decoding as performed in the memory of said U.S. Pat. No. 4,636,986, and therefore receives the row address strobe and column address strobe signals RAS.sub.-- and CAS.sub.--, respectively, and address lines A0 through A8. The row address value appearing on address lines A0 through A8 is latched by the row address strobe signal RAS.sub.--, and is communicated to X decoder 18 via lines 19, so that X decoder 18 can select a row in each of the arrays 2 in response to the latched row address value that appears on lines 19. Similarly, the column address value appearing on address lines A0 through A7 (the column address signal on line A8 being unnecessary to select one of 256 columns) is latched by RAM logic 16 in response to column address strobe signal CAS.sub.--. The latched column address value is communicated from RAM logic 16 to Y decoders 20 by way of lines 21, each of the eight arrays 2 having a Y decoder 20 associated therewith. Each of the Y decoders 20 selects the desired column line which applies a signal to connect the desired bit line to its associated input/output buffer 24.

In addition to functions described in said U.S. Pat. No. 4,636,986, dual-port memory 1 has additional control over the random access data input/output functions. Such additional control is performed by special function logic 30. Each of the eight input/output buffers 24 is connected through special function logic 30 to the data terminals D0 through D7. The multiplexer 26 provides for selection of two write modes via distinct data paths from the data terminals through the circuitry of special function logic 30 and the multiplexer 26 to the buffers 24 (as further described below with reference to FIG. 2). For purposes of random access read, the output of input/output buffers 24 is received by output drive circuitry 31 and is communicated therethrough to the terminals of lines D0 through D7. Output drive circuitry 31 is constructed in any one of a number of well known configurations, and is enabled from the external signal on line TR.sub.-- under the control of RAM logic 16. For purposes of random access write, of course, output drive circuitry 31 will be disabled by RAM logic 16 to prevent a data conflict.

During a random access write cycle, line WTCLR from special function logic 30 controls multiplexer 26 to select either the data value appearing at data terminals D0 through D7 or the contents of a color register 50 within special function logic 30 for sending to input/output buffers 24 via lines 27, depending upon the function selected by the user. Special function logic 30 is also operable to control the write mask feature similar to that described above for the memory of said U.S. Pat. No. 4,636,986. Special function logic 30 is operable, however, to store the value of the write mask in a write mask register 54 so that the write mask value can operate for a plurality of cycles, and so that the write mask value may be recalled many cycles after it is initially loaded, and after intervening cycles of non-masked random access writes. The contents of write mask register 34, or a non-masked write signal, as desired, are applied by special function logic 30 to input/output buffers 24 by way of lines WCLK, as will be described hereinbelow.

Referring now to FIG. 2, the construction and operation of special function logic 30 will be explained in detail. Special function logic 30 contains latches for storing the value of the various inputs thereto in conjunction with each of the row address strobe RAS.sub.-- and column address strobe CAS.sub.-- signals making high-to-low transitions, in a similar manner as the row and column addresses on address lines A0 through A8 are latched into RAM logic 16 of FIG. 1. Line SF, upon which the special function signal is presented from a source external to dual-port memory 1, is connected to the D-input of D-type latches 32 and 34. The clock input of latch 32 is clock signal RAS' which is a delayed clock pulse generated by RAM logic 16 from row address strobe signal RAS.sub.--. The clock input of latch 34 is clock signal CAS' which is similarly a delayed clock pulse generated by RAM logic 16 from column address strobe signal CAS.sub.--. Special function logic 30 further contains latch 36 which receives at its D input the external transfer signal on line TR.sub.-- , and receives at its clock input the clock signal RAS'. Latch 38 receives the external write enable signal on line WE.sub.--, and also is clocked by clock signal RAS'.

The data input signals D0 through D7 are also latched relative to row address strobe RAS.sub.--, similarly as the signals discussed above, by latch 40 within special function logic 30. Latch 40 thus consists of eight latching circuits, each of which is clocked by clock signal RAS', for the storage of the eight data signals from the eight data lines D0 through D7. The output of latch 40 is connected to one input of a multiplexer 58, which has its output connected to the input of an eight bit write mask register 54. The contents of write mask register 54 correspond to which of the eight input/output buffers 24 of FIG. 1 will be enabled for a random access write mask operation. The output of write mask register 54 is connected to a first input of a multiplexer 60, which has its other input connected to power supply V.sub.dd. Each of the inputs to multiplexer 60 consist of eight parallel bits, with multiplexer 60 selecting between the eight bit output of write mask register 54 or an eight bit value of all "1" generated by V.sub.dd. Multiplexer 60 is controlled by line SELMSK from combinational logic 44. Line SELMSK is set by combinational logic 44 to a high logic level when the contents of write mask register 54 are to generate the signals on the eight lines WCLK, each of said lines WCLK associated with one of input/output buffers 24. A high logic level on a line WCLK causes its associated input/output buffer 24 to write the value on its one of lines 27 to the selected memory location in its array 2. Line SELMSK from combinational logic 44 being at a low logic level causes multiplexer 60 to apply power supply V.sub.dd to its output, signifying that all input/output buffers 24 are to perform a write operation, regardless of the contents of write mask register 54. It should be noted that multiplexer 60 is also controlled by the output of AND gate 59, which receives at its inputs clock signal W' and write enable signal WEN from combinational logic 44. The output of AND gate 59 times the application of the output from the multiplexer 60 to lines WCLK, so that the enabling signals on lines WCLK are applied to input/output buffers 24 at the proper time, and so that no such enabling signals are applied during read cycles.

The data input signals on lines D0 through D7 are also latched into eight bit latch 42, responsive to a clock signal W', which is generated by RAM logic 16 upon the later of CAS.sub.-- and WE.sub.-- going low, as discussed below. The output of latch 42 is connected to the input of an eight-bit color register 50. The output of the color register 50 is connected to a first input of the data multiplexer 26 to provide a first data path between the data terminals D0-D7 and the output of the multiplexer 26. The output of latch 42 is also connected directly to a second input of the multiplexer 26 to provide a second data path between the data terminals D0-D7 and the output of the multiplexer 26. Color register 50 is loaded with the output of latch 42 upon combinational logic 44 generating a high logic level on line LDCLR, in order to store a predetermined data pattern to be presented to the eight input/output buffers 24 during a subsequent write cycle when the color register is selected as the data source. As is evident from FIGS. 1 and 2, the data multiplexer 26 operates in conjunction with write mode circuitry to select between the contents of the color register 50 or the contents of the latch 42 for application to the input/output buffers 24 via lines 27. That is, the multiplexer 26 is responsive to the control signal WTCLR from combinational logic 44 in special function logic 30. A high logic level on line WTCLR causes the contents of color register 50 to be applied to lines 27. As described above, output drive circuitry 31 applies the value of lines 27 to lines D0 through D7 during read cycles.

The output of latch 42 is also applied, as described above, to a second input of multiplexer 58, to provide an alternative method for loading write mask register 54. As will be explained below in greater detail, combinational logic 44, responsive to the user selecting one of the two operation modes for loading write mask register 54, will generate a high logic signal on line LDMSK. Depending upon whether the contents of latch 40 (storing the value of lines D0 through D7 latched by RAS') or the contents of latch 42 (storing the value of lines D0 through D7 latched by WE') are desired, combinational logic 44 will control the application of the selected latch contents to write mask register 54 by line SEL40. That is, a logic high signal provided on line SEL40 controls the multiplexer 58 to select the output of latch 40 and a logic low signal on line SEL40 controls the multiplexer to select the output of latch 42.

Referring to FIG. 3a, the generation of clock signal RAS' is illustrated. The circuitry illustrated in FIG. 3a is resident within RAM logic 16 of FIG. 1. The row address strobe signal RAS.sub.-- generated externally from dual-port memory 1 is inverted by inverter 100 and, after the desired delay through delay stage 102, generates the signal RAS' referred to above. An additional inversion by inverter 104 generates clock signal RAS.sub.-- ', which will be discussed below. It should be noted, of course, that the delays necessary, and indeed additional delayed versions of the signals RAS' and RAS.sub.-- ' are easily generated by those of ordinary skill in the art for use throughout dual-port memory 1 for a multitude of control functions. The signals CAS' and CAS.sub.-- ' may of course be generated within RAM logic 16 in a similar fashion, or by any of a number of methods well known by those of ordinary skill in the art.

FIG. 3b illustrates the generation of the clock signal W' by RAM logic 16, such clock signal W' used in the circuit of FIG. 2. Line WE.sub.-- receives the externally generated write enable signal, which is gated by way of NOR gate 106 having its other input connected to line RAS.sub.-- '. The output of NOR gate 106, which is at a high level only when the write enable signal WE.sub.-- occurs during a RAS.sub.-- active period, is connected to a first input of NAND gate 108, which has its other input connected to line CAS'. As described above, the clock signal on line CAS' is a delayed and inverted version of column address strobe signal CAS.sub.--. The output of NAND gate 108 is at a low logic level upon both the output of NOR gate 106 and signal CAS' being at a high logic level; i.e., upon the later to occur of WE.sub.-- and CAS.sub.--. By way of the desired delay by delay stage 110 and inversion by inverter 112, the clock signal W' utilized by the circuit of FIG. 2 is generated.

The circuitry of combinational logic 44 is coupled through latches 32, 34, 36 and 38 to receive input control signals SF, TR.sub.-- and WE.sub.-- provided on control lines 33, 35, 37 and 39. With these signals the circuitry of combinational logic 44 generates internal logic control signals to execute different modes of operation for the dual port memory 1. Table 1 is a truth table for the These control signals control dual-port memory 1 to execute the operations of its various modes. Table 1 is a truth table for the various special modes of dual-port memory 1, certain of which will be further explained in detail hereinbelow.

As discussed above, control signal WTCLR is the signal generated by combinational logic 44 to cause data multiplexer 26 to select either the contents of color register 50 or the contents of latch 42 for application to the input/output buffers 24 of FIG. 1. Control signal LDCLR is a signal applied by combinational logic 44 to cause color register 50 to be loaded with the contents of latch 42. Control signal LDMSK is a signal generated by combinational logic 44 to write mask register 54, to cause write mask register 54 to be loaded with either the contents of latch 42 or the contents of latch 40, depending upon the state of SEL40 which controls the operation of multiplexer 58. The application of the contents of write mask register 54 to lines WCLK is enabled depending upon the logic state on line SELMSK from combinational logic 44. Accordingly, combinational logic 44 is constructed of such logic necessary to generate the appropriate control signals responsive to the inputs presented thereto, and as will be described with reference to FIG. 4.

Combinational logic 44 receives the outputs of latches 32, 34, 36, and 38 on lines 33, 35, 37, and 39, respectively, as well as clock signals RAS' and W' described above. The construction and operation of combinational logic 44 will be described herein as it enables each of the special functions referred to above in Table 1.

As described above, write mask register 54 may be loaded from either the contents of latch 40 or the contents of latch 42. Since latch 42 is loaded responsive to the clock signal W', occurring upon the later of CAS.sub.-- and WE.sub.--, not only can write mask register 54 be loaded in different ways, but write mask register 54 can also be loaded at different times in a cycle, allowing increased flexibility for the user of dual-port memory 1.

Referring to FIG. 5a, a timing diagram for the loading of write mask register from latch 40, i.e., during the first portion of the cycle, is illustrated. Table 1 indicates that write mask register 54 is loaded early when lines WE.sub.-- and SF are at a low logic level, and line TR.sub.-- at a high logic level, at the time that RAS.sub.-- makes its high-to-low transition, as shown in FIG. 5a. At this time, the value on data lines D0 through D7 is loaded into latch 40 (responsive to clock signal RAS'), and the values on lines SF, TR.sub.--, and WE.sub.-- are latched into latches 32, 36 and 38, respectively. The outputs of latches 32, 36 and 38 on lines 33, 37 and 39, respectively, are connected to the inputs of NAND gate 118 (lines 33 and 39 inverted by inverters 114 and 116). Accordingly, the output of NAND gate 118 will go to a low level upon the latched states of lines WE.sub.-- and SF at a low level and the latched state of TR.sub.-- being at a high level. This presents a logic low to one input of NOR gate 120, which has its other input controlled by clock signal RAS', delayed as desired by inverting delay stage 122 to allow the operation of the latches and logic to occur; upon the low-to-high transition of delayed clock signal RAS', the output of NOR gate 120 will go to a high level, generating a high level on line SEL40 to multiplexer 58 of FIG. 2, indicating that the output of latch 40 is to be selected. Line SEL40 is also connected to one input of OR gate 124, to generate a high level on line LDMSK. Line LDMSK is connected to write mask register 54, and upon making a low-to-high transition indicates that write mask register 54 is to be loaded with the value of the output of multiplexer 58 which, in the described case, is the contents of latch 40. By this operation, write mask register 54 is loaded during the first part of the memory cycle.

After the values of lines TR.sub.--, WE.sub.-- and SF are latched into their respective latches upon RAS.sub.-- going low, lines TR.sub.--, WE.sub.-- and SF are "don't cares" for purposes of the loading of write mask register 54 and can go to another logic level. Subsequent to the loading of write mask register 54, however, either a read or a write cycle may be performed by dual-port memory 1 depending upon the values placed on lines WE.sub.-- and TR.sub.-- (line TR.sub.--, as in the memory of said U.S. Pat. No. 4,636,986, serving as a random access output enable). FIG. 5a illustrates the more likely event of a write cycle occurring after the loading of write mask register 54 (the user's interest in performing a write operation is evidenced by the loading of write mask register 54). As shown in FIG. 5a, the row address value, i.e., the state of address lines A0 through A8 at the time of the RAS.sub.-- transition, is received during the time that write mask register 54 is being loaded; the row address decoding and selection occurs by way of RAM logic 16 and X decoder 18 in the well known RAM manner. The column address value is presented on lines A0 through A7 in conjunction with the column address strobe signal CAS.sub.--, as illustrated in FIG. 5a.

Table 1 indicates that the value of line SF at the time of the CAS.sub.-- transition determines whether the data received on lines D0 through D7 or the contents of color register 50 will be the data written to arrays 2. As shown in FIG. 2, latch 34 is loaded with the value of line SF responsive to clock signal CAS', which is a delayed and inverted signal relative to CAS.sub.--. Line 35 from the output of latch 34 is connected (after inversion by inverter 125) to one input of NOR gate 126. AND gate 127 receives at one of its inputs the output of NAND gate 118, which is at a low level as described above in the loading of write mask register 54; this of course forces a low logic level at the output of AND gate 127, which is presented to the other input of NOR gate 126. A high level will be generated at the output of NOR gate 126, and on line WTCLR, if the value of line SF at the time of the CAS.sub.-- transition is at a "1" logic level, and a low level on line WTCLR will be generated in the event that line SF is at a "0" level at the CAS.sub.-- transition. Line WTCLR is connected to the control input of data multiplexer 26 which applies the contents of color register 50 to lines 27 responsive to line WTCLR at a high logic level, and applies the contents of latch 42 to lines 27 when line WTCLR is at a low level. In this manner, combinational logic 44 is operable to select the data source for a write operation in the same memory cycle as a write mask register 54 load, said selection responsive to the value of line SF at the CAS.sub.-- transition.

Lines 33, 37 and 39 are also connected to the inputs of AND gate 128, line 33 being inverted by inverter 114 prior thereto. Accordingly, since the value of the WE.sub.-- line was at a logic "0" at the time of the RAS.sub.-- transition, the output of AND gate 128 is at a logic "0". The output of AND gate 128 is connected, through inverter 130, to line SELMSK which is connected to the control input of multiplexer 60. A high logic level on line SELMSK, as in this cycle where write mask register 54 is loaded responsive to the RAS.sub.-- transition, indicates that the contents of write mask register 54 are to be selected for generation of the signals on lines WCLK to input/output buffers 24. In addition, lines 33, 37 and 39 are also connected, with none inverted, to the inputs of AND gate 132; the output of AND gate 132 will also be at a logic low level, due to lines 33 and 39 being at logic low levels. The output of AND gate 132 is connected to inverter 134, which generates at its output the signal for line WEN connected to one input of AND gate 59 in FIG. 2. Accordingly, since the output of AND gate 132 is at a low level, line WEN is at a logic high level, enabling clock signal W' to gate, via multiplexer 60, the contents of write mask register 54 to lines WCLK. As described above, the signals on lines WCLK are the write clocks to input/output buffers 24, which will effect the writing of the data on lines 27 to arrays 2, with those input/output buffers associated with stored "0"s in write mask register 54 not performing a write operation. Therefore, upon the later of WE.sub.-- and CAS.sub.-- making a high-to-low transition while the other is active low (i.e., the transition of WE.sub.-- to a low level and back to a high level in conjunction with RAS.sub.-- transition does not generate the W' clock signal), a clock signal will be generated on line W', which will appear to gate the selected input of multiplexer 60 to lines WCLK to effect the write operation by input/output buffers 24.

FIG. 6 illustrates the masked write operation on a register-level diagram. An example of the eight storage elements of a memory location prior to the masked write operation is shown therein as 2.sub.n, with each of the eight storage elements corresponding to the addressed location within each of arrays 2 of dual-port memory 1. The data source containing the data to be written in this example is color register 50, an example of the contents of which illustrated in FIG. 6 as 10101010.sub.2. The contents of write mask register 54 are illustrated in FIG. 6 as writing only to the four center storage elements, i.e., the third through sixth least significant storage elements of the memory location; conversely, the write operation is "masked" relative to the two most and two least significant storage elements of memory location 2.sub.n. Upon performing the write cycle described above, where the contents of color register 50 is written in a masked write, the updated contents of the addressed memory location is shown in FIG. 6 as 2.sub.n+1. It should be apparent that only the center four storage elements are written with the contents of color register 50, with the two most and two least significant bits remaining the same as prior to the write operation.

As mentioned above, dual-port memory 1 can load write mask register 54 during the latter portion of the memory cycle, by way of latch 42 clocked by clock signal W'. FIG. 5b illustrates a timing cycle for the loading of write mask register in the latter portion of the memory cycle. Lines 33, 37 and 39 are, as discussed above, connected to the inputs of AND gate 132 without any of the three signals being inverted, so that the output of AND gate 132 is at a high level when all three are at a high level. This corresponds to Table 1, where the late loading of write mask register 54 is enabled by lines SF, WE.sub.-- and TR.sub.-- being at a high logic level at the RAS.sub.-- transition. The high level at the output of AND gate 132 presents, via inverter 134, a low level on line WEN which disables any write clock signals from being presented on lines WCLK, thereby preventing a write operation to arrays 2. The output of AND gate 132 is connected to one input of NAND gate 136, which has line W' connected to its other input; until the later of WE.sub.-- or CAS.sub.-- (after the RAS.sub.-- transition), the output of NAND gate 136 will remain at a high logic level. NOR gate 138 receives the output of NAND gate 136 at one input, and receives the output of latch 34 on line 35 at its other input; as stated above, latch 34 stores the value of line SF at the time of the CAS.sub.-- transition. Table 1 indicates that write mask register 54 is loaded when line SF is at a "0" level at the CAS.sub.-- transition, when lines SF, WE.sub.-- and TR.sub.-- are all high at the RAS.sub.-- transition. Accordingly, for load of write mask register 54, line 35 will be at a low level responsive to clock signal CAS' latching the low level on line SF into latch 34.

The loading of write mask register 54 is completed upon the later of WE.sub.-- or CAS.sub.-- (after the RAS.sub.-- transition.sub.--). The example illustrated in FIG. 5b shows WE.sub.-- making its transition after CAS.sub.--, and the following description will use this example. Referring back to FIG. 2, latch 42 will be loaded with the value on lines D0 through D7 upon clock signal W', which is generated upon the later of WE.sub.-- and CAS.sub.-- making a high-to-low transition (while the other is active; see FIG. 3b). FIG. 5b illustrates the presentation of the contents of write mask register 54 as "MASK" on data lines D0 through D7 at the time of WE.sub.-- going low. In addition, clock signal W' causes the output of NAND gate 136 to go to a low level, thereby generating a high level at the output of NOR gate 138. This generates, via OR gate 124, a high level on line LDMSK which causes a load of write mask register 54 with the output of multiplexer 60. Since the output of NAND gate 118 is at a "1" level (line 39 being at a high level), line SEL40 will be at a low level by operation of NOR gate 120. As described above, a low level on line SEL40 will control multiplexer 60 to select the contents of latch 42 for application to write mask register 54 upon the LDMSK signal generated above; latch 42 is storing the value of data lines D0 through D7 loaded thereinto at this time. In this manner, combinational logic 44 effects the late load of write mask register 54 by way of the timing of FIG. 5b, with line SF at a low level at the CAS.sub.-- transition.

Color register 50 is loaded in the same manner as write mask register 54 in the late-load mode, only with line SF at a high level at the CAS.sub.-- transition as indicated in Table 1. This is effected by NOR gate 140 which receives the output of NAND gate 136 discussed above, and which receives line 35 after inversion by inverter 125. A high logic level on line SF at the CAS.sub.-- transition results in a low level at one input of NOR gate 140. Upon the later of WE.sub.-- and CAS.sub.-- making a high-to-low transition, the output of NAND gate 136 goes to a low level as described above, driving the output of NOR gate 140 to a high level. The output of NOR gate 140 is line LDCLR which is connected to color register 50 and which, at a high level, causes color register 50 to be loaded with the contents of latch 42. Latch 42, as described above, is loaded with the value of data lines D0 through D7 responsive to clock signal W' (i.e., the value "CONTENTS" of FIG. 5b).

It should be noted that for either the loading of color register 50 or of the late loading of write mask register 54 random access of dual-port memory 1 is inhibited. As illustrated in FIG. 5b, this causes the values of the addresses on lines A0 through A8 to be "don't cares" at both the RAS.sub.-- and CAS.sub.-- transitions.

It is useful, as discussed hereinbefore, to be able to use the contents of write mask register 54 in a multiple of memory cycles, as well as to be able to perform unmasked write operations without requiring the reloading of the write mask information prior to performing a subsequent masked write operation. Accordingly, Table 1 indicates that certain modes of operation are available to repeatedly use the contents of write mask register, as well as to perform unmasked write operations while retaining the write mask information in write mask register 54. Special function logic 30, and combinational logic 44 therewithin, are designed to accomplish these functions.

FIG. 5c is a timing diagram illustrating the operation of a masked write cycle, without the reloading of write mask information, i.e., utilizing the prior contents of write mask register 54. Upon the RAS.sub.-- transition, lines TR.sub.-- and SF are at a high logic level, while line WE.sub.-- is at a low logic level. As before, latches 32, 36, and 38 latch in these values upon clock signal RAS', for receipt by combinational logic 44. Referring to FIGS. 2 and 4, since the output of AND gate 128 is at a logic low level for this combination, line SELMSK will be at a high level, so that the contents of write mask register 54 will be selected for application to lines WCLK upon the output of AND gate 59 going to a high level. Since this combination of lines TR.sub.--, SF and WE.sub.-- on the RAS.sub.-- transition causes the output of AND gate 132 to be at a low level, so that line WEN will be at a high level, which allows the later of WE.sub.-- and CAS.sub.-- going low to apply the output of multiplexer 60, i.e., the contents of write mask register 54, to lines WCLK.

For the above-described combination of lines TR.sub.--, SF and WE.sub.-- on the RAS.sub.-- transition, however, the contents of write mask register 54 applied in this cycle will be unchanged from its prior state. The reloading of write mask register 54 is precluded by combinational logic 44, since the low level output of AND gate 132 also causes the output of NAND gate 136 to be at a high level and, in turn, the output of NOR gate 138 to be at a low level. Since the output of NAND gate 118 is at a high level for the above combination of lines TR.sub.--, SF and WE.sub.-- on the RAS.sub.-- transition shown in FIG. 5c, a low level is forced at the output of NOR gate 120. Therefore, both inputs to OR gate 124 are low, which forces a low level on line LDMSK, precluding write mask register 54 from being reloaded. The prior contents of write mask register 54 are thereby retained, and are utilized in the write cycle as selected by line SELMSK described above.

Depending upon the state of line SF upon the CAS.sub.-- transition, the data applied to lines 27 for the masked write operation can be either the contents of color register 50 or the value of data lines D0 through D7 which has been latched by latch 42 upon clock signal W'. Combination logic 44 illustrated in FIG. 4 allows this selection according to the truth table of Table 1, by way of AND gate 142 having its three inputs connected to lines 33, 37 and 39, with line 39 inverted by inverter 116. The output of AND gate 142 thus will have its output at a high logic level responsive to the combination upon the RAS.sub.-- transition of lines TR.sub.-- and SF at a high logic level and while line WE.sub.-- at a low logic level. The output of AND gate 142 is connected to a first input of OR gate 144, driving the output of OR gate 144 high when it is at a high level. The output of OR gate 144 is connected to a first input of NAND gate 146, which has its other input connected to clock signal W' described above, and its output connected to an input of AND gate 127. NAND gate 146 therefore has its output driven low when the output of AND gate 142 is at a high level upon the low-to-high transition of clock signal W'. The low level of the output of NAND gate 146 forces a low level at the output of AND gate 127 which presents a low level at an input of NOR gate 126 as discussed above. Similarly as discussed above for the cycle of FIG. 5a, line WTCLR is driven high or low by operation of line 35 from latch 34, which stores the value of line SF upon the CAS.sub.-- transition, thereby controlling data multiplexer 26 to select the contents of color register 50 for application to lines 27 to input/output buffers 24, or to select the value of data lines D0 through D7. FIG. 5c illustrates the timing required for data lines D0 through D7 to present valid data ("DATA") in the event that such input data is the desired data source. As described above, latch 42 latches the input data upon clock signal W', with the output of latch 42 applied to one input of data multiplexer 26, for selection if desired by the user.

The contents of write mask register 54 may be ignored for a write operation, yet retained for subsequent masked write operations, by a special cycle effected by special function logic 30, and combinational logic 44 therewithin. The timing of an example of such a cycle is illustrated in FIG. 5d. Upon the RAS.sub.-- transition, as stated in Table 1, lines TR.sub.-- and WE.sub.-- are at a high logic level while line SF is at a low level; as before, these values are latched into latches 36, 38 and 32, respectively, by clock signal RAS'. This combination, presented on lines 37, 39 and 33 (line 33 inverted by inverter 114) causes the output of AND gate 128 to go to a "1" logic level, placing a low logic level on line SELMSK so as to cause multiplexer 60 to select V.sub.dd for application to lines WCLK at the proper time, ignoring the contents of write mask register 54. Since the contents of latch 32, corresponding to the state of line SF low on the RAS.sub.-- transition, is at a low level, the output of AND gate 132 is also low, placing a high level on line WEN so that clock signal W' will be passed through to multiplexer 60 for generation of the high logic levels on all of lines WCLK, due to line SELMSK being low. As for the prior write cycles, FIG. 5d illustrates that line WE.sub.-- is driven low after the CAS.sub.-- transition, to effect the write operation via write signal W'.

Similarly as in the case of FIG. 5b, loading of write mask register 54 is precluded, since the outputs of AND gate 132 is low and the output of NAND gate 118 is high for the combination of lines TR.sub.-- and WE.sub.-- high with line SF low upon the RAS.sub.-- transition. Since no new value is loaded into write mask register 54 (line LDMSK staying low), the prior value stored therein is retained. Accordingly, a subsequent cycle such as that illustrated in FIG. 5c will cause a masked write operation, using the write mask information retained in write mask register 54, without the need to reload the write mask information.

As discussed above relative to FIG. 5c, the state of line SF at the time of the CAS.sub.-- transition will control whether the write cycle of FIG. 5d uses color register 50 as the data source (line SF being a "1") or uses the value of data lines D0 through D7 ("DATA" of FIG. 5d) as the data source. Combinational logic 44 effects this selection since the output of AND gate 128 is connected to a second input of OR gate 144, thereby having the same effect on the generation of the WTCLR signal by NOR gate 126 as the output of AND gate 142 discussed above relative to the cycle of FIG. 5c.

In the use of a dual-port memory such as dual-port memory 1 shown in FIG. 1 in a video system, often a number of successive memory locations may be written with identical data. For example, where dual-port memory 1 contains a bit-mapped representation of a graphics image, a large area of the displayed image may be filled with a certain color. Accordingly, it would be useful to write identical data to multiple locations in dual-port memory during a single cycle.

Referring now to FIG. 7, a block diagram of Y decoder 20 is illustrated which contains circuitry for performing the feature of addressing adjacent columns therewithin in a single cycle, hereinafter referred to as the "block write" feature. While the operation of dual-port memory 1 may be enhanced by the feature described hereinbelow relative to FIG. 7, it should be noted that dual-port memory described hereinabove is fully operable without the block write feature. It should be noted that FIG. 7 illustrates Y decoder 20 for a single array 2 in dual-port memory 1; of course, the circuitry illustrated in FIG. 7 will be associated with each of arrays 2 shown in FIG. 1. Y decoder 20, as described above, receives the latched values of the column address received on address lines A0 through A7; these latched column address values are represented by lines AY0 through AY7 on FIG. 7. Since only 256 columns are present in each of arrays 2, the value of address line A8 latched by the CAS.sub.-- signal is not utilized in the column decoding operation. Pre-decoder 200 receives lines AY2 through AY7, and decodes these six bits into 64 output lines 202, only one of which will be enabled at any given time by being at a high logic level. When at a high level, each output line 202 selects a different group of four columns in its associated array 2.

Associated with each group of four columns is column select circuit 204; only one column select circuit 204 is illustrated in FIG. 7, for the sake of simplicity. The associated output line 202 from pre-decoder 200 is connected to one input of AND gate 206, and to one input of AND gate 208, within the column select circuit 204. The signal on line WTCLR from special function logic 30 is applied to the second input of AND gate 206 and after inversion by inverter 207, is connected to the second input of AND gate 208. As described above, the signal WTCLR is generated when the contents of color register 50 are to be written into arrays 2. The feature described herein for addressing multiple columns within each of arrays 2 is enabled by the same signal WTCLR. Also included within column select circuit 204 is a one-of-four decoder 210 which performs the actual decoding of the two least significant column address bits on lines AY0 and AY1, in selecting the one column of the selected group of columns within array 2 which is to be addressed in the random access mode. One-of-four decoder 210 drives four lines 214.sub.n through 214.sub.n+3, depending upon the value of the signals on lines AY0 and AY1. Pass transistors 212.sub.n through 212.sub.n+3, each connects its corresponding line 214.sub.n through 214.sub.n+3 to the gate of its corresponding transistor 220.sub.n through 220.sub.n+3. The gates of pass transistors 212.sub.n through 212.sub.n+3 are controlled by the output of AND gate 208. Accordingly, in the event that the block write feature is selected, i.e., line WTCLR is at a high logic level while the corresponding output line 202 is selecting the group, the result of one-of-four decoder 210 will be ignored, because the AND gate 208 is disabled.

Column select circuit 204 further receives the even bits of the contents of latch 42, shown in FIG. 7 as lines 43.sub.0, 43.sub.2, 43.sub.4 and 43.sub.6. As described above, latch 42 stores the value of data input lines D0 through D7 received at the time of the later of the write enable signal on line WE.sub.-- or the column address signal on line CAS.sub.-- in each cycle. Each of lines 43.sub.0, 43.sub.2, 43.sub.4 and 43.sub.6 is connected to the conduction path of a different one of the pass transistors 216.sub.n through 216.sub.n+3, each of which has its gate connected to the output of AND gate 206. The other end of the conduction path of the pass transistors 216.sub.n through 216.sub.n+3 is connected to the gate of its corresponding transistor 220.sub.n through 220.sub.n+3.

Each of the transistors 220.sub.n through 220.sub.n+3 connects the input/output buffer 24 associated with array 2 to the sense amplifer 4 associated with its column, in order to accomplish the write operation for the selected columns, in a manner well known in the art. For the normal operating mode where line WTCLR is not enabled, the output of AND gate 206 is at a logic low, disabling lines 43.sub.0, 43.sub.2, 43.sub.4 and 43.sub.6 from affecting the state of transistors 220.sub.n through 220.sub.n+3. At the same time, the output of AND gate 208 for the column select circuit 204 selected by pre-decoder 200 will be at a logic high level, allowing the result of one-of-four decoder to control the connection of the associated input/output buffer 24 to the sense amplifier 4 for the one selected column.

When the block write feature is selected by the state of lines WE.sub.--, SF and TR.sub.-- as shown in Table 1 for the enabling of line WTCLR by combinational logic 44, the output of AND gate 206 will be at a high level in the column select circuit 204 for the group of four columns which are selected by pre-decoder 200 responsive to lines AY2 through AY7. In this event, the state of lines 43.sub.0, 43.sub.2, 43.sub.4 and 43.sub.6 will determine which of transistors 220.sub.n through 220.sub.n+3 will be conductive, and indeed allows the connection of up to all four of the columns, in the group, to be connected to the input/output buffer 24. The contents of the stage of color register 50 corresponding to the array 2 will then be written into all of the columns selected by the state of lines 43.sub.0, 43.sub.2, 43.sub.4 and 43.sub.6, from latch 42.

Referring now to FIG. 8, a timing diagram illustrates the operation of the block write feature. As is evident from Table 1 above, the contents of color register 50 are written in write cycles when line TR.sub.-- is high at RAS.sub.-- going active with either line WE.sub.-- or line SF low at that time, in conjunction with line SF being high when column address signal CAS.sub.-- goes active. According to Table 1 and as illustrated in FIG. 8, the write operation of the color register (and, in this embodiment, the block write feature), requires at the time that row access strobe signal RAS.sub.-- goes active in its low state, that line TR.sub.-- is high, and that the logical AND of WE.sub.-- and SF is low; at the time that column access strobe signal CAS.sub.-- goes active, line SF must be in its high state. With the block write mode thus enabled, the value of the even bits of the data input signal on lines D0, D2, D4 and D6 at the time of the later of CAS.sub.-- or WE.sub.-- going active designates the columns in the group of four which are to be written with the value of the data stored in the color register 50 for the corresponding array 2. As explained above, all four of such columns are addressable in this block write mode, thereby providing the feature that four columns in each of the eight arrays 2 may be written in a single cycle.

Referring again to Table 1, in the event that both line SF and line WE.sub.-- are low at the time RAS.sub.-- goes active, the masked write operation will be enabled along with the block write feature. In this way, the contents of color register 50 may be written to multiple columns (within a group of four), to only selected arrays. Referring to FIG. 9, a register level illustration of the application of the color register 50 and write mask register 54 is illustrated in modifying the contents of the memory locations in each of the arrays 2 associated with two columns COL.sub.n and COL.sub.n+1. As described above, columns n and n+1 would be selected in the event that data lines D0 and D2 had a "1" logic level, and data lines D4 and D6 had a "0" logic level, at the time of write enable line WE.sub.-- going active after CAS.sub.-- is active in the timing of FIG. 8. As in the example of FIG. 6, only the third through sixth least significant memory locations are written with the contents of color register 50. According to the block write feature explained above, however, this masked write operation takes place simultaneously in selected columns COL.sub.n and COL.sub.n+1.

In FIG. 10, dual port memory 1 connects to data processing unit 1002 through the signals D0-D7, SF, WE.sub.--, TR.sub.--, RAS.sub.--, CAS.sub.--, A0-A8, SCLK and SOE, previously described. Dual port memory 1 connects to video display 1003 through signals SD0-SD7 previously described.

While the invention has been described in detail herein with reference to its preferred embodiment, it is to be understood that this description is by way of example only, and is not to be construed in a limiting sense. It is to be further understood that numerous changes in the details of the embodiment of the invention, and additional embodiments of the invention, will be apparent to, and may be made by, persons of ordinary skill in the art having reference to this specification. It is contemplated that such changes and additional embodiments are within the scope and true scope of the invention as claimed below.