Integrated High Gain Amplifier

This invention relates to an integrated high gain amplifier and more particularly to a high gain amplifier in which the gain is increased by controlling the impedance at the high impedance node of the amplifier.

A prior art circuit for boosting impedance is described by G. M. Cotreau in a paper entitled "An Opamp With 375 V/.mu.s Slew Rate, .+-.100 MA Output Current, IEEE International Solid State Circuits Conference", Feb. 14, 1985. The method cancels h.sub.08 or r.sub.mu of cascode devices to raise the gain of the amplifier. The method has the drawback that it creates a voltage offset and a drift component that is sensitive to device matching. The increase in gain is limited by device matching.

It is the object of this invention to provide an integrated amplifier circuit in which the increase in gain increases the DC precision and does not degrade the AC performance of the amplifier.

It is another object of this invention to provide a high gain integrated amplifier in which the gain can be trimmed.

It is a further object of the invention to provide a high gain integrated amplifier in which the impedance cancellation is differential, thereby avoiding offset degradation.

It is a further object of the invention to provide an amplifier in which the gain is not limited by device matching.

The foregoing and other objects of the invention are achieved in an amplifier which has a high impedance node, a transistor whose emitter base voltage changes with swing on the high impedance node, a sense circuit which detects changes in the high impedance node voltage via the transistor emitter base and responds to the swing to couple current to the high impedance node to thereby control the gain.

The foregoing and other objects of the invention will be more clearly understood from the following description when read in connection with the accompanying drawings in which:

FIG. 1 is a schematic diagram of an integrated high gain amplifier in accordance with one embodiment of the invention;

FIG. 2 is a schematic diagram of an integrated high gain amplifier in accordance with another embodiment of the invention;

FIG. 3 is a schematic diagram of an integrated high gain amplifier in accordance with still another embodiment of the invention;

FIGS. 4,5,6,7,8,9,10 and 11 show circuits in accordance with still other embodiments of the invention; and

FIGS. 12,13,14,15 and 16 show circuits for generating the compensating current, I.sub.Z.

This invention relies on the ability to sense the collector voltage of a common-base configuration transistor by measuring the change in voltage at the emitter. A common base configuration (or cascode) consists of a transistor with a fixed base voltage whose input is its emitter current and whose output is its collector current. As the collector-to-emitter voltage is changed the output current changes. In the linear (non-saturation) region the output impedance of the transistor is due to the Early effect and can be characterized at a given operating point. The change in collector current is simply the ratio of the voltage change to the Early Voltage (a measurable characteristic of the transistor commonly denoted by V.sub.a). The change in collector current gives rise to a change in base-to-emitter voltage of the transistor. Using the well known exponential relationship between collector current and base-to-emitter voltage of the transistor the change can be calculated in terms of the thermal voltage, V.sub.t, the Early Voltage, V.sub.a, and the change in collector voltage. This relationship can be approximated by noting that the change in collector voltage is usually much less than the Early Voltage. With this assumption there is a substantially linear relationship between the change in collector voltage and the change in emitter voltage.

An amplifier incorporating the invention is shown in FIG. 1. The amplifier has a single gain stage configuration known as a folded cascode. The amplifier operates by taking a differential input voltage which appears across the bases of Q.sub.1, Q.sub.2, and R.sub.1, R.sub.2, (R.sub.1, R.sub.2 are optional) and converting it to a differential current which is subtracted from current sources I.sub.2, I.sub.3. Resistors R.sub.1, R.sub.2 are optional and can be eliminated if other circuit components are correctly chosen. The difference currents flow through Q.sub.3, Q.sub.4. The current through Q.sub.3 is inverted and summed by the current mirror (made up of Q.sub.5, Q.sub.6, Q.sub.7, Q.sub.8, R.sub.3, R.sub.4) with the current from Q.sub.4 at the high impedance node labeled V.sub.Z. The differential current is converted back to a voltage by the total impedance at V.sub.Z which is shown symbolically by resistor R.sub.Z. The voltage V.sub.Z is then buffered by a unity gain stage to the output. The voltage gain of the amplifier is determined by R.sub.Z and the transconductance of the input section.

In this invention, the voltage gain is increased by canceling the effect of R.sub.Z as much as possible. The change in voltage at V.sub.Z (as the output swings) is sensed by looking at the change in voltage between the emitters of Q.sub.3, Q.sub.4 (or alternatively, Q.sub.5, Q.sub.6). As the collector of Q.sub.3 does not move, its emitter voltage remains constant. The emitter voltage of Q.sub.4 changes as discussed above. The swing of V.sub.Z causes a current to flow in R.sub.Z. The differential pair Q.sub.Z1, Q.sub.Z2 senses this swing via the emitters of Q.sub.3 and Q.sub.4 and compensate for the current flow. Qualitatively, this can be seen if one considers V.sub.Z increasing so that current flows into R.sub.Z. The flow of current into R.sub.Z is provided from the collector of Q.sub.4. The effect of R.sub.Z can be eliminated if the same amount of current can be subtracted from Q.sub.6. The emitter-to-base voltage of Q.sub.4 will increase which will cause the current in Q.sub.Z1 to increase and the current in Q.sub.Z2 to decrease. The current in Q.sub.7 and Q.sub.8 will decrease because of the decrease in Q.sub.Z2 current. The increase in Q.sub.Z1 current and the decrease in Q.sub.8 current combine to decrease the current in Q.sub.6. If the current I.sub.Z is selected correctly, the decrease in Q.sub.6 current will cancel the effect of R.sub.Z which will boost the voltage gain of the amplifier to a theoretical value approaching infinity. The differential nature of this circuit leads to a low voltage offset contribution because the DC balance of the amplifier is not greatly affected. In fact, the circuit tends to reduce the built-in offset of the circuit due to the imbalance in collector-to-emitter voltages of Q.sub.3, Q.sub.4.

The current I.sub.Z is set to a value such that the change in current R.sub.Z (due to changes in V.sub.Z) is equal to the change in current between Q.sub.Z1, Q.sub.Z2 (due to changes in V.sub.Z). Thus, they cancel the currents in the amplifier. The result is dependent solely on the Early Voltage of the cascode device and inversely proportional to the impedance R.sub.Z. For the nulling to be constant over temperature and processing, the temperature and process dependence of R.sub.Z and the Early Voltage should be incorporated into I.sub.Z. As an example, if the value of R.sub.Z is due primarily to r.sub.mu of transistor Q.sub.4. then R.sub.Z =(Beta.sub.Q4)*(Va.sub.Q4)/Ic.sub.Q4. The value of I.sub.Z is then simply 2*Ic.sub.Q4 /Beta.sub.Q4 =2*Ib.sub.Q4.

Many different methods of generating I.sub.Z exist such as mirroring and scaling I.sub.b of a similar pnp elsewhere in the circuit. Another method is to use a pinch resistor constructed similarly to the pnp. Using a pnp-type pinch resistor insures that the current will track variations in the pnp due to process and temperature. For further accuracy I.sub.Z can be trimmed using techniques such as fuse blowing or cutting, zener zapping, or laser trim of thin film resistors. Further enhancements can be made so that the nulling is maintained over changes in the power supply voltages.

Some of these enhancements can be seen in FIG. 2. In this circuit Q.sub.16, Q.sub.17 are cascode transistors that serve the same function as Q.sub.3, Q.sub.4 in FIG. 1. A more complex current mirror is used composed of Q.sub.9, Q.sub.10, Q.sub.11, Q.sub.12, Q.sub.32, Q.sub.33, Q.sub.34, R.sub.7, R.sub.8, R.sub.19. The high impedance node is at the collector of Q.sub.10 and the collector of Q.sub.16. This node is buffered by emitter follower Q.sub.54 which is biased by current source Q.sub.13, R.sub.9 and its cascode device Q.sub.35. The voltage change on V.sub.Z is sensed at the emitters of Q.sub.9 and Q.sub.10 which are cascode devices. The transistors which sense the voltage are Q.sub.40, Q.sub.41 with their output currents being reinserted in the mirror at the convenient low impedance nodes at the emitters of Q.sub.9, Q.sub.10. The current "I.sub.Z " is formed by pinch resistor R.sub.p2 (which is trimmed), and Q.sub.38, Q.sub.39, Q.sub.51. The prime contributor to lowering the impedance at V.sub.Z is the r.sub.mu of Q.sub.16. The resistor R.sub.p2 is similar in structure to pnp Q.sub.16 to track its variations over processing and temperature. The rest of the current source is composed of Q.sub.39 and cascode device Q.sub.51. Device Q.sub.38 compensates the current for changes in power supply voltage.

Another embodiment of the invention is shown in FIG. 3. In this embodiment the sense voltage is at the emitters of cascode devices Q.sub.16, Q.sub.17. The sense devices Q.sub.N1, Q.sub.N2 feed their outputs into low impedance nodes at the emitters of Q.sub.5, Q.sub.6 in the current mirror. The current "I.sub.Z " is set by a pnp-type pinch resistor R.sub.p1 and the voltage drop set up between V.sup.+ and V.sub.bias minus the V.sub.be 's of Q.sub.16, Q.sub.17, Q.sub.N1, Q.sub.N2. This is a simpler implementation which may or may not employ trimming.

Referring to FIG. 1, there are two possible sense positions: at the emitters of Q.sub.3, Q.sub.4 ; or at the emitters of Q.sub.5, Q.sub.6. The voltage can be sensed differentially by either npn or pnp transistors. The differential correction current can be inserted at different low impedance points: the emitters of Q.sub.3, Q.sub.4 ; the emitters of Q.sub.5, Q.sub.6 ; or the emitters of Q.sub.7, Q.sub.8. The current I.sub.Z can be created in many different ways: current mirrors, pinch resistors, regular resistors. The current I.sub.Z should depend on the primary contributors to lowering R.sub.Z in order to optimize the effect and its generation should relate to those contributors so that it tracks changes in processing and temperature.

Some of the variations on the basic circuit of FIG. 1 are shown in FIGS. 4-9. Other variations include inverting the folded cascode so that the mirror is formed of pnp transistors and the cascode transistors are npn's. This variation, shown in FIG. 10, has two sense positions also: V.sub.1 and V.sub.2, and can use either pnp or npn differential pairs. Alternatives can be found by providing cascode transistors differently such as in the circuits of FIG. 3 or FIG. 11. Methods of generating I.sub.Z are too numerous to include, but some representative methods are shown in FIG. 12-16.

There are many variations on the basic circuit. The common ingredients are: sensing the voltage swing at the high impedance node of a gain stage by looking at the change in voltage at the emitter of a cascode device feeding the high impedance node; sensing the voltage differentially so as not to degrade input offset voltage; generation of a compensating current that tracks the impedance to be canceled; returning a compensating correction current to low impedance nodes; and optionally trimming the compensating current to optimize the gain.