Fuzzy Computer

1. Field of the Invention

This invention relates to fuzzy computers, fuzzy processors, fuzzy controllers, and MAX circuit composite devices, along with circuits used in same, including grade-controllable membership function circuits, grade-controllable membership function generator circuits, and center of gravity determination circuits which act as useful circuits for defuzzifiers which convert fuzzy quantities into definitive values.

2. Prior Art Statement

A great human mind created the digital computer through the harmonization of the elements of the concept of the stored program, Boolean algebra and binary hardware which carries out stable operations. Iteration of these operations makes possible the development of complex logical structures and complex data processing techniques and the like. The stability of these operations gives the digital computer excellent reliability, so digital computer systems are becoming larger and larger. As long as the program does not include any human mental information, digital computers can run any type of program, hence their appellation as the "universal machine." The appearance of the digital computer system is having profound effects on the everyday life and culture of man.

Another great human mind created an extremely important concept, that of "fuzziness" through the study of how man thinks and how men communicate between themselves. L.A. Zadeh proposed the concept of the fuzzy set in 1965. Since then, while there have been many papers published on theoretical studies of fuzziness, there have been few reports on its practical application, and in fact, such work has only been carried out with the help of binary digital computers.

Research into fuzziness has emphasized that human knowledge is based on accumulated experience which is summed up as linguistic information such as expert knowledge. This linguistic information is generally endowed with vagueness, ambiguity, inaccuracy, and incompleteness so it can be characterized as membership functions. The size of the membership can be expressed by numerical values in the region from 0.0 to 1.0, varying within this range.

For linguistic information to be handled by a digital computer, the size (value) of the membership is represented by a binary code. In binary electronic circuits, this value represented by binary code is repeatedly stored, transferred and finally calculated over and over according to a stored program. Thus there is a problem with the processing of fuzzy information by digital system in that they require large amounts of time to do so. In addition, the binary-coded values require incredibly large amounts of storage and vast numbers of devices used for calculation. While the digital computer is a universal machine as described above, it is not necessarily most suited for the realtime processing of fuzzy information. This has prompted searches for other types of machines which can efficiently process fuzzy information at high speed.

Recent fuzzy computer systems represent fuzzy information including fuzzy membership functions, results of fuzzy inferences and such as electrical signals (voltage or current) distributed among a plurality of lines. One often needs to select a single definitive value from the fuzzy information represented by an electrical signal distribution provided as output from fuzzy controllers or fuzzy computers. The circuits which convert fuzzy information to definitive values are called defuzzifiers, an example of which is a center of gravity determination circuit.

A center of gravity determination circuit typically comprises multiplication circuits, addition circuits and division circuits. The hardware for such multiplication circuits and division circuits is complex and not readily adjustable, while they are also limited in dynamic range.

An object of this invention is to provide a hardware system suited to the processing of fuzzy information, and more particularly, a system with a simple structure known as a fuzzy processor.

Another object of this invention is to realize in an extremely simple structure a MAX circuit which is particularly useful in fuzzy inference calculating devices or fuzzy processing devices known as fuzzy controllers, fuzzy computers or fuzzy processors.

The fuzzy processor of this invention is characterized by being provided with at least one membership function circuit which provides output of signals which represent membership functions in response to input signals, and a plurality of switches connected to its output side in parallel to each other, and also being provided with a plurality of implication circuits, one for each implication, and weighting circuits which apply weighting to each of the switches of the implication circuits.

By means of which, a simple fuzzy processor may be realized with a structure in which the antecedent section of the implications is represented by fuzzy values, while the consequent section is represented by singleton (non-fuzzy) values. A plurality of switches connected in parallel are provided to connect the fuzzy signals of the antecedent section to the singleton signals of the consequent section, so that any switch may be selectively turned on. The singleton signal is realized by the weighting of the selected switches.

The fuzzy processor of this invention is characterized by being provided with a plurality of implication circuits provided for each implication, being provided with at least one membership function circuit which, in response to input signals, provides output of signals which represent membership functions, and a variable resistance circuit connected to the output side for providing weighting, and addition circuits which add the output signals of the implication circuits.

By means of which, a simple fuzzy processor may be realized with a structure in which the antecedent section of the implications is represented by fuzzy values, while the consequent section is represented by singleton values. Moreover, the singleton weighting can be adjusted as desired using variable resistance.

The composite device of the MAX circuit block of this invention comprises a plurality of fuzzy inference circuits which carry out the specified fuzzy inference for each implication, a MAX circuit which carries out a MAX operation on the output signals from the a plurality of fuzzy inference circuits, and a back end circuit which processes or outputs the results of the MAX operation. The various fuzzy inference circuits are each provided on a single type 1 board and the back end circuits are provided on a type 2 board. A MAX circuit comprises transistors provided on each type 1 board, on which the bases of these transistors are provided with the output of fuzzy inference circuits, and the emitters of which become the output terminals for the type 1 boards, along with current sources provided on the type 2 boards and connected to the input terminals of these type 2 boards, and a wired OR comprising connections by means of a connector from the output terminals of the type 1 boards to the respective input terminals of the type 2 boards.

Another object of this invention is to provide hardware systems suited for the processing of fuzzy information, and more particularly grade-controllable membership function circuits and grade-controllable membership function generator circuits useful in the systems referred to as fuzzy controllers.

A still further object of this invention is to provide fuzzy computers and fuzzy controllers which are built using said grade-controllable membership function circuits and gradecontrollable membership function generator circuits.

A grade-controllable membership function circuit of the invention is characterized by being provided with a membership function circuit which, in response to an input signal, provides as output a level signal which represents a previously-determined membership function, the peak level section of which is determined by a label signal, and a grade-control circuit which controls the level of the output signal from this membership function circuit in response to a grade-control signal input.

By means of the invention, the grade of the membership function provided as output from the membership function circuit can be varied in response to a grade-control signal.

A grade-controllable membership function generator circuit of the invention is characterized by being provided with a signal distribution generation circuit which generates a signal level distribution which represents a membership function by means of signal levels distributed over a plurality of signal lines, and a switch array which converts said signal level distribution into specified positions on a plurality of output signal lines in response to a given level signal, while said signal distribution generation circuits are provided with circuit sections which generate a signal of a plurality of levels by dividing the level of the given control signal.

By means of this invention, the grade of the membership function generated by the membership function generation circuit can be varied in response to a control signal.

Furthermore, according to the invention, since the grade of the membership function can be adjusted manually or in response to the results of learning, the membership function can be weighted depending on the importance of the implication rule.

A sweep-type fuzzy controller of the invention is characterized by comprising an initial-rank circuit which, in response to one or more given inputs, provides as output a signal which represents the results of specified operations on a signal which represents a membership function value, or a signal which represents a plurality of membership function values, a sweep signal generator circuit which generates a sweep signal of a fixed period, and a grade-controllable membership function circuit which, synchronized with the input sweep signal, provides as output a signal which represents a specified membership function, and being provided with said output signal from said initial-rank circuit as a control signal, controls the level of the signal representing the membership function in response to this control signal, thus carrying out fuzzy inferences based on algebraic product rules.

By means of the invention, a fuzzy controller which carries out inferences based on algebraic product rules can be realized with an extremely simple structure.

A parallel-type fuzzy controller of the invention is characterized by comprising an initial-rank circuit which, in response to one or more inputs, provides as output a signal which represents the results of specified operations on a signal which represents a membership function value, or a signal which represents a plurality of membership function values, and a grade-controllable membership function generator circuit which generates and provides output signal levels which represent a membership function distributed over a plurality of signal lines, and being provided with said output signal from said initialrank circuit as a control signal, controls the level of the signal representing the membership function in response to this control signal, thus carrying out fuzzy inferences based on algebraic product rules.

By means of this invention, a fuzzy controller which carries out inference operations according to algebraic product rules can be realized with an extremely simple structure.

A parallel-type fuzzy controller of the invention is characterized by being provided with at least one grade-controllable membership function circuit which, in response to a given input signal, provides as output a signal representing a membership function, and controls the level of the output signal representing the membership function in response to a given control signal, a grade-controllable membership function generator circuit which generates and provides as output signal levels which represent a membership function distributed over a plurality of signal lines, and being provided with the same control signal as said grade-controllable membership function circuit, controls the level of the signal level distribution to be generated in response to this control signal, and a fuzzy inference synthesis circuit which executes specified fuzzy inference operations on the output signals from said gradecontrollable membership function circuits and grade-controllable membership function generator circuit.

By means of this invention, a fuzzy controller which carries out inference operations while controlling the grade of the antecedent and consequent sections, and is particularly useful in fuzzy systems which have learning functions can be realized.

A parallel-type fuzzy computer of the invention is characterized by being provided with at least three gradecontrollable membership function generator circuits each which generates and provides as output signal levels which represent different membership functions distributed over a plurality of signal lines, and being provided with the same control signal, controls the level of signal level distribution in response to this control signal, and a fuzzy inference engine which executes specified fuzzy inference operations on the output signals from said at least three grade-controllable membership function generator circuits.

By means of this invention, a fuzzy computer which is able to change or adjust the grade of membership functions in the antecedent and consequent sections, and is particularly useful in fuzzy systems which have learning functions can be realized.

A sweep-type fuzzy controller of the invention is characterized by being provided with at least one of a type 1 grade-controllable membership function circuit which, in response to a given input signal, provides as output a signal representing a membership function, and each controls the level of its output signal representing the membership function in response to a given control signal, a sweep signal generator circuit which generates a sweep signal of a fixed period, and a type 2 gradecontrollable membership function circuit which, synchronized with the sweep signal, provides as output a signal representing a membership function on the time axis, and being provided the same control signal given to said type 1 grade-controllable membership function circuit, controls the level of its output signal in response to this control signal, and a fuzzy inference synthesis circuit which executes specified fuzzy inference operations on the output signals from said type 1 grade-controllable membership function circuits and type 2 grade-controllable membership function circuit.

By means of this invention, a fuzzy controller is able to change the grade of membership functions in the antecedent and consequent sections, and would be suited for fuzzy systems which have learning functions.

A sweep-type fuzzy computer of the invention is characterized by being provided with a sweep signal generator circuit which generates a sweep signal of a fixed period, at least three grade-controllable membership function circuits, each of which, synchronized with the sweep signal, provides as output a signal representing a different membership function on the time axis, and being provided the same control signal, controls the level of its output signal in response to this control signal, and a fuzzy inference synthesis circuit which executes specified fuzzy inference operations on the output signals from said gradecontrollable membership function circuits.

By means of this invention, a fuzzy computer can be realized in such a way that the grade of membership functions in the antecedent and consequent sections can be changed. This fuzzy computer is suited to the creation of fuzzy systems which have learning functions.

A still further object of this invention is to provide a circuit which can determine the center of gravity of fuzzy information using neither multiplication circuits nor division circuits.

A center of gravity determination circuit of the invention is characterized by providing a type 1 weighted addition circuit which multiplies each electrical signal representing fuzzy information distributed over a plurality of lines by a value which depends on the number of that line and then adds the results, a type 2 simple addition circuit which adds said electrical signals distributed over a plurality of lines, and a control means which controls the circuit sections related to said electrical signals so that the output signal of the type 2 simple addition circuit represents a value which is equivalent to 1.

By means of this invention, since the related electrical circuits are controlled so that the output signal of the type 2 simple addition circuit represents a value which is equivalent to 1, the output of the type 1 weighted addition circuit, which multiplies each electrical signal in the distribution over a plurality of lines by a value which depends on the number of that line and adds the results, represents the center of gravity. Since the type 1 addition circuit's output signal which serves as the divisor (denominator) in the center-of-gravity operation is always 1, no division circuits are required. Since multiplication and addition are carried out by the type 1 weighted addition circuit, no addittioncircuits in the normal sense are required. In this manner, the center of gravity of fuzzy information can be determined with a simple structure to obtain a signal which represents this determined center of gravity.

A center of gravity determination circuit of the invention is further characterized by executing specified fuzzy inferences based on output signals from membership circuits (includes membership function circuits and membership function generator circuits) which provide output signals representing membership functions, and is suitable as a fuzzy processing device (includes a fuzzy computer or fuzzy controller) which provides output signals representing the inference results distributed over a plurality of lines, and as such it is provided, for each of the output signals representing the inference results distributed over a plurality of lines, with a type 1 weighted addition circuit which multiplies each electrical signal representing the inference results distributed over a plurality of lines by a value which depends on the number of that line and adds the results, a type 2 simple addition circuit which adds said signals representing the inference results distributed over a plurality of lines, and a grade control means which controls the level of the output signals from said membership circuits so that the output signal of the type 2 simple addition circuit represents a value which is equivalent to 1.

In the invention, since the grade of the membership function in the membership circuits within the fuzzy processing device is adjusted so that the output signal of the type 2 simple addition circuit represents a value which is equivalent to 1, determination of the center of gravity of fuzzy inference results may be accomplished without multiplication or division circuits.

FIGS. 1A, 1B and 1C are graphs illustrating membership functions where FIG. 1A shows the typical form, FIG. 1B shows triangular and truncated triangle-shaped membership functions while FIG. 1C shows the Z and S functions.

FIG. 2 illustrates a membership function represented by a distribution of voltages on a plurality of signal lines.

FIG. 3 is a waveform chart illustrating a sawtooth sweep signal and a membership function signal waveform.

FIG. 4 is a block diagram illustrating the concept of a basic parallel-type fuzzy computer.

FIG. 5 is a block diagram illustrating the concept of a parallel-type fuzzy computer which includes a plurality of implications.

FIG. 6 is a block diagram illustrating the structure of a basic parallel-type fuzzy inference engine.

FIG. 7 is a block diagram illustrating the concept of a basic sweep-type fuzzy computer.

FIG. 8 is a block diagram illustrating the concept of a parallel-type fuzzy computer which is suited to fuzzy inferences using a plurality of implications.

FIG. 9 is an explanatory diagram graphically illustrating the process of making fuzzy inferences.

FIG. 10 illustrates the concept of an expanded parallel-type fuzzy inference engine, while FIG. 11 is a block diagram illustrating its structure.

FIGS. 12 and 13 are explanatory diagrams of the process of making inferences in a parallel-type fuzzy controller.

FIG. 14 is a block diagram illustrating the structure of a parallel-type fuzzy controller.

FIG. 15/is a block diagram illustrating the structure of a sweep-type fuzzy controller.

FIG. 16 is a block diagram illustrating the structure of another example of a sweep-type fuzzy controller.

FIG. 17 is a block diagram illustrating an example of a fuzzy computer which employs a center of gravity determination circuit.

FIG. 18 is a block diagram illustrating an example of a fuzzy controller which employs a center of gravity determination circuit.

FIG. 19 is a diagram used to explain the process of making inferences when the consequent section of the implication is represented as a singleton.

FIG. 20 is a circuit diagram of a weighted addition circuit.

FIG. 21 is a circuit diagram of a simple addition circuit.

FIG. 22 is a graph showing a membership function and its labels and singleton forms.

FIG. 23 is a circuit diagram of a MIN circuit.

FIG. 24 is a circuit diagram of a MAX circuit.

FIG. 25, consisting of FIGS. 25A and 25B, is a circuit diagram illustrating the structure of a fuzzy processor.

FIG. 26, consisting of FIGS. 26A and 26B, is a circuit diagram illustrating the structure of a fuzzy processor rule board.

FIG. 27 is a circuit diagram used to explain a membership function circuit, illustrating part of the circuit cut away, while FIG. 28 (A) through (E) are graphs illustrating the signals of the circuit.

FIGS. 29A and 29B are each block diagrams illustrating examples of the structure of a fuzzy controller which carries out inferences based on algebraic product operations.

FIG. 30 is a circuit diagram illustrating the structure of a center of gravity determination circuit.

FIG. 31 is a waveform diagram illustrating the operation of the circuits shown in FIG. 29 and FIG. 30.

FIG. 32 is a block diagram illustrating a rule board for a parallel-type fuzzy controller which carries out weighting for each rule board.

FIG. 33 is a block diagram illustrating the basic structure of a grade-controllable membership function circuit.

FIG. 34 is a circuit diagram illustrating a gradecontrollable membership function generator circuit realized through the use of a switch matrix, while FIG. 35 illustrates the actual structure of the symbols used in FIG. 34.

FIG. 36, consisting of FIGS. 36A, 36B and 36C, is a circuit diagram illustrating a grade-controllable membership function generator circuit realized through the use of a pass transistor array. FIG. 37 illustrates the actual structure of the symbols used in FIG. 36. FIG. 38 is a table illustrating the operation of the decoder of FIG. 36. FIG. 39 is a circuit diagram illustrating the actual structure of the decoder of FIG. 36. FIG. 40 is a circuit diagram illustrating the NAND gate used in the circuits of FIG. 36.

FIG. 41 is a circuit diagram illustrating a voltage distribution generator circuit which can select the shape of the membership function.

FIG. 42 is a block diagram illustrating the progression of a grade-controllable membership function generator circuit.

FIGS. 43 through 4 are circuit diagrams illustrating examples of variations on the fuzzy processor.

FIG. 47, consisting of FIGS. 47A and 47B, is a block diagram illustrating a concrete example of the structure of a grade-controllable membership function circuit.

FIG. 48 is a circuit diagram used to explain a membership function circuit, illustrating part of the circuit in detail, while FIG. 49 (A) through (E) are graphs illustrating the signals of the circuit.

FIG. 50 is a block diagram of a center of gravity determination circuit illustrating Preferred Embodiment 1.

FIG. 51 is a graph used to explain fuzzy information and its center of gravity.

FIG. 52 is a circuit diagram illustrating an example of a weighted addition circuit.

FIG. 53 is a circuit diagram illustrating an example of a variation.

Human rules of experience, simplified to the utmost degree, can be expressed by the proposition

If x is A, then y is B. where "If x is A," is called the antecedent and "then y is B." is called the consequent. If A and B are in the form of vague linguistic information such as "a tall person," "an old person" or "a small positive number," they can be characterized as a membership function. Specifically, A and B are fuzzy sets (in the following explanation of specific circuits, A and B, etc., will indicate voltage signals which represent membership functions).

The above proposition can be represented simply by the notation

Humans often make inferences which include fuzzy representations of the antecedent and consequent. This type of inference cannot be satisfactorily executed using classical Boolean logic. Consider the following inference format. ##STR1##

This inference format, specifically when implications are present, in which the conclusion is inferred from the given premise is called a generalized modus ponens.

Many implication rules may also be present, as in the following: ##STR2## where the many implications are linked by a logical "else" or a logical "and."

Now consider the concept of the "fuzzy relation from A to B," as represented by R.sub.AB (hereafter abbreviated merely as R).

Generally, when

the fuzzy relation from A to B is represented by ##EQU1## where

The r operator which represents the fuzzy relation will be described hereafter.

Considering A and B to be membership functions, the above expression is equivalent to sampling a membership function and describing it with vectors.

When one premise (x =A') is given for each implication rule (x=A.fwdarw.y=B), from which a conclusion (y=B') is inferred, the "compositional rule of inference" can is represented by the following using the fuzzy relationship R. ##EQU2##

Various operations have been proposed to represent the fuzzy relationship r. For details, refer to Masaharu Mizumoto and Hans-Jurgen Zimmermann, "Comparison of Fuzzy Reasoning Methods," Fuzzy Sets and Systems Vol.8, No.3, pp.253-283 (1982).

Representative fuzzy relations already proposed include the following: ##EQU3##

The MIN operation rule above is the most well known, and its validity has been proved in industrial applications, so in the specific examples of circuits described hereafter, the MIN operation rule is employed. However, it need not be said that many other operation rules can be employed.

Various operations have also been proposed for the * operations (specifically the b and A operations) in the above expression. For example, MIN/MAX operations, algebraic product/MAX operations and others are used. In the specific examples of circuits described hereafter, the most commonly used MIN/MAX operations will be used as the * operations. That is to say, the MAX operation will be employed as the b operation while the MIN operation will be employed as the A operation.

Therefore, using MIN/MAX operations as the * operations and the MIN operation rule as the fuzzy relationship, the conclusion b.sub.j ' of the compositional rule of inference is represented as follows: ##EQU4##

From the above expression, it is obvious that a fuzzy inference engine or fuzzy inference synthesis circuit would be comprised mainly of MIN circuits or MAX circuits.

Before describing the configuration of fuzzy computers and fuzzy controllers, here is a brief explanation of membership functions.

Membership functions are generally represented by a curved line as in the example shown in FIG. 1A. Yet whether it is represented by a curved line or not is not essential to the membership function. A more important characteristic of a membership function is that it may assume a continuous range of values from 0 to 1.

On the other hand, from the standpoint of circuit design, membership functions are simpler to handle if represented by a polygonal line made up of straight line segments as shown by MF.sub.1 and MF.sub.2 in FIG. 1B, so that the membership function can be characterized with a small number of parameters, simplifying design. Yet the membership function does not lose the above characteristics even when represented by a polygonal line.

Consider the triangular membership function MF.sub.1 represented by the solid line on FIG. 1B, and the truncated triangle-shaped membership function MFz represented by the dashed line as the basic shapes. Assuming that triangular membership function MF.sub.1 is a function .mu.(x)=peak value P (the peak value is not necessarily equal to 1) the function can be characterized by the value x.sub.L (called the label) of the variable x and the slope of the curve.

Note that the variable x of the membership function .mu.(x) and the variable y of the function .mu.(y) which will appear later have no particular relationship to the same symbols x and y used in the above inference format. This notation shall be followed in this specification.

As illustrated in FIG. 1C, other membership functions include the function indicated by MF.sub.3, a function .mu.(x) which assumes the value 1 when the variable x is small, and at a certain value x.sub.L of the variable x begin to drop off to 0 at a constant slope (this is called the Z function) and the function MF.sub.4 (called the S function) which varies in the opposite manner as the Z function. In addition, many other types of membership functions are conceivable.

The membership functions described above are given concrete expression in various forms. One of these is illustrated in FIG. 2, in which a membership function is represented by an electrical signal (which may be voltage or current but only voltage signals are considered here) distributed among a plurality (25 for example) of signal lines l. The variable of the membership function .mu.(x) assumes discrete values, and these variables are allocated to the various signal lines. The signal lines corresponding to the allocated variables are assigned numbers (from 1-25 in FIG. 2). The plurality of signal lines comprises a type of bus. The label x.sub.L is represented by the number of the signal line in which the peak voltage appears.

Another form of expression is achieved by representing the variable x of a membership function .mu.(x) on the time axis. Specifically, the variable becomes time t (for convenience in the explanation, this time variable t is differentiated from the overall time T). A sweep signal is required to generate this type of membership function .mu.(x). The sweep signal can take on various waveforms (e.g., a sawtooth waveform, triangular wave, sine wave, or a full wave rectification of a sine wave), but this description here will use the sawtooth waveform shown in FIG. 3 as an example.

In FIG. 3, the sawtooth sweep signal SW varies linearly from -E to +E with a fixed period .tau., and then returns to -E after a short period (the flyback time). The point in time at which the sweep signal SW crosses zero corresponds to, for example, x=0 of the membership function .mu.(x). The label x.sub.L is represented by the voltage V.sub.L of the sweep signal SW at the point in time corresponding to the value x.sub.L.

FIG. 4 illustrates the concept of a parallel type fuzzy computer which carries out operations using a membership function distributed over the bus lines shown in FIG. 2; this fuzzy computer is suited to the case of when one implication is present. The fuzzy computer comprises three membership function generator circuits 11, 12, and 13 which respectively provide as output the membership functions A, A' and B distributed over the bus lines shown in FIG. 2, and a fuzzy inference engine 14 which is given the output signals from these circuits 11, 12 and 13 and carries out the modus ponens fuzzy inference operations described above (specifically, equations (3-1) and (3-2)) and provides as output the inference result B'. The membership function generator circuits 11, 12, and 13 are given the labels LA, LA' and LB which define the membership functions they should generate as output. If the fuzzy computer is required to produce definitive results (non-fuzzy output), a defuzzifier 15 is connected to the back end of the fuzzy inference engine 14.

FIG. 6 illustrates an example of the structure of the fuzzy inference engine 14 described above. This engine carries out the operation represented by equation (3-2). Voltages representing the membership functions A and A' each distributed over m signal lines are given to a C-MIN circuit (correspondence MIN circuit) 21 which carries out the MIN operation a.sub.j b.sub.i ' (1.ltoreq.i.ltoreq.m). The m output voltages from C-MIN circuit 21 are input for an E-MAX circuit (ensemble MAX circuit) 22. The output of this E-MAX circuit 22 is represents ##EQU5## The E-MAX circuit 22 carries out ensemble MAX operations on the m input signals. The output of the E-MAX circuit 22 is provided to a truncation circuit 23 as truncating input a. In addition, the truncation circuit 23 accepts as input a voltage distribution (b.sub.j, where 1.ltoreq.j.ltoreq.n) representing the fuzzy membership function B distributed among n signal lines. The truncation circuit 23 is a circuit which makes common all input other than that to the EMAX circuit 22. As a result, the operation of equation (3-2) is ultimately carried out by the truncation circuit 23, so that the conclusion B' of the fuzzy inference can be obtained as a set of analog voltages b.sub.j ' distributed over n output lines.

FIG. 5 illustrates the concept of a parallel type fuzzy computer which is effective when r implications are present. A total of r sets of three membership function generator circuits 11, 12, and 13 are provided. The labels LA and LB given to the membership function generator circuits have subscripts from 1 to r. There is no need to provide each of these sets with a separate membership function generator circuit 12, but rather one circuit 12 can be shared among all of the sets. Linkage between implications (else or and) is realized by a MAX circuit 16. Specifically, the outputs of all of the fuzzy inference engines 14 are provided to the MAX circuit 16, and the ultimate inference result B' is obtained from the MAX circuit 16. Naturally, linkage with an operation other than MAX can also be executed.

FIG. 7 illustrates the concept of a sweep type fuzzy computer which carries out operations using a membership function represented by the time axis shown in FIG. 3; this fuzzy computer is for the case of when one implication is present. This sweep type fuzzy computer comprises three membership function circuits 31, 32, and 33 which respectively provide as output the membership functions A, A' and B represented on the time axis, a fuzzy inference synthesis circuit 34 which is given the output signals from these circuits 31, 32 and 33 and carries out the modus ponens fuzzy inference operations described above and provides as output the inference result B', and a timing circuit 35 which not only provides a sweep signal SW as an input signal to the membership function circuits 31, 32, and 33 but also provides to the fuzzy inference synthesis circuit 34 a timing signal synchronized to this sweep signal. Not only the membership functions A, A' and B, but naturally the inference results B' are also represented as voltage appearing on the time axis. The membership function circuits 31, 32, and 33 are provided with the labels (label voltages) LA, LA' and LB respectively which define the membership functions to be provided as output by each. If the fuzzy computer is required to produce definitive results (non-fuzzy output), a defuzzifier 36 is connected to the back end of the fuzzy inference synthesis circuit 34. A constant (at least constant for one period .tau. of the sweep signal) voltage signal is obtained from the defuzzifier 36.

FIG. 8 illustrates the concept of a sweep type fuzzy computer which is effective when r implications are present. Its configuration is readily understood by comparing the parallel type fuzzy computer which is effective when r implications are present shown in FIG. 5 and the basic form of the sweep type fuzzy computer shown in FIG. 7 described above.

In order to assist understanding, as an example of the fuzzy inferences made by the fuzzy inference engine 14 or fuzzy inference synthesis circuit 34 described above, FIG. 9 graphically represents an inference made according to equation (3-2). This assumes a plurality (r) of implications. Furthermore, a triangular membership function is represented. In equation (3-2), the membership functions A, A', B and such are represented using elements a.sub.i, a.sub.i ', b.sub.j of fuzzy sets, but in FIG. 9, the functions are represented by the functions .mu.(x) or .mu.(y) (or .mu.(t)) of the variables x or y (or time t) on the horizontal axis.

Referring to the upper row left graph of FIG. 9, the results A.sub.1 A' of taking the MIN operation of the membership functions A.sub.1 and A' are shown as the region indicated with hatching. The MIN operation results' maximum value a maxl (the truncating input a shown on FIG. 6) is found. The upper row middle graph shows the results of a MIN operation on the membership function B.sub.1 and the maximum value a maxl found above as the region S.sub.1 indicated with hatching. The hatched portion S.sub.1 is the results of one inference regarding one implication and would be the output from one fuzzy inference engine 14 or fuzzy inference synthesis circuit 34.

Inferences regarding the other implications are made using the same technique, and these inference results are represented by S.sub.2 and S.sub.r.

The results B' of taking a MAX operation (with circuit 16 or circuit 37) of the inference results are represented on the right of FIG. 9. As to the technique for defuzzifying the inference results, many have been proposed and one of them is the center of gravity method. According to this method, the center of gravity y.sub.w is found by the expression

Specifically, this expression finds the y coordinate (time t) at which the area indicated with hatching is evenly divided in half, to the left and right of the coordinate. The coordinate y.sub.w thus found becomes the output of defuzzifier 15 or 36 as a definitive value.

The fuzzy inference engines or fuzzy inference synthesis circuits described above both make inferences when only one fuzzy proposition is present in the antecedent of the implication, but as shown in the following, there are cases which require inferences which include two fuzzy propositions present in the antecedent of the implication. These are referred to as expanded fuzzy inferences. The antecedent of the implication is linked by a logical and/or. Either "and" or "or" must be selected.

Implication: If x is A and/or y is B, then z is C

This can be symbolically represented as follows:

Expanded fuzzy inferences in parallel type fuzzy computers are made using expanded fuzzy inference engines. FIG. 10 illustrates the concept of the expanded fuzzy inference engine. Input is the membership functions A, B, C, A' and B', along with the linkage selection c used to select the and/or linkage. Output is the membership function C' which represents the conclusion. The membership functions A and A' are represented by voltage distributed over m signal lines, B and B' by voltage distributed over m' signal lines, and C by voltage distributed over n signal lines, respectively.

FIG. 11 illustrates the structure of such an expanded inference engine, obtained by slightly modifying the structure of the basic inference engine illustrated in FIG. 6. A C-MIN operation is carried out (with the C-MIN circuit 21A) on the membership functions A and A', and an E-MAX operation is carried out (with the E-MAX circuit 22A) on the m voltages which represent the results. Similarly, C-MIN and E-MAX operations are carried out (with the C-MIN circuit 21B and E-MAX circuit 22B) on the membership functions B and B'. The linkage "and" is realized in this preferred embodiment by a MIN operation, while the "or" is done with a MAX operation. So that the linkage operation and selection may be done readily, a controlled MINMAX circuit 24 is provided. The controlled MIN-MAX circuit 24 can be switched between its MIN operation function and MAX operation function depending on the level (H or L) of the linkage selection input signal c. The results of two E-MAX operations are provided as input to the controlled MIN-MAX circuit 24. The linkage selection input signal c is also provided to the controlled MIN-MAX circuit 24 as control input used to select "and" or "or." The membership function C is provided to the truncation circuit 23, and the output a from the controlled MINMAX circuit 24 is provided as its truncating signal. A voltage distribution of the fuzzy membership function representing the conclusion C' is obtained from the truncation circuit 23.

Next the concept of the fuzzy controller will be described.

In general, the input to a controller is controlled variables from the controlled system and its output is manipulated variables provided to the controlled system to elicit the desired control. Both the controlled variables and manipulated variables are definitive values. A fuzzy controller must accept definitive values as input, make fuzzy inferences and provide definitive values as output. Taking as an example the case in which one fuzzy proposition is present in the antecedent of the implication, the fuzzy computer described above is provided input of fuzzy sets or the membership function A', and provides as output fuzzy sets or a membership function B' (or a definitive value as the case may be).

The fuzzy inferences made by a fuzzy controller in the case of one implication (where there is also one fuzzy proposition in the antecedent), in contrast to FIG. 9, are graphically represented as illustrated in FIG. 12. With respect to an implication which includes the membership functions A and B, the results of fuzzy inference when given the definitive value x.sub.A are shown by the hatched region B'. By defuzzifying these inference results, the definitive inference result B.sub.W ' is obtained. FIG. 13 illustrates the case of two fuzzy propositions in the antecedent of the implication. When the two membership functions A and B in the antecedent of the implication are each provided with definitive values x.sub.A and y.sub.B respectively, the function values a.sub.A and a.sub.B are operated on with a MIN or MAX (corresponding to the linkages "and" or "or"), and then the result a.sub.M of this operation and the membership function C are operated on with a MIN operation, the results of which become the fuzzy inference results (shown by the hatched region C'). A definitive inference result C.sub.W ' is obtained by defuzzifying the fuzzy inference results C'.

FIG. 14 illustrates an example of the configuration of parallel type fuzzy controller which uses fuzzy membership functions distributed over bus lines, being suited to making fuzzy inferences in which two implications are present while each implication has two fuzzy propositions in their antecedents. This fuzzy controller will be described in contrast to FIG. 5 and its fuzzy inference engine shown in FIG. 11.

The implication is represented as follows:

The fuzzy inference engine 14 is interchangeable with the fuzzy inference synthesis circuit 14a. Since the two inputs are given as the definitive values x.sub.A and x.sub.B, the circuits 11, 12 and such which generate the membership function distributed over the bus lines are not necessary, so in their place, two membership function circuits 31a and 31b are provided. A fuzzy inference synthesis circuit 14a, two membership function circuits 31a and 31b and the like are provided for each implication, while the labels LA and LB of the membership function circuits 31a and 31b are given subscripts corresponding to the implication number. Implication 1 will be described below as a representative example.

The membership function circuits 31a and 31b provide as output the membership function values and .mu..sub.A1 (x.sub.A) and .mu..sub.B1 (Y.sub.B) corresponding to the input variables x.sub.A and x.sub.B. The output of these circuits 31a and 31b is provided to the MIN or MAX circuit 24a. This MIN or MAX circuit 24a corresponds to the controlled MIN-MAX circuit 24, and can be replaced with this circuit 24. The output of circuit 24a becomes the truncating input a.sub.M1. The output of membership function generator circuit 13 which generates membership function C.sub.1 as voltage distribution appearing on the bus line (plurality of signal lines) is provided to the truncation circuit 23 where the MIN operation of it and a.sub.M1 is taken, and the results of this MIN operation becomes C.sub.1 '.

For the remaining (r-1) implications, C.sub.2 ' through C.sub.r ' are obtained in similar fashion, and the results of a MAX operation on C.sub.2 ' through C.sub.r ' (done by MAX circuit 16) becomes the fuzzy inference result C' from which the defuzzified result C.sub.w ' is obtained.

FIG. 15 illustrates the configuration of a sweep type fuzzy controller for when a plurality of implications are present (but there is one fuzzy proposition in the antecedent of the implication). In contrast to FIG. 8, since input is provided as the definitive value x.sub.A, the circuits 32 (MFC2 in the computer) which generate the membership function A' are not needed. Circuit 31 of membership function A1 is provided with x.sub.A as input. The output of this circuit 31 is provided to the MIN circuit 38 to which the output from circuit 33 is also provided. A sweep signal is provided as input to circuit 33. The output Bl' of the MIN circuit 38 is provided to the MAX circuit 37 as input. Since each of the above circuits are provided for each of a plurality of implications, all of their MIN circuit 38 outputs B.sub.1 ' through B.sub.r ' are provided as input to the MAX circuit 37. The output B' of the MAX circuit 37 determines the definitive value output from the defuzzifier 36.

In the event that two fuzzy propositions are present in the antecedent of the implication, as shown in FIG. 16, two membership function circuits 31a and 31b are provided and definitive input values x.sub.A and x.sub.b are provided to these circuits 31a and 31b. The output of these circuits 31a and 31b is provided to the MIN or MAX circuit 24a. A MIN operation is carried out on the output of this circuit 24a and the membership function C which is the output of a membership function circuit 33c provided with input of a sweep signal, the results of which, C', becomes output from the MIN circuit 38. Since this inference result C' is a fuzzy function, its definite value is determined by a defuzzifier.

Naturally, in the event that three or more propositions are present in the antecedent of the implication, a fuzzy controller (regardless of whether parallel type or sweep type) to carry out such processing can be constructed as an extension of the above thinking.

FIG. 17 illustrates an example of a center of gravity determination circuit of the invention employed in the fuzzy computer shown in FIG. 4. Instead of the membership function generator circuits 11, 12, and 13, grade-controllable membership function generator circuits (GC-MFG) 11GC, 12GC and 13GC are prepared. In addition, as a concrete example of defuzzifier 5, a center of gravity determination circuit comprising a weighted addition circuit 2 and simple addition circuit 3 is prepared. While its specific configuration will be described later, the GC-MFG changes the voltage (grade) of the voltage distribution it generates to represent a membership function depending on the control voltage V.sub.c provided. This control voltage V.sub.c is generated by the voltage regulator circuit 4. The output of the control voltage V.sub.c from the voltage regulator circuit 4 provided to the GC-MFG circuits 11GC, 12GC and 13GC is varied so that the output of the simple addition circuit 3 is always 1 (specifically, so that the denominator of equation (12) described hereafter, is always 1). Thus a definitive value (defuzzified output) representing the center of gravity of the inference results is obtained from the weighted addition circuit 2.

This thinking can naturally be applied to the fuzzy computers illustrated in FIGS. 5, 10 and 11.

FIG. 18 illustrates an example of a center of gravity determination circuit of the invention employed in the fuzzy controller illustrated in FIG. 14. Here the MAX circuit 16 is omitted, and only the circuits which process one implication rule are diagrammed, but naturally this can be applied also to fuzzy controllers which include the MAX circuit 16 for a plurality of implications. A grade control circuit 51 is provided to control the peak value (grade) of the membership function circuits 31a and 31b. The output control voltage V.sub.c of a voltage regulator circuit 4 is provided to this grade control circuit 51 and GCMFG 13GC, thus controlling the grade of the membership functions of the membership function circuits 31a and 31b and the GC-MFG 13GC so that the output of the simple addition circuit 3 is always 1. The combination of the grade control circuit 51 and membership function circuit 31a or 31b is called a gradecontrollable membership function circuit (GC-MFC).

Consider the case of a plurality (r) of implications with two fuzzy propositions, in reference to FIG. 19. Looking at the first implication, when definitive-valued inputs x.sub.A and y.sub.B are provided to the membership functions A1 and B1 respectively, the function values a.sub.A1 and a.sub.B1 are obtained. The result of a MIN (or MAX) operation on these function values is a.sub.M1. For the other implications, definitive-valued inputs x.sub.A and y.sub.B are provided and the results a.sub.Mi (2.ltoreq.i.ltoreq.r) are obtained.

Each of the membership functions C.sub.i (1.ltoreq.i.ltoreq.r) in the consequent of the implication can be represented by one function C.sub.si (1.ltoreq.i.ltoreq.r) extended to the peak on its label position Z.sub.Li (1.ltoreq.i.ltoreq.r). This function is known as a singleton and is a nonfuzzy quantity. The result of a MIN operation (equivalent to the truncating described above, but as described hereafter, the MIN operation is unnecessary) on the above MIN operation results and the singletons C.sub.si are represented by thick arrows C.sub.si ' (1.ltoreq.i.ltoreq.r).

In order to simplify symbols in the following explanation, Z.sub.Li will be replaced with Z.sub.i (1.ltoreq.i.ltoreq.r), and C.sub.si ' with V.sub.zi.

When the linkage between a plurality of implications is the MAX operation, the final fuzzy implication results are illustrated in the form of the bar graph on the right-hand side of FIG. 17. Since the implication results are defuzzified in this way, the center of gravity technique described above can be used here. The center of gravity C.sub.SW ' (set equal to Z.sub.W) is found with the following equation. ##EQU6##

The numerator of equation (4) can be calculated by a weighted addition circuit such as that illustrated in FIG. 20, while the denominator can be calculated by a simple addition circuit such as that illustrated in FIG. 21.

In FIG. 20, the weighted addition circuit comprises an operational amplifier 41, input resistors R.sub.1, . . . , R.sub.r connected in parallel and a feedback resistor R.sub.f. Each of the input resistors R.sub.1 through R.sub.r, is provided at one end with a voltage V.sub.z1 through V.sub.zr. Thus, the output V.sub.ol of this weighted addition circuit is found by the following equation: ##EQU7## And by setting

equation (5) becomes the denominator of equation (4) (with the sign reversed).

From equation (6), it can be seen that the label of the singleton C.sub.si which represents the membership C.sub.i takes shape as the input resistors R.sub.i and the feedback resistor R.sub.f.

As shown in FIG. 22, when considering the membership functions or singletons represented by the seven labels from NL (negative large) through PL (positive large), these labels are defined by the input resistors R.sub.i (1.ltoreq.i.ltoreq.r) and the feedback resistor R.sub.f. In FIG. 22, the N in NL, NM, and NS stands for negative, the P in PS, PM and PL for positive, while ZR is zero.

The simple addition circuit in FIG. 21 comprises an operational amplifier 45, input resistors R.sub.o connected in parallel and a feedback resistor R.sub.o with the same value as the input resistors (but not necessarily the same value). Each of the input resistors is provided at one end with a voltage V.sub.z1 through V.sub.zr, Thus the output V.sub.o2 of this simple addition circuit is represented by the following equation: ##EQU8##

This represents the denominator of equation (4) (with the sign reversed).

Like the fuzzy controller, the fuzzy processor graphically illustrated in FIG. 19 is characterized by being provided with definitive inputs x.sub.A and x.sub.B and making fuzzy inferences based on specified implications and then providing a definitive value (center of gravity Z.sub.w) as output. This fuzzy processor is also characterized by its fuzzy inferences in which, while fuzzy functions are used in the antecedent of the implications, the consequents are represented by non-fuzzy quantities (singletons). Furthermore, the value of the MIN operation results a.sub.m1 (1.ltoreq.i.ltoreq.r) for each implication represents the results of that implication operation so the truncation circuits in the fuzzy computers or fuzzy controllers described above are unnecessary. By carrying out weighted addition (the weighting represents the level of the singleton of the consequent as described above) of the operation results from a plurality of implications, the final output (the center of gravity Z.sub.w) is obtained. Naturally, while the simple addition described above is required, the division of equation (4) can be omitted as described hereafter. While examples of specific configurations of fuzzy processors which have these several characteristics will be described later, before that the MIN and MAX circuits which are the basic operation circuits will be described.

FIG. 23 illustrates an example of an n-input, 1-output MIN circuit comprised of bipolar transistors. If the input voltages are x.sub.1, x.sub.2, . . . , x.sub.n and the output voltage is z, this circuit carries out the operation ##EQU9## This is to say, an output voltage equal to the smallest input voltage is generated.

This MIN circuit is comprises a comparator and a compensator. The comparator comprises n different PNP transistors Q.sub.11, Q.sub.12, Q.sub.13, . . . , and Q.sub.1n, each with emitters linked to each other, and a current source CS.sub.1 of current I.sub.1 which drives these transistors. The input voltages x.sub.l through x.sub.n are provided to the bases of each of the transistors Q.sub.11, through Q.sub.1n. The transistor with the lowest input voltage (V.sub.min) of any of the transistors Q.sub.11, through Q.sub.1n will enter the conducting state and other transistors will enter the cut-off state. Therefore, a voltage of the input voltage V.sub.min added to the emitter/base voltage V.sub.Eb, specifically ##EQU10## would appear at the emitter. If two input voltages are equal and are lower than the other input voltages, a current of I.sub.1 /2 would flow in each of these two transistors with the same input voltage, giving the same results. This also holds for cases in which three or more input voltages are equal and lower than the other input voltages.

The compensator compensates for any voltage V.sub.EB which should appear as a MIN operation error in the comparator output. This compensator comprises an NPN transistor Q.sub.1 and a current source CS.sub.2 of current I.sub.2 which drives this transistor Q.sub.1. The emitter of transistor Q.sub.1 is coupled to the output terminal of this MIN circuit. As a result of subtracting the base/emitter voltage V.sub.BE of transistor Q.sub.2 from the output voltage of the comparator the output voltage z represents ##EQU11## The current of current sources CS.sub.1 and CS.sub.2 would preferably have the relationship I.sub.1 =I.sub.2.

FIG. 24 is an example of a MAX circuit. This MAX circuit also comprises a comparator and compensator. The comparator comprises NPN transistors Q.sub.21, Q.sub.22, . . . , Q.sub.2n which are base-controlled by their input voltages x.sub.1, x.sub.2, . . . , x.sub.n and have their emitters coupled to each other, and a current source CS.sub.1 which drives these transistors. Only the transistor with the highest input voltage (V.sub.max) of any of the transistors Q.sub.21, through Q.sub.2n will enter the conducting state and a voltage of V.sub.max -V.sub.EB would appear at the emitter. This error of -V.sub.EB is compensated by the compensator comprised of a PNP transistor Q.sub.2 and a current source CS.sub.2, resulting in an output voltage z of ##EQU12## being obtained at the output terminal.

Since all of the transistors in the MIN and MAX circuits described above have their emitters coupled to each other, this circuit is named an emitter-coupled fuzzy logic gate (ECFL gate).

The MIN and MAX circuits described above can be considered as a cascade connection of two emitter followers driven by current sources. Therefore, these circuits exhibit extremely high input impedance and extremely low output impedance. This fact demonstrates that these circuits will be highly resistant to external noise and cross-talk of signals, meaning that many different types of circuits can be connected to their back ends.

Since the MIN and MAX circuits described are driven by current sources, no saturation of transistors will occur. This is to say, the phenomenon of minority carriers accumulating in the base regions will not occur. Therefore, these circuits exhibit extremely high processing speeds. The response time has been experimentally demonstrated to be 10 nsec or less.

Even if one or more of the input terminals of the circuits described above would be open, this would have no effect on the I/O static characteristics of the whole circuit.

The PNP or NPN transistors in the circuits described above can be replaced by p-channel or n-channel MOSFETs, respectively. This is true for not only the MIN and MAX circuits described above, but any of the other circuits to be described hereafter.

FIG. 25 illustrates the overall structure of a fuzzy processor which carries out the operations illustrated in FIG. 19. In order to carry out fuzzy inferences including r implications, r rule boards 50 are provided, so that inferences for each implication are carried out on a different rule board. On each rule board 50 (using the notation of the first rule board as a representative), two definitive-value inputs x.sub.A and x.sub.B are provided to membership function circuits 31a and 31b, whose outputs a.sub.A1 and a.sub.B1 are provided as input to a MIN (or MAX) circuit 24a obtaining the result a.sub.M1 of the MIN operation. The structure so far is identical to that of the fuzzy controller illustrated in FIG. 14.

In a fuzzy processor, as explained above, the truncation circuit is unneeded. The output of the MIN circuit 24a is provided to a switch array 52. The switch array 52 is used to select the weighting described above. In this preferred embodiment, the seven singleton labels NL through PL illustrated in FIG. 22 are employed. Therefore, the switch array 52 is equipped with seven switches S.sub.NL through S.sub.PL, and one terminal of each of these switches is provided with the operation results a.sub.M1. The switches S.sub.ML through S.sub.PL are preferably able to be manually turned off and on, like DIP switches. The other terminals of the switches S.sub.NL through S.sub.PL are each connected the base of one of the transistors Q.sub.31 through Q.sub.37, the collectors of which are connected to the power source V.sub.cc, and the emitters of which are connected output terminals.

On each rule board 50, one of the seven switches in the switch array 52 is selectively turned on. For example if switch S.sub.NL on the first rule board is turned on, the weighting NL would be selected. If switch S.sub.PM on the second rule board is turned on, the weighting PM is set. When a certain rule board is to beee not working, all of the switches on that board are turned off.

One board (with no particular notation) contains the defuzzifier, and this board has seven input terminals corresponding to the labels NL through PL. The corresponding output terminals on each rule board is connected to these input terminals through the connector 53. For example, connected to the input terminal of label NL are all of the output terminals (emitters of the transmitters Q.sub.31) corresponding the switch S.sub.NL on each of the rule boards 50. Thus a wired OR connection of the output of all rule boards is accomplished for each label.

The seven input terminals NL through PL on the defuzzifier board are each connected a corresponding input resister R.sub.1 through R.sub.7 on the weighted addition circuit 42 and to one of the input resistors R.sub.o on the simple addition circuit 46. The weighted addition circuit 42 is identical to the one illustrated in FIG. 20, where r=7. The weighting NL through PL is carried out depending on the values of the input resistors R.sub.1 through R.sub.7. The simple addition circuit is identical to the one illustrated in FIG. 21.

The seven input terminals NL through PL on the defuzzifier board are also connected to transistors Q.sub.41 through Q.sub.47 which act as power sources. These transistors Q.sub.41 through Q.sub.47 comprise a transistor Q.sub.40 comprising a current source 49 and a multi-current mirror, so that a constant current determined by the current source 49 flows through each of these transistors Q.sub.41 through Q.sub.47 ;

The output-side transistor (one of the transistors Q.sub.31 through Q.sub.37) corresponding to the switches belonging to the same label on the switch arrays 52 on each rule board, and the corresponding transistor (the corresponding one of transistors Q.sub.41 through Q.sub.47) on the defuzzifier board acting as the current source, and the corresponding wired OR on the connector 53 between the output terminal of each rule board 50 and the input terminal of the defuzzifier board each comprise a respective MAX circuit. For example, the first rule board transistor Q .sub.31 annotated with the marking (Q.sub.21) to clarify its relationship with FIG. 24, and the r-th rule board transistor Q.sub.31 annotated with (Q.sub.2n), and the defuzzifier board transistor Q.sub.41 annotated with (CS.sub.1), along with the I/O terminals of the label NL on the connector 53 which connects them comprise one MAX circuit.

In this way, since the output terminals of a plurality of rule boards 50 and the input terminals of the defuzzifier board can be simply connected by the connector 53 to form a wired OR of corresponding elements, thus comprising a MAX circuit, the construction becomes simple. Additionally, since even if one or more rule boards 50 would be removed, a constant current will flow due to the current sources (Q.sub.41 through Q.sub.47), the input impedance on the defuzzifier board will not change, so that the correct input voltage will be added to the addition circuits 42 and 46. Since a current source need be provided only on the defuzzifier board, there is no need to provide current sources on the individual rule boards 50, simplifying the rule boards. With the circuit of FIG. 25, the compensator illustrated on FIG. 24 is omitted.

The configuration of the above MAX circuit may also be applied to the MAX circuits 16 and 37 illustrated in FIGS. 5, 8, 14 and 15.

While transistors Q.sub.31 through Q.sub.37 are shown connected to the output side of switches S.sub.NL through S.sub.PL in FIG. 25, the order of connection for these transistors and switches may be reversed as shown in FIG. 43. In this case, one transistor (marked by Q.sub.31) is sufficient to control the output of the MIN circuit 24a, and the switch array 52 would then be connected to the emitter of this transistor Q.sub.31.

Also, as illustrated in FIG. 44, the defuzzifier board current source 49 and the transistors Q.sub.41 through Q.sub.47 driven by this the current source 49 can be omitted and a current source 49A provided on each rule board 50, connected to the emitter of the transistor Q.sub.31.

Also, as illustrated in FIG. 45, SPDT (single-pole dual throw) switches are preferably used as the switches of the switch array 52. These SPDT switches will naturally comprise semiconductor switching elements. One of the two input terminals of these SPDT switches will be grounded. The switches of the switch arrays illustrated in FIGS. 41 and 42 can also be replaced in this way with SPDT switches.

The output voltage V.sub.o2 of the simple addition circuit 46 is provided as input to a nonreversed input terminal of an operational amplifier 47 through a resistor R.sub.14. A constant standard voltage V.sub.o is provided to the reversed input terminal of the operational amplifier 47 through a resistor R.sub.11, and the output voltage is fed back through a feedback resistor R.sub.12. The resistor R.sub.11 has a resistance sufficiently greater (e.g., 10 to 100 times) than the feedback resistor R.sub.12. The above nonreversed input terminal is grounded through a resistor R.sub.13, but this resistor R.sub.13 is not absolutely necessary.

This voltage regulator circuit 48 generates a control voltage V.sub.c such that the simple addition circuit 46 output V.sub.o2 becomes a voltage which represents a fuzzy logic value of 1.0, and this control voltage is fed back to the grade control circuits 51 which control the peak value (grade) of the membership functions of the membership function circuits 31a and 31b on each rule board 50. In this preferred embodiment, the fuzzy logical values between 0.0 and 1.0 correspond to voltage between 0 V and 5 V. Since this voltage is reversed by the operational amplifier 47 of the simple addition circuit 46, the reversed input terminal is provided a standard voltage V.sub.o of -5 V.

Thus, since the output voltage V.sub.o2 of the simple addition circuit 46 is always -5 V (corresponding to a fuzzy logical value of 1), the denominator of the equation (4) described above becomes 1, and ultimately the output voltage V of the weighted addition circuit 42 will indicate the center of gravity of the fuzzy inference results. The output of the weighted addition circuit 42 is reversed by a reverse amplifier circuit 43, becoming the final non-fuzzy output as a positive voltage.

Next the concrete structure of a rule board 50 will be described using the first rule board as an example with reference to FIG. 26. Since this circuit includes the membership function circuits 31a and 31b which generate membership functions represented by voltages, their labels LA.sub.1 and LB.sub.1 are provided as voltages (these label voltages are V.sub.LA and V.sub.LB respectively), while the inputs x.sub.A and y.sub.B are also provided as voltage signals (these input voltage signals are V.sub.x and V.sub.y respectively). The membership function circuits 31a and 31b provide output voltage signals which represent the triangular membership function MF.sub.1 described above. Since the two membership function circuits 31a and 31b have identical structures, only the one circuit 31a will be described. Since the membership function circuit 31a includes differential circuits 61 and 62, the operation of these circuits will be described using the differential circuit 62 as an example with reference to FIGS. 27 and 28.

In FIG. 27, the differential circuit 62 includes two transistors Q.sub.61 and Q.sub.62 with a variable resistor R.sub.22 connected between the emitters of these transistors. An input voltage V.sub.x is provided (if the circuit is to be used in a sweep type fuzzy computer, a sweep signal SW is provided) to the base of one of the transistors, Q.sub.61, (this will become the input terminal for the membership function circuit), while a voltage V.sub.LA representing a label is provided to the base of the other transistor, Q.sub.62. A current I is supplied by the current source to the emitters of both transistors Q.sub.61 and Q.sub.62.

Assuming the current flowing in transistor Q1 to be I.degree. 1, and the current flowing in transistor Q.sub.62 to be I.sub.62, as shown in FIG. 28(A), when V.sub.x <V.sub.LA, the current I flowing in transistor Q.sub.62 is I.sub.62, but no current flows in transistor Q.sub.61 (I.sub.62 =0). If the input voltage V.sub.x becomes greater or equal to the label V.sub.LA, the transistor Q.sub.62 current I.sub.62 will decrease linearly and the current I.sub.61 flowing in transistor Q.sub.62 will increase linearly from 0. When V.sub.x =V.sub.LA +R.sub.22 I, I.sub.62 =0 and I.sub.61 =I, and this state will be maintained in the region over which V.sub.x becomes even larger.

A current mirror CM.sub.2 is provided, and this current mirror is driven by the current I.sub.62 flowing in the transistor Q.sub.62. Connected to the output side of the current mirror CM.sub.2 is a resistor R.sub.L, and the voltage appearing at this resistor R.sub.L is the voltage x.sub.2. Since the voltage x.sub.2 is provided as x.sub.2 =I.sub.62 R.sub.L, this voltage x.sub.2 will change as the solid line in FIG. 28(B) with respect to changes in the input voltage V.sub.x. The slope of the section in which voltage x.sub.2 is changing linearly is given as- R.sub.i /R.sub.22. Therefore, this slope can be changed by changing the resistance value of resistor R.sub.22.

The other differential circuit 61 in FIG. 26 has the same structure as differential circuit 62. The currents flowing in transistor Q.sub.51 which provides the input voltage V.sub.x and in transistor Q.sub.52 which provides the label voltage V.sub.LA are I.sub.51 and I.sub.52 respectively, and these currents vary with the input voltage V.sub.x as shown in FIG. 28(C).

A current mirror CM.sub.1 is driven by the current I.sub.51 flowing in the transistor Q.sub.51. Since the current I.sub.51 is flowing through a resistor R.sub.L connected to the output side of the current mirror CM.sub.1, the dropping voltage x.sub.1 at the resistor R.sub.L is x.sub.1 =I.sub.51 R.sub.L. The changes in voltage x.sub.1 with respect to the input voltage V.sub.x are represented by the solid line in FIG. 28(D). The slope of the section in which voltage x.sub.1 is increases linearly is given as R.sub.L /R.sub.21. Resistor R.sub.21 is the resistor connected between the emitters of the two differential circuit 61 transistors Q.sub.51 and Q.sub.52, so this slope can be changed by changing the resistance value of this resistor R.sub.22.

The membership function circuit 31a includes a 2-input MIN circuit. In order for the figure to be more readily understood, the components of this MIN circuit are given the same notation Q.sub.12 and Q.sub.13 of the corresponding components of the MIN circuit of FIG. 23. The current source 64 of the MIN circuit 24a to be described later is used as current source CS.sub.1. No compensator is provided. As described above, the compensator of a MIN circuit is used to subtract the emitter/base voltage V.sub.EB of the transistor, while the compensator of a MAX circuit is used to add the emitter/base voltage V.sub.EB of the transistor. Therefore, when a MIN circuit and a MAX circuit are connected by cascade connection, the compensators of these circuits may be omitted. Since the MAX circuit containing transistors Q.sub.31 and Q.sub.41 and a wired OR described above is not provided with a compensator, the compensator of the MIN circuit including transistors Q.sub.11 and Q.sub.12 may be omitted.

The voltages x.sub.1 and x.sub.2 described above are provided to the bases of transistors Q.sub.11 and Q.sub.12 which comprise the MIN circuit. The output voltage V.sub.A1 (a.sub.A1) is the result of a MIN operation on the voltages x.sub.1 and x.sub.2, a graph of which is shown as the solid line on FIG. 28(E). The output voltage V.sub.A1 becomes triangularly shaped with respect to input voltage V.sub.x, representing the triangular membership function MF.sub.1. Furthermore, the input voltage corresponding to the peak value is the label voltage V.sub.LA. Depending on the resistors R.sub.21 or R.sub.22, the slope will vary as shown by SL.sub.1 and SL.sub.2 on FIG. 1B.

While not particularly relevant to FIG. 26, for the sake of completeness, if the input voltage V.sub.x were a sweep described above, the output voltage V.sub.A1 would change to a triangular wave on the time axis. The input voltage V.sub.x and label voltage V.sub.LA could take on positive or negative values.

Similarly, the other membership function circuit 31b also uses a set label voltage V.sub.LB to obtain an output voltage V.sub.B1 representing a membership function value (a.sub.B1) corresponding to the input voltage V.sub.y.

The MIN circuit 24a includes a wired OR 63 and a current source 64. Furthermore, the output voltages V.sub.A1 and V.sub.B1 of the above membership function circuits 31a and 31b are provided to this wired OR 63. The output of the wired OR becomes the voltage V.sub.M1 which represents the results of the MIN operation corresponding to a1

To describe this in further detail, transistors Q.sub.11 and Q.sub.12 of membership function circuit 31a, transistors Q.sub.11 and Q.sub.12 of membership function circuit 31b, the wired OR 63 and the current source 64 comprise a 4-input MIN circuit.

As can be seen from the graph of FIG. 28(E), the peak value of the membership function of membership function circuits 31a and 31b is determined by IR.sub.L. If resistance R.sub.L is constant, the peak value varies as the current I changes.

The grade control circuits 51 are used to vary the current I depending on a given control voltage V.sub.c. The grade control circuits 51 include a current mirror CM.sub.4 which acts as a current source. This current mirror CM.sub.4, transistors Q.sub.53 and Q.sub.54. which act as the current source for the membership function circuit 31a and transistors Q.sub.53 and Q.sub.54 which act as the current source for the membership function circuit 31b comprise a multicurrent mirror. Therefore, a current equal to the current I which flows through the current mirror CM.sub.4 will flow through these transistors Q.sub.53 and Q.sub.54. The current mirror CM.sub.4 contains a capacitor C.sub.1. This capacitor C.sub.1 is a capacitor used for phase compensation. As shown in FIG. 25, this capacitor can prevent fluctuations when the output of the voltage regulator circuit 48 is fed back to the input V.sub.c of the grade control circuit 51.

This current mirror C.sub.4 drives another current mirror CM.sub.5. The collector of one of the current mirror CM.sub.5 transistors is connected to a resistor R.sub.o. Since a current I flows through this resistor R.sub.o, the voltage V.sub.R =IR.sub.o appears.

The grade control circuit 51 is provided with a differential circuit 65 and a current source CS.sub.o. The differential circuit 65 includes two transistors Q.sub.71 and Q.sub.72, the emitters of which are connected to two resistors R.sub.23 and R.sub.24 of the same resistance values, and their point of connection is connected to the output side of current source CS.sub.o.

The base of one of the transistors Q.sub.71 is provided with the control voltage V.sub.c, while the base of the other transistor Q.sub.72 is provided with the above voltage V.sub.R. If these voltages V.sub.c and V.sub.R are equal, an equal current will flow through the two transistors Q.sub.71 and Q.sub.72 from the current mirror CM.sub.3.

If these voltages V.sub.c and V.sub.R are not equal, a difference in the currents I.sub.1 and I.sub.2 flowing through the two transistors will occur. The current mirror CM.sub.3 acts to keep equal currents flowing through the two transistors Q.sub.71 and Q.sub.72, so any difference in currents I.sub.1 and I.sub.2 will flow to the base of transistor Q.sub.73 connected to the collector side of transistor Q.sub.72, so current of a value the amplification factor .beta. times this difference will flow through emitter of transistor Q.sub.73. The emitter of transistor Q.sub.73 is connected to the current mirror CM.sub.4 through a Zener diode ZD, so the current flowing through the current mirror CM.sub.4 will change. This change in current will appear as a change in the current I flowing through the resistor R.sub.o, acting to make the voltage V.sub.R equal to the control voltage V.sub.c. The Zener diode ZN gives the emitter of transistor Q.sub.73 an appropriate potential, but can also be replaced by providing a plurality of transmitters.

Assuming the difference between the voltages V.sub.C and V.sub.R to be .DELTA.V, and that R.sub.23 =R.sub.24 =r.sub.c, the current I and voltage V.sub.R are found by the following equations. ##EQU13## Therefore,

and assuming (1/r.sub.e).multidot..beta..multidot.R.sub.o >>1,

Therefore, the current I flowing in resistor R.sub.o becomes

In this way, the current I will be controlled by the control voltage V.sub.c, and the peak voltage of the membership function circuits 31a and 31b will be controlled so that the output voltage V.sub.o2 of the simple addition circuit 46 illustrated in FIG. 25 will be equal to the standard voltage V.sub.o (equivalent to a fuzzy logical 1). Since the control voltage V.sub.c is provided to each rule board 50, the above control will be carried out on each rule board 50.

The combination of a membership function circuit 31a or 31b and a grade control circuit 51 is called a grade-controllable membership function circuit (GC-MFC).

While not particularly relevant to this preferred embodiment, when the peak value of the grade-controllable membership function circuits on each rule board are controlled, the output voltage V.sub.o2 (V.sub.c) of the simple addition circuit 46 is not fed back to each rule board. So the output voltage V.sub.o1 of the weighted addition circuit 42 is divided by the output voltage V.sub.o2 of the simple addition circuit 46 according to equation (4) so that the final non-fuzzy output is obtained.

FIG. 46 illustrates another preferred embodiment. As described above, the label (weighting) of the singletons in the consequent is defined by the resistors R.sub.i (1.ltoreq.i.ltoreq.r) and the resistor R.sub.f. In FIG. 25 these resistors R.sub.i and R.sub.f are all provided on the defuzzifier board. In the circuits of FIG. 46, the input resistor R.sub.i of the weighted addition circuit 42 and input resistors R.sub.o of the simple addition circuit 46 are provided on each rule board. Moreover, the weighting can be changed by using variable resistors for the resistors R.sub.i. One of the switches S.sub.P and S.sub.N will generally be on. If a certain rule board is not in use, both switches S.sub.P and S.sub.N are turned off, or the resistors R.sub.i is given infinite resistance.

In FIG. 46, the output voltage a.sub.M1 of each rule board 50 is provided to the resistors R.sub.i and R.sub.o through a buffer circuit 50a. Each of the resistors R.sub.i are connected to the output terminals T.sub.P and T.sub.N through switches S.sub.P and S.sub.N. Switch S is turned on for a positive singleton, while switch S.sub.N is turned on for a negative singleton. The voltages appearing at the output terminals T.sub.P and T.sub.N through these switches S.sub.P and S.sub.N are V.sub.Pi and V.sub.Ni respectively. On the other hand, the resistor R.sub.o is connected to a rule board output terminal T.sub.o. The voltage appearing at this terminal is V.sub.oi.

The output terminals T.sub.p of all of the rule boards 50 are connected to the input terminals T.sub.p of the defuzzifier board, the output terminals T.sub.N to the input terminals T.sub.N, while the output terminals T.sub.o of all of the rule boards 50 are connected to the input terminals T.sub.o of the defuzzifier board.

On the defuzzifier board, the weighted addition circuit 42 comprises operational amplifier circuits 41A and 41B connected to the input terminals T.sub.P and T.sub.N respectively, and an operational amplifier circuit 41C which subtracts the output of these operational amplifier circuits 41A and 41B. The operational amplifier circuit 41A carries out the summation ##EQU14## while the operational amplifier circuit 41B carries out the ##EQU15## is obtained from the operational amplifier circuit 41C.

Naturally, a signal representing ##EQU16## is obtained from the simple addition circuit 46.

In the preferred embodiment illustrated in FIG. 46, no MAX circuit is provided. This is because this preferred embodiment uses addition/subtraction rules instead of MIN/MAX operation rules.

Next, a sweep type fuzzy controller based on algebraic product rules, will be described as a practical application of grade-controllable membership function circuits (GC-MFC).

Consider the most simple example, in which one implication is present and this implication includes one fuzzy proposition in its antecedent. In the sweep type controller illustrated in FIG. 15, the MIN operation (with the MIN circuit 38) was used for the fuzzy inference synthesis operation. The fuzzy controller described here uses the algebraic product (or so-called multiplication) for the fuzzy inference synthesis operation.

In reference to FIG. 29A, two GC-MFC, 31GC and 33GC, are provided. These GC-MFC are combinations of the membership function circuit 31a (MFC 1a) and the grade control circuit 51 illustrated in FIG. 26. One of the circuits, GC-MFC 31GC is provided with the definitive-value input V.sub.x. The label voltage V.sub.LA is also set. A constant voltage V.sub.c (corresponding to V.sub.c in FIG. 26) is provided as the grade control voltage for this circuit 31GC. Naturally, this control voltage V.sub.c can be changed if necessary (e.g., to add weighting as described hereafter). If the control voltage V.sub.c is a constant, a membership function circuit (which provides a constant current to transistors Q.sub.53 and Q.sub.54 of circuit 31a in FIG. 26) can be used instead of this GC-MFC 31GC.

The other circuit, GC-MFC 33GC is provided a sweep signal SW from the timing circuit 60. It is also provided the output voltage V.sub.A (corresponding to the output voltage V.sub.A1 in FIG. 26) from the previous GC-MFC 3lGC. This circuit 33GC also has a characteristic label voltage V.sub.LB set.

As described above, the grade control voltage sets the grade (peak value) of the GC-MFC. Since the output voltage V.sub.A from GC-MFC 31GC is provided as the grade control voltage for GC-MFC 33GC, GC-MFC 33GC multiplies the output voltage V.sub.A by appropriate values to obtain the output V.sub.B which represents a membership function distributed over the time axis. In short, fuzzy inference operations of algebraic products are carried out.

The output voltage V.sub.B the GC-MFC 33GC is next provided to the center of gravity determination circuit 36SW, where the voltage V.sub.W which represents the center of gravity is produced, becoming the definitive output of this fuzzy controller.

In the event that a plurality of implications are present, in the same manner as is illustrated in FIG. 15, as many pairs of circuits, made up of the two GC-MFC circuits 31GC and 33GC, as the number of implications are prepared. A MAX operation on the output of these circuits is carried out and the results of this MAX operation is defuzzified with a defuzzifier (center of gravity determination circuit).

In the event that two fuzzy propositions are present in the antecedent of one implication, the output of the MIN or MAX circuit 24a illustrated in FIG. 16 is provided as a grade control voltage for the GC-MFC 33GC, and this GC-MFC 33GC is made into the membership function circuit of the consequent of the implication. The case of three or more fuzzy propositions is handled similarly. If there is a plurality of implications with two or more fuzzy propositions present in the antecedents, naturally, the output of each GC-MFC 33GC should be provided to a MAX circuit 37 (FIG. 15).

FIG. 29B illustrates an example of a parallel type fuzzy controller based on algebraic product rules. To explaining it in contrast to FIG. 29A, the GC-MFC 33GC is replaced with a grade-controllable membership function generator circuit GCMFG 13GC and the output of the former GC-MFC 31GC is provided as the grade control voltage for the GC-MFG 13GC. The output of the GC-MFG 13GC is provided to a defuzzifier 15 so no truncation circuit is required. By using a MAX circuit, this controller is expandable if a plurality of implications are present, and by providing the output of the MIN or MAX circuit 24a illustrated in FIG. 14 to the GC-MFG 13GC as a control voltage V.sub.c, it can be expanded to be applicable to cases in which two or more fuzzy propositions are present in the antecedent of the implications.

One example of the center of gravity determination circuit 36SW in FIG. 29A is described simply here with reference to FIGS. 28 and 31. FIG. 30 is one example of the structure of the center of gravity determination circuit 36SW. FIG. 31 is a waveform diagram illustrating the operation of the fuzzy controller illustrated in FIG. 29, including this center of gravity determination circuit. In a sweep type fuzzy controller, the voltage signals which represent inference results are expressed on the time axis. Fuzzy inferences are made every period .tau. of the sweep signal SW, and one center of gravity determination operation is carried out every two periods (2.tau.)l. Therefore in the space of two periods (2.tau.), the input voltage V.sub.x is maintained as a constant. If the time axis of the sweep signal SW is T, the local time variable for the voltage V.sub.B (t) which represents the inference results is t. The origin of time t is, for example, the point at which the sweep signal SW crosses zero.

As explained in reference to FIG. 9, the center of gravity position of the inference results B' is the point on the time axis at which the surface area of the function B'=.mu.(t) is divided equally with left and right (before and after) symmetry. First the surface area S.sub.0 of the inference results B' from the first period is found. Then in the second period, the integral control action is carried out on the time axis, and the time t.sub.w at which the integral value becomes exactly S.sub.0 /2 represents the center of gravity position. This is to say the center of gravity of the interference results B' can be represented as the time on the time axis t when the above integral value becomes S.sub.0 /2, or the time on the time axis T at this time, or the phase of the sweep signal SW at that time. This phase on the sweep signal SW can also be expressed as the corresponding sweep signal SW voltage V.sub.w. Therefore, this voltage V.sub.w becomes the definitive output of the inference results B' from the center of gravity determination circuit 36SW.

In reference to FIGS. 30 and 31, the above integral control action can be embodied as the charging of a capacitor, in which the charging voltage represents the integral value. A capacitor C.sub.11 with a capacitance of 2 C.sub.0 (C.sub.0 may be any value) and a capacitor C.sub.12 with a capacitance of C.sub.o, half this amount, are provided. The voltage signal V.sub.B which represents the inference results is converted by a voltage/current converter circuit 63 to a current I.sub.B which corresponds to that voltage and provided to a selector switch 64. The selector switch 64 is switched between sending current to capacitor C.sub.11 or sending current to capacitor C.sub.12, being controlled by the selector control signal SC. The selector control signal SC is provided by the timing circuit 60, being H level during the first period and L level during the second period, repeating after two periods 2.tau..

In the first period, the input current I.sub.B is provided to capacitor C.sub.11, thus charging capacitor C.sub.11. When the first period ends, the voltage V.sub.1 of capacitor C.sub.11 represents the above surface area S.sub.0, and this is provided to the negative input terminal of comparator 65. In the second period, the current I.sub.B flows into capacitor C.sub.12 through the selector switch 64. Since the capacitance of capacitor C.sub.12 is one half the capacitance of capacitor C.sub.11, when capacitor C.sub.12 is charged with half the electric charge of capacitor C.sub.11 (meaning that the integrated surface area has become S.sub.0 /2), the voltage V.sub.2 of capacitor C.sub.12 becomes equal to the voltage V.sub.1 of capacitor C.sub.11. The voltage of capacitor C.sub.12 is provided to the positive input terminal of comparator 65. Therefore, the point in time when the output V.sub.0 of comparator 65 rises is the point t.sub.w representing the center of gravity. When the second period ends, the reset signal PR generated from the timing circuit 60 will turn on switches 61 and 62 thus discharging capacitors C.sub.11 and C.sub.12.

The rise of the output voltage V.sub.o of comparator 65 is then detected, and the point in time of that rise t.sub.w is sent to a circuit which converts the rise into a corresponding sweep signal SW voltage V.sub.w. The rise of signal V.sub.o is detected by a differential circuit 66, and furthermore this rise detection pulse is converted by a monostable multivibrator, etc., to a single pulse signal S.sub.0 of constant amplitude which is then provided as output. The pulse duration of this pulse signal S.sub.0 is preferably as short as possible as long as it is of sufficient duration to charge capacitor C.sub.c to be described hereafter. The pulse signal S.sub.0 is used to control an analog switch 67, and this switch 67 is on for only a time period equal to the duration of the pulse signal S.sub.0. Thus the capacitor C.sub.c is charged by the sweep signal SW provided to this switch 67 up to a voltage equal to the voltage of the signal at that time. The voltage of capacitor C.sub.c is maintained until next pulse signal S.sub.0 is generated. When the switch 67 is turned on by the next pulse signal S.sub.0, if the voltage of the sweep signal SW is higher than the voltage of the capacitor C.sub.c, the capacitor C.sub.c is charged to a voltage equal to that of the sweep signal SW, if lower, the capacitor C.sub.c is discharged to a voltage equal to that of the sweep signal SW. In this way, the voltage of capacitor C.sub.c always represents the determined center of gravity position. This voltage could be the output of a center of gravity position voltage V.sub.W provided through, for example, an FET input operational amplifier 68.

The theory of center of gravity determination using the circuits of FIG. 30 is as follows: a first capacitor of capacitance 2 C.sub.0 is charged by input current during the first period, then in the second period, a second capacitor of capacitance C.sub.0, half of that of the first capacitor, is charged with the same input current. The time t.sub.W at which the voltage of the second capacitor becomes equal to the voltage of the first capacitor is detected as the time which represents the center of gravity. Instead of using two capacitors with capacitances of 2 C.sub.o and C.sub.o, two capacitors of equal capacitance can also be used. In this case, during the second integral control action of the inference results, a current of twice that of the input current is used. Specifically, in this method, the first capacitor of a certain capacitance is charged by the input current, and then the second capacitor of the same capacitance as the first capacitor is charged by a current of twice the input current. The time t.sub.W at which the voltage of the second capacitor becomes equal to the voltage of the first capacitor is detected as the time which represents the center of gravity. The voltage can also be doubled instead of the current.

(5) Fuzzy Controller Able to Apply Weighting for Each Rule

As described earlier, FIG. 14 illustrates a parallel type fuzzy controller suited to the case of a plurality of implication rules with two fuzzy propositions in their antecedents. Fuzzy inferences for one implication rule are made using a fuzzy inference synthesis circuit 14a which uses as input the output from two membership function circuits 31a and 31b and one membership function generator circuit 13. These circuits 31a, 31b, 13 and 14a are together called a rule board.

For fuzzy inferences predicated upon the existence of a plurality of implication rules, all of the implication rules are not necessarily of the same importance. In some instances an implication may be extremely important, while others may be not very important at all. For this reason, the implication rules will be weighted according to their importance. This weighting is applied to each rule board. The weighting is accomplished by simultaneously controlling the grades (peak values) of both the antecedents and consequents, so that implications of high importance are given high grade settings. The membership function circuits and membership function generator circuits belonging to one rule board will be weighted identically, specifically the membership peaks of the antecedents and consequents will be set to the same values.

To weight the membership functions of the membership function circuits, the grade-controllable membership function circuits (GC-MFC) described above are used. To weight the membership functions generated by the membership function generator circuits, grade-controllable membership function generator circuits (GC-MFG) to be described below are used. FIG. 32 illustrates one rule board R of the fuzzy controller of FIG. 14 rewritten to use such GC-MFC and GC-MFG circuits. FIG. 32, aside from the membership function circuits 31a and 31b and the membership function generation circuit I3 being replaced by GC-MFC 31GCa, 31GCb and GC-MFG 13GC, is exactly identical to one of the rule boards illustrated in FIG. 14. The maximum grades (peak value of the membership functions) of GC-MFC 31GCa, 31GCb and GC-MFG 13GC are all controlled by one grade control voltage V.sub.c to be exactly equal. This grade control voltage V.sub.c can be set manually from the outside, or it can be adjusted by a digital computer or the like based on the results of some sort of learning with respect to the controlled system for which the fuzzy controller is used.

The control voltage V.sub.c of the GC-MFC can be provided instead of the control voltage V.sub.c of the GC-MFC illustrated in FIG. 26 (comprising a combination of a grade control circuit 51 and a membership function circuit 31a or 31b).

The GC-MFG will be described hereafter.

In FIG. 33, the GC-MFG 73 comprises a voltage distribution generator circuit 74 which generates the specified voltage distribution on a plurality of signal lines, a switch array 75 used to send the generated voltage distribution to the specified output signal line, and a decoder which deciphers the codes which represent the provided labels and controls the switches of switch array 75. The form of the voltage distribution generated by the voltage distribution generator circuit 74 is previously determined but the position on the output signal lines is changed by the switch array 75 controlled by the output of the decoder 76. Therefore, the voltage distribution representing the membership function corresponding to the given label will appear on the output lines. The grade (voltage value) of the voltage distribution generated by the voltage distribution generator circuit 74 is adjusted by the grade control signal V.sub.c.

Several concrete examples of GC-MFG circuits will be described hereafter, and these will generate seven types of membership functions. The labels of these membership functions are the NL, NM, NS, ZR, PS, PM and PL labels described above. In addition, the number of points in the domain of variables of the membership function (corresponding to the number of elements in the fuzzy set) is limited to 25. Therefore, there are 25 output terminals from the membership function generator circuit.

FIG. 34 and FIG. 35 illustrate an example of a GCMFG in which a switch matrix is used as the switch array. In FIG. 34, beneath the GC-MFG output terminals numbered from 0 to 24 are diagrammed the seven types of membership functions provided as output from these output terminals.

The output values of the fuzzy membership functions are quantized into four levels for simplicity. These four levels are 0, V.sub.c1, V.sub.c2, and and the maximum value of the control voltage V.sub.c is, for example, 5 V. These four levels of voltage are generated by a voltage distribution generator circuit 74A. This circuit 74A includes three resistors 71 connected in series, so the control voltage V.sub.c applied to this resistance circuit results in voltages of V.sub.c1 and V.sub.c2 at the points of connection to the resistors 71. Therefore, V.sub.C1 =V.sub.c /3 and V.sub.c2 =2V.sub.c /3. Five voltage lines VL from this voltage distribution generator circuit 74A are drawn on a slant in FIG. 34. The middle line is provided a voltage of V.sub.C3, the lines to each side are provided with voltages of V.sub.c2 and the outermost two lines with voltages of V.sub.c1.

A decoder 76A is a 1-of-8 decoder. Input to the decoder 76A is a 3-bit (c.sub.1, c.sub.2 and c.sub.3) binary signal representing the labels. The decoder 76A provides output of an H level signal on one of its eight output terminals depending on the code represented by the input signal. The eight output terminals correspond to "unset" or one of the seven labels described above. For example, if the input code is 000, an H level signal is generated on the unset output terminal, or if the input code is 001, an H level signal is generated on the NL output terminal. With the exception of the unset output terminal, signal lines SL lead from these output terminals as shown by the parallel lines on FIG. 34.

In the switch matrix 75A, 25 output lines OL lead from specified intersections of the voltage lines VL and signal lines SL. The symbols 75a indicated by small squares at these intersections, as shown in FIG. 35, are switches provided between the voltage lines VL and the output lines OL. The switches comprise MOSFETs, for example, and are toggled on and off by the voltage of the signal lines SL. Naturally, two or more switches 75a may be provided on one output line OL. Each of the output lines OL is grounded on its output terminal side through a resistor 75b.

In the above structure, when the label of a certain membership function is provided to the decoder 76A, a signal of the H (enable) level appears on the signal label SL which corresponds to that label, and the switches 75a provided on that signal line are turned on. As a result, the various voltages of the voltage distribution generator circuit 74A pass through the toggled-on switches 75a and through the output lines OL to appear at the corresponding output terminals, thus producing output of a voltage distribution representing the membership function described above. Furthermore, the grade of the output membership function is controlled by the control voltage V.sub.c.

FIGS. 36 and 37 illustrate a GC-MFG which uses a pass transistor array as its switch array.

A voltage distribution generator circuit 74B quantizes the membership function into 11 discrete levels, having a voltage divider circuit made up of ten series resistors 71. The control voltage V.sub.c is applied to this voltage divider circuit. Appearing at the earth terminal and the junctions between resistors are the fuzzy truth value voltages 0, V.sub.c1 =V.sub.c /10, V.sub.c2 =2V.sub.c /10, . . . , V.sub.c9 =9V.sub.c /10, and V.sub.310 =V.sub.c, which represents the fuzzy truth values 0, 1/10, . . . , 9/10 and 1 respectively. These voltage V.sub.c1 through V.sub.C10 are also variable depending on the control voltage V.sub.c. This voltage distribution generator circuit 74B is also equipped with a PROM programmed with the value of the membership function of the label ZR. This PROM is also provided with the voltage lines VL connected between the above voltage source and the ground, and the output lines OL connected through the pass transistor array to the output terminals. The PROM is comprised of two A layers, a top and bottom layer, such that the output lines OL are formed on the first layer, while the voltage lines VL are formed on the second layer. These two layers are insulated by an insulating layer of a material such as photosensitive polyimide. The shape of the membership function can be programmed by forming through holes between these two layers. Since the through holes can be formed using masked ROM technology, a membership function of any shape can be programmed. The black circles indicating nodes between a line VL and line OL indicate represent through holes. A voltage line VL and an output line OL are connected at the points where through holes are formed, so the fuzzy truth value voltages are transferred to the pass transistor array 75B. The nodes between two lines, a VL and an OL, can also be formed using field ROM technology, in which high voltage is applied to induce dielectric breakdown at the desired intersections, thus shortcircuiting the lines.

The pass transistor array 75B comprises output lines 0L extending from the voltage distribution generator circuit 74B, signal lines SL connected to the seven output terminals of the decoder 76A, diagonal lines BL used to shift the voltages at the intersections of these lines by four or eight digits to the right or left, along with switching devices which are PMOS FETs 75c provided at the junctions of the signal lines SL, output lines OL and the diagonal lines BL and controlled by the voltage of the signal lines SL. The connections of these switching devices 75c are illustrated in detail in FIG. 37. The seven signal lines SL connected to the decoder 76B and the rows of switching devices controlled by these lines are named switch row S.sub.1, S.sub.2, . . . , S.sub.7 respectively. The notation S.sub.1 through S.sub.7 can also designate the signals on these lines SL.

Switch row S.sub.1 shifts the membership function programmed in the voltage distribution generator circuit 74B four digits to the left, while switch rows S.sub.3, S.sub.4 and S.sub.6 shift the function four digits to the right, eight digits to the left and eight digits to the right, respectively. Switch rows S.sub.2 and S.sub.5 do not shift the programmed membership function to the left or right, but rather send it directly to the output terminals. Switch row S.sub.7 is a grounded switch array, so when this switch S.sub.7 is on and the other switches S.sub.1 through S.sub.6 are off, the output terminals are dropped to ground level.

The relationship between the membership function labels and the binary levels of signals S.sub.1 through S.sub.7 is illustrated in FIG. 38. The decoder 76B converts the input of 3-bit binary signals c.sub.1, c.sub.2, and c.sub.3 (either 0 V or +5 V) into the 7-bit binary signals S.sub.1 through S.sub.7 (either -5 V "L level" or +5 V "H level") according to the table shown in FIG. 38. As shown in FIG. 39, the decoder physically comprises a combination of NAND gates 77 and inverters 78.

For example when the input label is PL, switch rows S.sub.3 and S.sub.6 are toggled on. The membership function programmed in the voltage distribution generator circuit 74B passes through switch row S.sub.3 and is shifted four digits to the right, and then passes through switch row S.sub.6 and is shifted eight digits to the right. Therefore, the programmed membership function is shifted a total of 12 digits to the right, so the membership function appearing at the output terminals is PL (positive large).

In FIG. 36, the line VL connected to the ground level of the voltage distribution generator circuit 74B is connected to the central 25 output lines OL and an additional 12 lines both on the left and right, all of which are parallel to the output lines OL, along with the diagonal lines BL. Switch rows S.sub.1, S.sub.2, S.sub.3, S.sub.4 and S.sub.6 are provided at the points of intersection of these lines and the signal lines SL. These lines and switches are provided to be certain that the ground level signal is provided to the output terminals no matter how the programmed membership signal may be shifted.

The pass transistor array 75B must pass the fuzzy truth value voltages (0 to 5 V) to the output terminals without attenuation. In normal PMOS circuits, when the fuzzy truth value voltage would be lower than the PMOS FET threshold voltage, the PMOS FET will not be completely in the on state if the gate voltage V.sub.G (decoder output) is 0 V. In order to put a PMOS FET completely in the on state, Ve must be approximately -5 V. For this reason, as described above, the decoder 76B is configured so that it generates output which takes the values -5 V (L) and +5 V (H). FIG. 40 illustrates an example of one of the NAND gates 77 which make up the decoder of FIG. 39 which generates these output signals S.sub.1 through S.sub.7.

In the above explanation, the fuzzy membership function is illustrated as being angular or triangular in shape. Yet many shapes are conceivable for the membership function, so it is preferable to be able to select a different shape if necessary.

FIG. 41 illustrates a voltage distribution generator circuit which is applicable to the type of GC-MFG illustrated in FIG. 34, and in which the shape of the fuzzy membership function can be selected. Voltage lines VL are connected to nodes at which appear voltages V.sub.c1 through V.sub.c4 which controlled by control voltage V.sub.c. One set of output lines OLl is connected to voltage lines VL in such a way that a voltage distribution representing an angled or triangular fuzzy membership function shape is produced. Another set of output lines OL2 is connected in such a way that a voltage distribution representing a truncated triangle-shaped function shape is produced. Connected to each of these lines OL1 and OL2 are switching devices, NMOS FET 70A and 70B, and through the output side of these switching devices, the lines OLI and OL2 are connected to the output lines OL connected to the output terminals. The switching devices 70B are controlled directly by the selection signal c, while the devices 70A are controlled indirectly through an inverter 79. .

When the selection signal c.sub.S is L level, the switching devices 70A are on, so voltages representing an angled or triangular fuzzy membership function shape are produced on the output lines OL. When the selection signal c.sub.S is H level, the switching devices 70B are on, so voltages representing a truncated triangle-shaped function shape are produced. Thus the shape of the fuzzy membership function can be selected.

In the circuits of FIG. 41, if the threshold value voltage is V.sub.TH (normally approximately 1 V), the binary levels of the selection signal c which controls this FET should be set so the L level is V.sub.TM or less, and H is +5 V or more. In this case, 5 V is the maximum voltage of the control voltage V.sub.c.

The shape of the voltage distribution generated by the voltage distribution generator circuit, and hence the shape of the fuzzy membership function is not limited to the two shapes described above, but rather three or more shapes can be created in advance and one of them may be selected. Naturally, selection of the function shape is also applicable to the GC-MFG illustrated in FIG. 36.

The voltage distribution generator circuit generates a voltage signal which is distributed over a plurality of lines. Therefore, the output voltages from one voltage distribution generator circuit may be provided to a plurality of switch arrays 75. FIG. 42 illustrates a GC-MFG which contains one voltage distribution generator circuit 74 and a plurality of switch arrays 75 to which this output voltage is provided. Each of the switch arrays 75 is driven by its own decoder 76. The various decoders may be provided with code signals of the same or different labels. Therefore, a plurality of voltage distributions representing the same or different membership functions may be obtained from this GC-MFG. Furthermore, the grades of this plurality of membership functions are equally and simultaneously controlled by means of the control voltage V.sub.c.

The GC-MFG illustrated in FIG. 42 is particularly suited for use in the parallel type fuzzy computers illustrated in FIGS. 4 and 5. In this case also, the grade for each implication can naturally ge controlled.

The GC-MFG is can also be applied to the sweep type fuzzy computer illustrated in FIG. 8. In this case also, it is preferable to adjust the grade for each implication.

Next, a specific example of a GC-MFC will be explained in reference to FIG. 47. Since the membership function circuits 31a and 31b generate membership functions represented by voltages, their labels LA.sub.1 and LB.sub.1 are provided as voltages (these label voltages are V.sub.LA and V.sub.LB respectively), while the inputs x.sub.A and y.sub.B are also provided as voltage signals (these input voltage signals are V.sub.X and V.sub.Y respectively). The membership function circuits 31a and 31b provide output voltage signals which represent the triangular membership function MF.sub.1 described above. Since the two membership function circuits 31a and 31b have identical structures, only the one circuit 31a will be described. Since the membership function circuit 31a includes differential circuits 61 and 62, the operation of these circuits will be described using the differential circuit 62 as an example with reference to FIGS. 48 and 49.

In FIG. 48, the differential circuit 62 includes two transistors Q.sub.61 and Q.sub.62 with a variable resistor R.sub.22 connected between the emitters of these transistors. An input voltage V.sub.x is provided to the base of one of the transistors, Q.sub.61, (this will become the input terminal for the membership function circuit), while a voltage V.sub.LA representing a label is provided to the base of the other transistor, Q.sub.62. A current I is supplied by the current source to the emitters of both transistors Q.sub.61 and Q.sub.62.

Assuming the current flowing in transistor Q.sub.61 to be I.sub.61, and the current flowing in transistor Q.sub.62 to be I.sub.62, as shown in FIG. 49(A), when V.sub.x <V.sub.LA,the current I flowing in transistor Q.sub.62 is I.sub.62, but no current flows in transistor Q.sub.61 (I.sub.62 =0). If the input voltage V.sub.x becomes greater or equal to the label V.sub.LA, the transistor Q.sub.62 current I.sub.62 will decrease linearly and the current I.sub.61 flowing in transistor Q.sub.62 will increase linearly from 0. When V.sub.x =V.sub.LA +R.sub.22 I, I.sub.62 =0 and I.sub.62 :=I, and this state will be maintained in the region over which V.sub.x becomes even larger.

A current mirror CM.sub.2 is provided, and this current mirror is driven by the current I.sub.62 flowing in the transistor Q.sub.62 Connected to the output side of the current mirror CM.sub.2 is a resistor R.sub.L, and the voltage appearing at this resistor R.sub.L is the voltage x.sub.2. Since the voltage x.sub.2 is provided as x.sub.2 =I.sub.62 R.sub.L, this voltage x.sub.2 will change as the solid line in FIG. 49(B) with respect to changes in the input voltage V.sub.x. The slope of the section in which voltage xz is changing linearly is given as - R.sub.L /R.sub.22. Therefore, this slope can be changed by changing the resistance value of resistor R.sub.22.

The other differential circuit 61 in FIG. 26 has the same structure as differential circuit 62. The currents flowing in transistor Q.sub.51 which provides the input voltage V.sub.x and in transistor Q.sub.52 which provides the label voltage V.sub.LA are I.sub.51 and I.sub.52 respectively, and these currents vary with the input voltage V.sub.x as shown in FIG. 49(C).

A current mirror CM.sub.1 is driven by the current I.sub.51 flowing in the transistor Q.sub.51. Since the current I.sub.51 is flowing through a resistor R.sub.L connected to the output side of the current mirror CM.sub.1, the dropping voltage x.sub.1 at the resistor R.sub.L is x.sub.1 =I.sub.51 R.sub.L. The changes in voltage x.sub.1 with respect to the input voltage V.sub.x are represented by the solid line in FIG. 49(D). The slope of the section in which voltage x.sub.1 is increases linearly is given as R.sub.L /R.sub.21. Resistor R.sub.21 is the resistor connected between the emitters of the two differential circuit 61 transistors Q>: and Q.sub.52, so this slope can be changed by changing the resistance value of this resistor R.sub.22.

The membership function circuit 31a includes a 2-input MIN circuit. The voltages x.sub.1 and x.sub.2 described above are provided to the bases of transistors Q.sub.11 and Q.sub.12 which comprise the MIN circuit. The output voltage V.sub.A1 (.mu..sub.A) is the result of a MIN operation on the voltages x.sub.1 and x.sub.2, a graph of which is shown as the solid line on FIG. 49(E). The output voltage V.sub.A becomes triangularly shaped with respect to input voltage V.sub.x, representing the triangular membership function MF.sub.1. Furthermore, the input voltage corresponding to the peak value is the label voltage V.sub.LA. Depending on the resistors R.sub.21 or R.sub.22, the slope will vary as shown by SL.sub.1 and SL.sub.2 on FIG. 1B.

Similarly, the other membership function circuit 31b also uses a set label voltage V.sub.LB to obtain an output voltage V.sub.B1 representing a membership function value (.mu..sub.B) corresponding to the input voltage V.sub.y.

The MIN circuit 24a (included in the fuzzy inference synthesis circuit 14a, see FIG. 15) includes a wired OR 63 and a current source 64. Furthermore, the output voltages V.sub.A and V.sub.B of the above membership function circuits 31a and 31b are provided to this wired OR 63. The output of the wired OR becomes the voltage V.sub.M which represents the results of the MIN operation corresponding to a.sub.M1 (a.sub.M).

To describe this in further detail, transistors Q.sub.11 and Q.sub.12 of membership function circuit 31a, transistors Q.sub.11 and Q.sub.12 of membership function circuit 31b, the wired OR 63 and the current source 64 comprise a 4-input MIN circuit.

As can be seen from the graph of FIG. 49(E), the peak value of the membership function of membership function circuits 31a and 31b is determined by IR.sub.L. If resistance R.sub.L is constant, the peak value varies as the current I changes.

The grade control circuits 51 are used to vary the current I depending on a given control voltage V.sub.c. The grade control circuits 51 include a current mirror CM.sub.4 which acts as a current source. This current mirror CM.sub.4, transistors Q.sub.53 and Q.sub.54 which act as the current source for the membership function circuit 31a and transistors Q.sub.53 and Q.sub.54 which act as the current source for the membership function circuit 31b comprise a multicurrent mirror. Therefore, a current equal to the current I which flows through the current mirror CM.sub.4 will flow through these transistors Q.sub.54 and Q.sub.54. The current mirror CM.sub.4 contains a capacitor C.sub.1. This capacitor C.sub.1 is a capacitor used for phase compensation. As shown in FIG. 18, this capacitor can prevent fluctuations when the output of the voltage regulator circuit 4 is fed back to the input V.sub.C of the grade control circuit 51.

This current mirror CM.sub.4 drives another current mirror CM.sub.5. The collector of one of the current mirror CM.sub.5 transistors is connected to a resistor R.sub.c. Since a current I flows through this resistor R.sub.o, the voltage V.sub.R =IR.sub.o appears.

The grade control circuit 51 is provided with a differential circuit 65 and a current source CS.sub.o. The differential circuit 65 includes two transistors Q.sub.71 and Q.sub.72, the emitters of which are connected to two resistors R.sub.23 and R.sub.24 of the same resistance values, and their point of connection is connected to the output side of current source CS.sub.o.

The base of one of the transistors Q.sub.71 is provided with the control voltage V.sub.c, while the base of the other transistor Q.sub.72 is provided with the above voltage V.sub.R. If these voltages V.sub.c and V.sub.R are equal, an equal current will flow through the two transistors Q.sub.71 and Q.sub.72 from the current mirror CM.sub.3.

If these voltages V.sub.c and V.sub.R are not equal, a difference in the currents I.sub.1 and I.sub.2 flowing through the two transistors will occur. The current mirror CM.sub.3 acts to keep equal currents flowing through the two transistors Q.sub.71 and Q.sub.72, so any difference in currents I.sub.1 and I.sub.2 will flow to the base of transistor Q.sub.73 connected to the collector side of transistor Q.sub.72, so current of a value the amplification factor .beta. times this difference will flow through emitter of transistor Q.sub.73. The emitter of transistor Q.sub.73 is connected to the current mirror CM.sub.4 through a Zener diode ZD, so the current flowing through the current mirror CM.sub.4 will change. This change in current will appear as a change in the current I flowing through the resistor R.sub.o, acting to make the voltage V.sub.R equal to the control voltage V.sub.c. The Zener diode ZN gives the emitter of transistor Q.sub.73 an appropriate potential, but can also be replaced by providing a plurality of transmitters.

Assuming the difference between the voltages V.sub.c and V.sub.R to be .DELTA.V, and that R.sub.23 =R.sub.24 <=r.sub.e, the current I and voltage V are found by the following equations. ##EQU17## Therefore,

and assuming (1/r.sub.e).multidot..beta..multidot.R.sub.o >>1,

Therefore, the current I flowing in resistor R.sub.o becomes

In this way, the current I will be controlled by the control voltage V.sub.c, and the peak voltage of the membership function circuits 31a and 31b will be controlled so that the output voltage V.sub.o2 of the simple addition circuit 3 will be 1.

FIG. 50 illustrates the overall structure of a center of gravity determination circuit. The input to this center of gravity determination circuit is fuzzy information. This fuzzy information may represent the output of inference results from the fuzzy inference synthesis circuit of a fuzzy controller or the fuzzy inference engine of a fuzzy computer, or it may represent an inference in progress, as long as it represents a membership function generated by a membership function generator circuit.

A total of n signal lines l.sub.1, l.sub.2, l.sub.3, . . . , l.sub.i, . . . , l.sub.n-1, and l.sub.n are provided, and the fuzzy information is represented by an electrical signal (voltage or current). Fuzzy information can also be referred to as fuzzy sets (membership functions), and these fuzzy sets (membership functions) are sets of grades (function values) corresponding to a plurality of elements (variables).

FIG. 51 illustrates one example of fuzzy information. The elements of the fuzzy set (or the variables of the membership function) are represented by x, assuming the discrete values x.sub.1, x.sub.2, x.sub.3, . . . , x.sub.i, . . . , x.sub.n-1, and x.sub.n. These elements (or variables) are embodied by means of a plurality of signal lines l.sub.1 through l.sub.n. The grades (function values corresponding to the variables) .mu..sub.1, .mu..sub.2, .mu..sub.3, . . . , .mu..sub.i, . . . , .mu..sub.n-1, and .mu..sub.n are represented on these lines l.sub.1 through l.sub.2 by analog voltage or current signals.

In the following discussion, the grades .mu..sub.l through .mu..sub.n are represented by voltages. Therefore, for convenience, the voltages representing the grades l.sub.l through .mu..sub.n are also expressed as .mu..sub.l through .mu..sub.n.

The center of gravity CG (position on the x axis) of the fuzzy information is found with the following equation. ##EQU18##

As is clear from equation (1), multiplication, addition and division are required to find the center of gravity CG. By means of the center of gravity determination circuit of FIG. 50, the center of gravity CG can be found without multiplication or division, but by using addition only.

Equation (1) is transformed as follows. ##EQU19##

If the denominator of equation (12) is adjusted to be 1, the center of gravity CG would be represented by the following equation. ##EQU20##

In FIG. 50, the n signal lines l.sub.i, upon which the voltages .mu..sub.i representing the fuzzy information are distributed, are connected to the input side of a variable coefficient array 5. The operation of multiplying the voltages .mu.i by the coefficient k (k.mu.i) is carried out by the variable coefficient array 5.

The output of the variable coefficient array 5 (k.mu..sub.i) *(1.ltoreq.i.ltoreq.n) is provided to a weighted addition circuit 2. The output of the weighted addition circuit 2 is a voltage signal representing the center of gravity CG which is calculated with the right side of equation (13), namely, ##EQU21##

The output of the variable coefficient array 5 (k.mu..sub.i) (1.ltoreq.i.ltoreq.n) is also provided as input to a simple addition circuit 3. This simple addition circuit 3 calculates the denominator ##EQU22## of equation 12, and the output which represents the calculation results is provided as input to one input terminal of a voltage regulator circuit (comparator or differential circuit) 4.

A voltage equivalent to grade 1 of the fuzzy information is provided to the other input terminal of the voltage regulator circuit 4. The various grades representing fuzzy information can take any value in the range 0 to 1. By means of the output signal from this voltage regulator circuit 4, the coefficients k in the variable coefficient array 5 are adjusted so that the output of the simple addition circuit 3 is always 1.

FIG. 52 illustrates a specific example of the construction of the weighted addition circuit 2. The output k.mu..sub.1, k.mu..sub.2, k.mu..sub.3, . . . , k.mu.i, . . . , k.mu..sub.n-1, and k.mu..sub.n from the variable coefficient array 5 is provided as input to input side of an operational amplifier circuit 41 through resistors R.sub.1, R.sub.2, R.sub.3, . . . , R.sub.i, R.sub.n-1, and R.sub.n. A feedback resistor R.sub.f is provided across the operational amplifier circuit 41.

Therefore, the output voltage V.sub.o of the operational amplifier circuit 41 is given by the following equations.

Setting

simplifies equation (14) to ##EQU23##

This equation is essentially equivalent to equation (13) described above. The minus sign merely indicates that the voltage is reversed, so if necessary, an inversion (amplifier) circuit can be used to make this a positive value.

As is clear from equation (15), the elements (variables) x.sub.1 of fuzzy information (membership functions) embodied as a row position in the signal lines l.sub.1 are expressed in the weighted addition circuit 2 as the input side resistors R.sub.i.

The simple addition circuit 3 can be readily understood by taking the structure of the weighted addition circuit illustrated in FIG. 52 and setting the input-side resistors R.sub.i (1.ltoreq..ltoreq.n) all to the same resistance value.

The variable coefficient array 5 may be realized by various means. For example, it could be realized by providing each line with an amplification circuit of a magnification k which is variable depending on the output voltage of the voltage regulator circuit 4, or it could also be realized by simultaneously changing the resistance value of the input resistors (R.sub.l through R.sub.4, etc.) of the weighted addition circuit 2 and the simple addition circuit 3. Additionally, a MOS FET can be used instead of the feedback resistor as illustrated in FIG. 53.

In FIG. 53, the weighted addition circuit 2 comprises an operational amplifier circuit 41, a plurality of input resistors R.sub.l through R.sub.n, and n MOS FET transistors Q.sub.1. The simple addition circuit 3 comprises an operational amplifier circuit 42, a plurality of input resistors R, and n MOS FET transistors Q.sub.2. By controlling these MOS FET transistors Q.sub.1 and Q.sub.2 by means of the output voltage V.sub.c of the voltage regulator circuit 4, their resistance between source and drain will be changed so the gain values k.sub.1 and k.sub.2 of these addition circuits 2 and 3 will change, so that the output of the simple addition circuit 3 is always 1. Employing the good linearity of MOS FET drain characteristics is preferable. In this preferred embodiment, equation (12) can be expressed in this manner: ##EQU24##

In addition, these input resistors R.sub.l through R.sub.n and R can also be replaced by MOS FET. In this case, conversion to an IC is particularly preferable.