Method and Apparatus for Adaptive Radar Environmental Signal Filtration

This invention relates to electronic signal conditioning and more particularly to the filtering of RADAR signal data using an adaptive conditioning network to selectively transmit signal information for more efficient processing.

RADAR systems mounted aboard missiles and other target seeking projectiles are highly constrained by weight, power, size and to some degree, cost limitations. Design of these missile RADAR seekers is further complicated by the fact that since the units are traveling at speeds in excess of Mach 1, real time operation of the missile system results in the collection of vast quantities of rapidly changing data. Data which is not quickly processed soon becomes obsolete. Exacerbating the difficulty of handling enormous amounts of available data are the limits on computational power imposed by the weight, power and size constraints of the missile payload.

In accordance with the present invention, an environmental signal filter (1) gate array is described for use in the preprocessing of RADAR signals within missile seeker systems (10). The preprocessing filter (1) is used to thin incoming RADAR pulse information from the RF receiver before it is sent to the computer processor (8). Digitized RADAR pulse data is applied to a network of adaptive comparators (5) to filter out extraneous and unnecessary information. This preprocessing allows the missile seeker (10) to operate in a very dense RADAR signal environment without taxing the processing power of the on-board processor (8). Preprocessing is achieved by comparing the characteristics (discriminants) of the incoming pulses against upper and lower limits and ignoring those pulses which fall outside of the limits. The upper and lower limits define the window of acceptability for each discriminant. The window for each discriminant can be programmed individually using a discriminant mask field. Individual counters (47) keep track of each discriminant as incoming pulses are passed. Using the counter (47) information, the on-board processor (8) provides threshold control over window width based on preprogrammed parameters as applied to the incoming data stream.

FIG. 1 is a block diagram showing a typical missile seeker system (10) in which the environmental signal filter 1 of the present invention is utilized;

FIG. 2 is a schematic block diagram of the environmental signal filter 1 comprising a plurality of parallel discriminator cells 65;

FIG. 3 is a functional block diagram of the environmental signal filter 1 of FIG. 2;

FIG. 4 is a schematic block diagram of a single discriminator cell 65 of the present invention; and

FIG. 5 is a block diagram showing the gate array pin locations used in the preferred embodiment of the environmental signal filter 1.

FIG. 1 shows a typical missile seeker system 10 in which the environmental signal filter 1 of the present invention is utilized. In application, the missile seeker 10 receives reflected pulsed radio frequency (RF) signals from RADAR 2. The signals are amplified and separated in receiver 4 and digitized in analog to digital converter (ADC) 6 prior to undergoing preprocessing in environmental signal filter 1. Signal filter 1 removes part of the incoming signal by eliminating data which lies outside acceptable parameters set by processor 8. Processor 8 then receives the filtered data which it uses to provide control instructions to the missile upon which the seeker system 10 is mounted.

Referring now to FIG. 2, a schematic block diagram of the environmental signal filter 1 is shown. The preferred embodiment consists of a plurality of RF RADAR inputs 57 connected to an array of parallel discriminator cells 65. These discriminator cells 65 provide output signals to a combinational logic block 59 which networks the inputs to produce a correlation load output 63. Each of the discriminator cells 65 are synchronized with processor 8 (FIG. 1) by way of discriminator enable latch 55, which receives input from processor 8 through data bus 67. The correlation load signal 63 is synchronized with processor 8 through correlation load input 61.

The internal operation of the signal filter 1 can be more easily understood by referring to FIG. 3. In the preferred embodiment, the signal filter 1 consists of six discriminator cells 65 described above. Each discriminator cell 65 has a latch 3 which receives upper and lower threshold data from data bus 12, and which stores this threshold data to comparator 5. An incoming pulsed RADAR signal is simultaneously applied to each of the comparators 5 and logically evaluated relative to the data stored in latch 3. Through a network of combinational logic 7, a logical TRUE output signal is further applied to combinational logic 27 to provide the correlation load signal 29. The purpose of each of these discriminator cells 65 is to establish whether an incoming signal characteristic, specific to an individual discriminator cell 65, lies within a range or a window of acceptable values, Each window comparator 5 has an upper and lower threshold through which intramarginal data values may pass.

The purpose of discriminator cells 65 is to mask out unwanted data. Discriminator cells 65 are individually programmed by processor 8 by writing or storing a parallel set of threshold values to the field of discriminator cells 65 in a format referred to as the mask field. Various RADAR signal parameters generated by receiver 4 are discriminated by signal filter 1. Latch 3, referred to as the reference latch, compares amplitude or power in the RADAR signal. Latch 13 is used to check the frequency range of the incoming signal with respect to pulse repetition rate. Latch 15 and latch 17 are fine angle adjustments which relate to RADAR phase information. Course angle A latch 19 and course angle B latch 21 test for additional RADAR data characteristics based on amplitude. Sideband signal 20 is useful for daisy chaining multiple signal filters 1.

Referring now to FIG. 4, the individual discriminator cell 65 is shown in more detail. Comparator 35 logically compares pulsed RF RADAR inputs 37 to stored threshold data maintained in latch 36. In the preferred embodiment, both RF input 37 data and stored latch 36 information contains eight data bits. The single bit logical True/False comparator data output 43 which results from the logical comparison of the input data is transmitted to combinational logic 39 to produce discriminator output 49. This discriminator output 49 provides pulses to counter 47 which are then detected by processor 8. The processor 8 periodically polls the data stored in counter 47 to determine the rate at which RF input data 37 is actually being transmitted to processor 8. Processor 8 uses the rate data to control signal flow by continuously varying the threshold values stored in latch 36. If the data throughput to processor 8 becomes such that the throughput inordinately taxes the computational capabilities of processor 8, narrower threshold values are transmitted to latch 36 to effectively thin out the amount of RF input data 37 sent to processor 8. If the data flow becomes too sparse, processor 8 sends latch 36 a set of wider threshold parameters to allow the acceptance of more data. This adaptive filtering of data based on comparison to a dynamic set of threshold values is repeated in each of the six discriminator cells 65 of FIG. 2.

Referring now to FIG. 5, a block diagram is shown of the pin locations in the preferred single chip embodiment of the environmental signal filter 1. The control lines on the package include Reset 79, Clock 81, Read 83, and Write 85. The Address Bus 87 contains five lines for addresses 1 through 5. Additional control lines include Counters Clear 89, Counters Clock 91, Two's Compliment 93, and Correlation Load In 95. Input data lines include Sideband 97, Amplitude Bus 80, Frequency Bus 82, Course Angle A Bus 84, Course Angle B Bus 86, Fine Angle A Bus 88, and Fine Angle B Bus 90. Power and ground to the integrated circuit are provided by VCC 92 and Ground 94. Test Pins 76, Data Bus 96, and Correlation Load 98 round out the remaining pins on this gate array circuit.

The invention has now been explained with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art in light of this disclosure. Therefore it is not intended that this invention be limited, except as indicated by the appended claims.