Identification System

The primary object of this invention is to provide a system for identifying an object, animal or person consisting essentially of two units, one being a passive integrated transponder (PIT) which is carried by or embedded in the thing or animal to be identified and which responds to interrogation with an identifying code, and the other unit being an interrogator-reader separate from the PIT.

Heretofore, in identification device systems, there is usually found some sort of an exciter which is associated with an interrogator which feeds a combined alternating current clock signal and power supply signal to a responder device via an inductive coupling. The responder may be implanted in an animal or on something whose identity is to be ascertained, such as a freight car. The responder produces a coded identification signal which is fed back through the inductive coupling to a detector and demodulator which produces an output signal characteristic of the particular animal or thing that is being identified.

Many coded data transmission systems have been used. In some the responder entails a resonant circuit the resonant frequency of which varies according to the encoded signal peculiar to the animal or thing being identified. In Kaplan et al. U.S. Pat. No. 3,689,885, coded information was returned from a responder to an interrogator in the form of spaced bursts of alternating current of a fixed frequency. In Beigel U.S. Pat. No. 4,333,072, for example, the responder or tag circuit produces a signal by varying the load across the inductor responsive to the encoded signal characteristic of the animal or thing being identified. All of these systems were subject to certain drawbacks: the resonant circuit systems particularly being subject to variations in resonance frequency produced by, for example, changes in temperature which, in some instances, could produce spurious variations in frequency which were difficult if not impossible to differentiate from variations produced by the encoding device. Systems wherein the code signal was represented by variations in amplitude of an oscillating circuit have the drawback that such variations in amplitude are difficult to accurately detect.

As in the cases of most of its predecessor systems, the subject transponder is supplied with a combined clock and power signal from an interrogating unit by way of inductively coupling and is implanted on the thing to be identified and detected. The transponder produces an encoded signal which is fed back through the inductive coupling to the interrogating unit, but in a different form than that incorporated in the predecessor devices. According to the invention, the clock signal derived via the inductive coupling from the interrogating unit is reduced in frequency and then caused to shift in frequency. In particular an incoming clock signal of 400 KHz is fed to a variable modulus counter followed by a divide-by-two circuit which together, in one state, divide the clock signal by eight and, in another state, divide the clock signal by ten. Thus, the output of the variable modulus counter produces an alternating current signal of either 40 KHz or 50 KHz, a shift from a first one of which frequencies to the second, generally stated, is representative of a "zero" while the opposite shift is representative of a "one". The "ones" or "zeros" are produced by the encoding device, and are returned to the interrogating device via the inductive coupling and detected. It is an easy task for the interrogator-detector to recognize a shift from a 40 KHz signal to a 50 KHz signal and vice-versa.

The foregoing represents a simplification of the encoding system. In practice, an array of logic gates is used to control the insertion of a sync word in the data-stream. This logic also creates a Manchester encoding on the datastream. The result is a serial composite signal including sync and data information.

The composite stream controls the modulus (divide ratio) of the variable modulus counter which is clocked by the input clock (400 kHz). The output of the variable modulus counter is either 80 khz or 100 khz. depending on the data value. This counter drives a divide-by-two flip flop which results in output frequencies of 40 KHz or 50 KHz which vary as a function of the data.

More specific objects will be apparent from the following specification and drawings in which:

FIG. 1 is a block diagram of the overall system;

FIG. 2 is a circuit diagram of the exciter;

FIG. 3 is a circuit diagram of the signal conditioner;

FIG. 4 is a circuit diagram of the passive integrated transponder (PIT);

FIG. 5 is a timing diagram showing the transmitted message;

FIG. 6 is a circuit diagram of the demodulator; and,

FIGS. 7A and 7B are a diagram of the control logic and encoding circuit.

FIG. 1 shows the overall system consisting of a reader/exciter 2 and the passive integrated transponder (PIT) 18.

The reader/exciter unit 2 includes three main functional units: The exciter 4, signal conditioner 6 and the demodulation and detection circuits 8. The exciter 4 consists of an AC signal source 10, followed by a power driver 12 which provides a high current, high voltage excitation signal to the interrogator coil 14 through a capacitor 16. The interrogator coil 14 the capacitor 16 are selected to resonate at the excitation signal frequency so that the voltage across the coil is much greater than the voltage output from the driver.

The signal conditioner 6 connects to the interrogator coil 14 and serves to amplify the identification signal returned from the PIT 18 while filtering out the excitation signal frequency as well as other noise and undesired signals outside of the frequency range used by the PIT signals.

The amplified output of the signal conditioner 6 is fed to the demodulation and detection unit 8 which includes a low pass filter 20 to further reduce excitation signal energy, a frequency shift keyed (FSK) demodulator 22 and a microcomputer 24. The FSK demodulator 22 is a phase-locked loop circuit configured as a tone decoder which gives a digital output as the signal from the PIT 18 shifts between two frequencies. The microcomputer 24 extracts the identification code from this digital output by observing the timing of transitions between the two logic levels. The identification code obtained by the microcomputer 24 can be transferred to a display or printer, sent over communication lines to a remote point, stored on tape, disk or other storage medium, or sent to another computer.

The PIT 18 consists of an induction coil 26 which is located such that the magnetic flux generated by the interrogator coil 14 couples energy at the exciter frequency into the PIT. This energy is converted to a DC voltage using a full-wave rectifier bridge 28 and a smoothing capacitor 30 as is commonly used in power supply circuits. This DC voltage supplies the power to the control logic and ID memory circuit 32.

The control logic 32a consists of counters and gates which sequentially read out the contents of the ID memory 32b. The logic 32a also inserts a sync word into the signal data stream to allow the reader/exciter to synchronize to the data. The excitation signal which appears on the PIT coil 26 is supplied to the control logic to provide a clock signal. The logic circuit 32a convert the serial data and sync stream into a frequency shift keyed (FSK) waveform which is connected to the PIT coil 26 through complementary current sinks to transmit the FSK identification signal. The transmitted signal is received by the interrogator coil 14 due to the mutual inductance and is amplified by the signal conditioner and detected.

In following detailed description of the system, the components of the interrogator 2, e.g., the exciter 4, the signal conditioner 6, etc., are different units which, are connected to one another through a standard connection TSI (FIG. 2) as indicated. It should be understood, however, that they may all be wired together.

In the following description of the circuits, the reference numeral prefix denotes the drawing figure in which the designated element resides. Thus, "2Cl" or "2Ll" means that "Cl" and "Ll" are in the circuit shown in FIG. 2.

A schematic diagram of the exciter 4 is shown in FIG. 2. The exciter consists of a crystal controlled oscillator 34 formed by gate 2U.sub.1 B and crystal 2X.sub.1. In this example the crystal frequency is 4 MHz. The crystal oscillator output is buffered by 2U.sub.1 C and then divided in frequency by 5 using flip flops 2U.sub.2 A, 2U.sub.2 B, 2U.sub.3 A. The output of 2U.sub.3 A, which is now at 800 KH, is divided in frequency by another factor of 2 in flip flop 2U.sub.3 B to create a square wave output at 400 KHz. This square wave output then drives a high power switch driver 36 which in turn will drive the coil which is connected to terminals 7 and 8 of connection TSI. The function of gate 2U.sub.1 A in this circuit is to allow the exciter to be remotely enabled and disabled via the enable input line from terminal TSI-5.

The high power switch driver 36 is formed by VMOS transistors 2Q.sub.1 and 2Q.sub.2. 2Q.sub.2 is switched on by a positive going signal from pin 14 of 2U.sub.3 B. This turns 2Q.sub.2 on with a low resistance to ground. When the output pin 14 is at a low logic level, 2Q.sub.2 is turned fully off. 2Q.sub.1 performs the same function being turned on between a positive DC voltage and off in a high impedance state. Transistors 2Q.sub.3 and 2Q.sub.4 perform a voltage translation required to take the output of 2UlD, pin 11, and convert it to the required voltage levels to drive the gate of 2Q.sub.1. In operation transistor 2Q.sub.2 is on when transistor 2Q.sub.1 is off and visa versa. This timing of 2Q.sub.1 and 2Q.sub.2 sets up an alternating voltage which is impressed upon the coil via terminals TSI-7 and TSI-8 though capacitors 2C.sub.4 and 2C.sub.5. Resistors 2R.sub.4 through 2R.sub.7 and 2R.sub.13 through 2R.sub.16 serve to reduce the dissipation of 2Q.sub.1 and 2Q.sub.2 during the switching transitions and also define the Q of the circuit formed by 2C.sub.4 and 2C.sub.5 and the coil. The voltage across the coil is much greater than the DC voltage at the drain of 2Q.sub.1. This is due to the resonance of 2C.sub.4 and 2C.sub.5 with the coil inductance, at the excitation frequency, in this case 400 KHz. The connections to and from exciter 4 are generally as indicated by the legends. TP 1 and TP 2 are test points. Enable connections TSI-5 and TSI-6 need not be used. They do, however, provide for remote control of the exciter. Open circuits, at these points, enable the exciter. TSI-9 and TSI-10 connect to the signal conditioner.

The signal conditioner 6 is shown in FIG. 3 and consists of a conventional power supply 38 formed by transformer 3T.sub.1, diodes 3CR.sub.3 through 3CR.sub.6, capacitors 3C.sub.15 through C.sub.18 and voltage regulators 3VR.sub.1 and 3VR.sub.2. This power supply provides a positive 15 volt and negative 15 volt DC output to power the signal conditioning circuit. The signal conditioning circuit consists of a bandpass filter 40 tuned to the frequencies used by the PIT 18. The bandpass filter 40 consists of inductances 3L.sub.1, 3L.sub.2, 3L.sub.3 and capacitors 3C.sub.1 and 3C.sub.2. In this case the PIT frequency is shifted between 40 and 50 kilohertz. Resistor 3R.sub.1 sets the bandwidth of the filter at 10 kilohertz. In addition 3L.sub.1 through 3L.sub.3 appear as a high impedance to the excitation signal of 400 kilohertz; and the series combination of 3L.sub.4 and 3C.sub.1 and 3C.sub.2 serve as a very low impedance to the 400 kilohertz excitation signal, passing it to ground. The identification signal from the PIT 18 is supplied at the SIGNAL and SIG RTN terminals. It is supplied to amplifier 3U.sub.1, which is is a unity gain amplifier which acts as a buffer to drive a bandpass filter 42 formed by 3C.sub.6, 3L.sub.5, 3L.sub.6 and 3C.sub.7 passing signals between 40 and 50 kilohertz. The output of filter 42 is amplified in 3U.sub.2 and 3U.sub.3 to create the filtered amplified output of the signal conditioner circuit, as indicated. The connections for the signal conditioner are generally as indicated in that "SIGNAL" and "SIGRTN" connect to the similarly marked exciter connections TSI-9 and TSI-10, respectively (FIG. 2), "AC-10" and "AC-9" are connections to a power line, 110 volts, 60 HZ, "+15 v" is a positive voltage output and connects to TSI-3 of exciter 4, and "GROUND" 6 is a return for the supply voltages and connects to exciter TSI-4. The "-15 v" connection 5 is not presently used. TPI is a test point. The output of the conditioning circuit 6 is the input to the demodulator circuit (FIG. 6).

The PIT, FIG. 4, consists of an inductance winding 26, a full-wave rectifier bridge 46, programmable matrix array 4U2 and the control logic 4U1 necessary to provide a frequency shift keyed modulated waveform serially encoded according to the data programmed into the matrix 4U2. The circuit is powered by an alternating current excitation signal resulting from the mutual inductance between the interrogator coil 14 and the PIT winding 26. This is converted to a DC voltage by the full-wave rectifier bridge formed by 4CR.sub.1 4CR.sub.2, 4CR.sub.3 and 4CR.sub.4 and the ripple filtering capacitor 4C.sub.1. This filtered DC level provides the power to the control logic circuits. The zener diode 4VR1 protects the circuit from excessive DC voltage. The control logic 4U1 provides the signals to scan the matrix array 4U2 convert the data to serial format and insert synchronization information, and generate an FSK modulated output. The array 4U2 of FIG. 4 is a fusible link diode matrix model HM-0186 manufactured by Harris Semiconductor, into which the ID data characterizing the particular PIT transponder is programmed prior to incorporation of 4U2 into the circuit. The array is scanned at a rate determined by the AC excitation signal which is low pass filtered by 4R.sub.3 and 4C.sub.2 and then injected into the circuit. Within 4U.sub.1 (as detailed below in FIG. 7) the clock signal is divided in frequency by 100 and then further divided by eight and decoded to provide eight row select outputs to scan the array 4U2. A divide by six counter with associated gating multiplexes the five column outputs of the array into a serial format. Synchronization information is inserted during one phase of the divide by six operation. The resulting serial composite waveform controls a variable modulus counter (divide by 4/divide by 5) which is clocked at a rate set derived from the excitation signal to produce an FSK modulated waveform. This waveform is divided by 2 and connected back to the AC excitation input via open drain complementary drivers and current limiting resistors 4R.sub.1 and 4R.sub.2.

FIGS. 7A and 7B detail the circuit of the PIT. The incoming 400 KHz clock signal is fed through a series 100 of flip flop units, being first divided by two, then by five, again by five, again by two and finally again by eight at 104. The output of this series of flip flops, then at 500 hz, is used to generate eight row strobe signals via NAND gates DM to scan the array 4U2 at connections ROW 1-ROW 8. The five column outputs of array 4U2 are connected to the inputs col 1-col 5 of a column select gate array 102. While these inputs are shown as being connected to positive voltage supply +v by 100 k resistors, in actual practice the actual devices are FETs; the net result being the same as if resistors were used to bias the incoming circuits to the column select gates.

Reverting momentarily to the NAND gates DM, the outputs of the divide by 8 counter 104 are decoded by eight, three input NAND gates DM to generate the eight row strobes. These row strobes connect to the row inputs of the diode matrix 4U2. During the operation the row strobes are sequentially set to a "low" output. With a 400 KHz clock input each row output is low for 250 milliseconds so that it takes 2 milliseconds for all the row inputs to sequence through the low state. The process is repeated every 2 milliseconds during interrogation.

The col 1-col 5 signals and the outputs of further divide by six counter 106 provide inputs to five, four-input NAND gates of the column select matrix 102. A given column input is enabled for the time it takes to strobe all eight row outputs (2 milliseconds in the present case). Then the next column is enabled and so on. When the counter 106 is in the 0-0-0 state, no column inputs are enabled, providing a 2 ms "slot" in which and the sync word is inserted.

An array LG of logic gates is used to control the insertion of a sync word in the data stream. This logic also applies a Manchester encoding techniques to data stream. The result is a serial composite signal including sync and data information which is fed to the variable modulus counter VMC as a composite stream. The composite stream controls the modulus (divide ratio) of a variable modulus counter. The variable modulus counter comprising flip flops 108a, 108b, 108c is clocked by the input clock (400 KHZ). The output of this counter is either 80 KHZ or 100 KHZ depending on the data value. This counter drives a divide-by-2 (flip-flop 110) which results in output frequencies of 40 KHZ or 50 KHZ varying as a function of the data stored in the array 4U2.

The output drivers of the divide by two counter 110 are open-drain transistors which are connected through resistors to the transponder coil (PIT coil 26). Thus, when a driver is "on" it "sinks" current from the coil. Since the drivers are driven out of phase, yielding signals FSK, FSK; and are connected to opposite sides of the coil, they create an alternating current at the coil with a frequency of 40 KHz or 50 KHz.

An exemplary representation of the serial digital data stream which controls the variable modulus counter is shown in FIG. 5. Reading down, FIG. 5 shows the message, that is, the data transmitted, the signal frequency, the spacing of the bit periods, the distinction between the sync or preamble portions of the signal and data, and the Manchester encoding scheme used. The data stream consists of a total of 48 bit periods. Data is encoded using the Manchester encoding technique commonly employed in serial data transmissions. In the Manchester technique, data values are represented by transitions from a low to high level or high to low level in the middle of the bit period. In the present representation, a logical zero data bit is represented by a low to high transition in the middle of the bit period, and a logical one data bit is represented by a transition from high to low in the middle of the bit period. Synchronization ("sync") information is contained in the first 8 bit periods of the data stream. The sync consists of 4 bit periods of preamble information followed by a constant low level for one and a half bit periods, a constant high level for one and a half bit periods and a zero data bit. The eight sync-bit periods are followed by 40 bit periods containing the actual ID data. Exemplary data corresponding to "11001 . . . " is shown. The circuit runs continuously during interrogation such that an endless stream of sync followed by data appears.

The demodulation circuit is shown in FIG. 6. Its input is the output of the signal conditioner (FIG. 3). The demodulation circuit shown in, FIG. 6, includes a low pass filter 48 which functions to further reduce the undesired excitation signal frequencies, followed by a tone decoder 6U2 which tracks the excursions of the frequency shift keyed waveform output from the passive integrated transponder. 6U2 is an FSK demodulator manufactured by EXAR Corporation, model XR-2211. The low pass filter is a three pole unity gain design formed by 6U.sub.1 in combination with 6R.sub.2 through 6R.sub.4 and 6C.sub.4 through 6C.sub.6. The output of this low pass filter drives the tone decoder 6U2. The tone decoder consists of a voltage controlled oscillator and a phase detector arranged such that the phase detector output provides a control voltage to the voltage controlled oscillator to track the frequency excursions of the input signal. The free-running frequency of the voltage controlled oscillator is set by 6C.sub.12 and 6R.sub.6 plus 6R.sub.7. The phase detector output, signal .phi. DET, at pin 11, provides a control voltage to the oscillator through 6R.sub.8 so that the oscillator tracks the frequency of the incoming signal and is phase locked to it. The output .phi. DET of the phase detector is also filtered by 6C.sub.13, 6R.sub.9 and 6C.sub.14 and input at comp to a comparator circuit. The comparator threshold is in the center of the tracking range between the two frequencies. Therefore, as the frequency shifts between its lower value and its upper value, the DATA output signal of the comparator at pin 7 of 6U2 alternates between two logic levels. Thus, 6U2 demodulates the FSK waveform presented as INPUT at pin 2 into a digital waveform which is OUTPUT at pin 7. This digital waveform may be processed by the microcomputer using the sync and timing information within the waveform to actually decode the final identification number and use it as desired. Tone decoder 6U2 provides output signals as follows:

"Carrier Detect A" indicates that a carrier signal from the transponder 18 is present.

Carrier Detect B is the same as "Carrier Detect A", but with opposite logic sense.

"Demod Data" supplies the demodulated identification signal.