Phase and Period Synchronization for a Slave Disk Drive

This invention relates to storage units and to a method of synchronizing a plurality of individual storage units joined in parallel.

A conventional electronic computer system is equipped with a plurality of magnetic disk devices as external storage units for storing large amounts of data. In such a system, it is important to transfer large amounts of data for video processing among the individual disk devices at high speeds. However, the data transfer speed of the individual magnetic disk devices is limited by the speed of revolution of the magnetic disk and the like, and is difficult to increase.

Previous systems proposed a technique of transferring data simultaneously to the individual disk devices by synchronously driving the spindle motors that drive the disks. According to this technique, it is important for the spindle motors of the individual disk devices to have the same rotational phase. For instance, Japanese Patent Laid-Open No. 160877/1986 discloses a technique which finds the difference between the rotational phase of a reference spindle motor and the rotational phase of a spindle motor that rotates following thereto. This system then transmits a compensation signal which corresponds to the rotational phase difference of these motors to the revolution control circuit of the spindle motor of the follow-up side to drive each motor in synchronism.

According to the above prior art, each magnetic disk device has a reference revolution control circuit which includes a reference signal generating circuit such as a quartz oscillator that maintains the speed of revolution constant. When the spindle motors of the reference side and the follow-up side have an equal speed of revolution, the synchronous operation can be carried out sufficiently. However, the inventors have found the problem that it is difficult to drive the individual spindle motors at perfectly the same speed and the problem that when there is a difference in the speed of revolution of these spindle motors at the start of synchronous operation, a steady phase difference occurs depending upon the speed of revolution, making it impossible to achieve perfect synchronous operation.

When data is transferred in parallel from the individual magnetic disks to a higher-rank apparatus such as a host computer, it becomes necessary to temporarily store the data in a buffer memory of the data transfer circuit to absorb the difference of arrival time of the transferred data in order to bring the transfer of data into synchronism. The inventors, however, have found the fact that when the plurality of spindle motors have large difference in the revolution, their speed of buffer memory must have an increased capacity.

A first object of the present invention is to provide a synchronized motor control system which is capable of decreasing the steady difference in the rotational phases that occur during synchronous operation.

A second object of the present invention is to provide a synchronized motor control system that is capable of decreasing the capacity of the buffer memory that is necessary for transferring data in parallel during the synchronous operation.

In order to achieve the above objects, features of the present invention resides in the following constitution.

In a system equipped with a plurality of magnetic disk devices, one magnetic disk generates reference signals for driving other disk in synchronism (hereinafter, the magnetic disk that generates the reference signals is referred to as a "master unit"). Other magnetic disks (hereinafter referred to as "slave units") are driven in synchronism following the reference signals generated by the master unit.

According to the present invention, the rotational phase and frequency of the spindle motors of the master and slave units are compared with each other and are brought into synchronism in order to synchronize their revolutions. The reference signals for maintaining the synchronous revolution are servo signals such as index signals recorded on the magnetic disks of the master unit and the slave units. The index signals obtained from the master and slave units are compared with each other, and the speed of revolution of the slave units is so compensated that the phase difference becomes zero. Furthermore, in order to compensate for a steady phase difference arising from the difference of period of revolution of the spindle motors between the master side and the slave side, the speed of revolution of the slave units is adjusted using a compensation value which is proportional to the difference in the number of revolution specific to the spindle motors.

The synchronized operation is carried out as described below. Prior to operating a plurality of magnetic disks in synchronism, the spindle motors of the magnetic disk devices are independently rotated until steady revolutions are obtained. Each magnetic disk has a revolution control circuit. In this case, the master unit produces a master index signal that serves as a reference signal for rotating the slave-side disks in synchronism based upon the index signals written on a surface of the magnetic disk. Similarly, each slave unit produces a slave index signal that serves as a reference for bringing the phase into agreement with the master index signal based on the index signals written on a surface of the disk. As the speed of revolution reaches nearly the steady state, the revolution control circuit of the slave unit determines the difference in period between the master index signal and the slave index signal, and the difference in period is stored in the buffer. Then, the plurality of magnetic disk devices have their rotation interlocked with each other. At this moment, the difference in period stored in the buffer is added as a compensation value to the revolution control circuit of the slave side. Then, the index signals from the master side are successively compared with the index signals from the slave side, and the speed of revolution of the slave unit is adjusted so that the difference in phase becomes zero.

The present invention will be more apparent from the following detailed description, when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram illustrating the constitution of storage units according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating the whole constitution of a synchronized motor control system for storage units according to the embodiment of the present invention;

FIGS. 3a and 3b are diagrams illustrating a relationship between the master and slave index signals in FIG. 1;

FIGS. 3c and 3d are diagrams showing output signals of a period difference detector and of a phase comparator of FIG. 1;

FIGS. 4a to 4d are diagrams showing a period difference signal V.sub..theta. and a phase difference signal V.sub..phi. in FIG. 1;

FIG. 5 is a block diagram showing a synchronized motor control system for disk drives, according to another embodiment of the present invention; and

FIG. 6 is a flow chart illustrating the operation of the synchronized motor control system for the disk drives of FIG. 5.

First, an outline of the synchronized motor control system for storage units of the embodiment will be described in conjunction with FIGS. 1 and 2.

The synchronized motor control system for storage units of the embodiment is constituted by a master storage unit 100 that serves as a reference in the synchronized operation, and one or more slave storage units 200 which are connected to a higher-rank data transfer control unit 400 via data lines 300.

The data transfer control unit 400 is connected, via data line 500, to a higher-rank unit such as a channel unit of an electronic computer system and a central processing unit that are not diagramed. The data transfer control unit 400 has a plurality of storage units 100, 200 and a buffer memory 400a which temporarily stores the data that is to be transferred to the higher-rank units. The buffer memory 400a adjusts variations of the transfer times of the data transferred in parallel from the plurality of storage units 100, 200 to the higher-rank unit. Further, the data transfer control unit 400 gives a SYNC-ON signal 600 to the slave storage units 200 to instruct synchronous operation.

The storage unit 100 that serves as a reference in the synchronous operation has a spindle motor 5 that drives a magnetic disk (not shown), a frequency generator 7 that generates signals of a frequency corresponding to the number of revolutions of the spindle motor 5, a reference frequency generator 1 that produces reference signals to determine the number of revolutions of the spindle motor, a velocity error detector 2 that produces a control signal Vv proportional to the difference between an output of the reference frequency generator 1 and an output of the frequency generator 7, and a motor driver 4 that feeds a power source corresponding to the control signal Vv to the spindle motor 5. Using a feedback loop control system constituted by the velocity error detector 2, motor driver 4, spindle motor 5, and frequency generator 7, the number of revolutions per second of the spindle motor 5 is controlled to have the same frequency as a reference signal of reference frequency generator 1. The spindle motor 5 is connected to an index pulse generator 6 that generates master index pulses (MIDX). The index pulse generator 6 generates a pulse for each revolution of the spindle motor 5, i.e., generates master index pulses (MIDX) of a period T.sub.1 that corresponds to an actual number of revolutions of the spindle motor 5. The master index pulses (MIDX) are also sent to the slave storage units 200.

The slave storage unit 200 is fundamentally as the master storage unit 100, i.e., has a spindle motor 5a, a frequency generator 7a, a reference frequency generator 1a, a velocity error detector 2a, a motor driver 4a, and an index pulse generator 6a. The spindle motor 5a is connected to index pulse generator 6a that generates slave index pulses (SIDX). The index pulse generator 6a generates a pulse for each revolution of spindle motor 5a, i.e., generates slave index pulses of a period T.sub.2 that corresponds to an actual number of revolutions of the spindle motor. The slave index pulses (SIDX) are sent to a phase comparator 8a and a period difference detector 9a that will be described later.

The slave storage unit 200 has a phase comparator 8a that detects the difference of rotational phase between the spindle motors 5 and 5a of the master and slave storage units 100 and 200. As shown in FIGS. 3b, and 3d the phase comparator 8a in the slave storage unit 200 receives the master index pulse (MIDX) and the slave index pulse (SIDX), and produces a phase difference signal V.sub..phi. that corresponds to the phase difference .phi. generated by these signals. The phase difference signal V.sub..phi. is given, via a switch 12a, to an adder 3a that is inserted between velocity error detector 2a and motor driver 4a. Through adder 3a, the phase difference signal V.sub..phi. is fed back to the control system, and spindle motor 5a is controlled so as to reduce the difference of rotational phase between the master index pulse (MIDX) and the slave index pulse (SIDX). At this moment, the switch 12a is instructed to be opened or closed by a SYNC-ON signal 600 given from a higher-rank unit, and is closed during the synchronous operation.

The slave storage unit 200 is further provided with a period difference detector 9a that produces a period difference signal V.sub..theta. which corresponds to a period difference T.sub.3 between the master index pulse (MIDX) and the slave index pulse (SIDX), a buffer 10a which stores and holds the period difference signal V.sub..theta., switches 11a and 14a, and an inverter 13a. As shown in FIG. 3c, the period difference signal V.sub..theta. corresponds to the difference of number of revolutions between the spindle motors 5 and 5a. The period difference signal V.sub..theta., stored by the buffer 10a, transmitted, via switch 11a, to the adder 3a inserted between the velocity error detector 2a and the motor driver 4a. The switch 11a is closed when a SYNC-ON signal 600 assumes the high level, and the period difference signal V.sub..theta., stored by the buffer 10a, is transmitted to the feedback loop control system as a compensation value during the synchronous operation. Buffer 10a includes a switch 14a and the stored value is updated every time the period difference signal V.sub..theta. is input when the SYNC-ON signal 600 assumes a low level that closes the switch 14a. However, when the SYNC-ON signal 600 assumes a high level that opens the switch 14a and closes the switch 11a the buffer 10a is not updated upon receiving the newly input period difference signal V.sub..theta., but produces the period difference signal V.sub..theta. that has been held as a compensation value.

The operation of an embodiment of the invention will now be described.

The reference frequency generators 1 and 1a in the storage units 100 and 200 have an equal reference frequency to rotate the spindle motors 5 and 5a in synchronism with each other.

To obtain a synchronous rotation, first, the spindle motors 5 and 5a in the storage units 100 and 200 are independently rotated until they reach steady speed. During this time, the SYNC-ON signal 600 is assuming a low level (asynchronous state), switches 11a and 12a are opened, and switch 14a is closed. The frequencies of the reference frequency generators 1 and 1a in the storage units 100 and 200 are set equaly to rotate the spindle motors 5 and 5a in synchronism. However, the numbers of revolutions of the two spindle motors 5 and 5a are not in perfect agreement with each other, even during the steady-speed operation, and there is a difference in the number of revolutions, as illustrated in FIG. 3a. This is attributed, for example, to a slight difference in the oscillation frequencies of quartz oscillators included in the reference frequency generators 1 and 1a, and variations of characteristics of circuit components in the reference frequency generators 1 and 1a.

When the spindle motor 5 of the master storage unit 100 is started under this condition, the frequency generator 7 generates signals of a frequency proportional to the number of revolutions of the spindle motor 5. These signals are input to the velocity error detector 2 where they are compared with the outputs of the reference frequency generator 1, and a control signal Vv which is proportional to the difference of these signals is transmitted to the motor driver 4 which supplies a drive current proportional to the control signal Vv to the spindle motor 5. Owing to the feedback control of speed as described above, the spindle motor 5 in the storage unit 100 revolves at a number of revolutions substantially equal to the number of revolutions set by the reference frequency generator 1. The index pulse generator 6 generates master index pulses (MIDX) of a period T.sub.1 at a rate of one pulse per revolution of the spindle motor 5, and the pulses are received by period difference detector 9a and the phase comparator 8a.

The slave storage unit 200 operates in the same manner as that of the master unit because the switches 11a and 12a are open when the SYNC-ON signal 600 assumes 1a low level (asynchronous state), and the spindle motor 5a rotates at a frequency substantially equal to the frequency set by the reference frequency generator 1a. The index pulse generator 6a generates slave index pulses (SIDX) of a period T.sub.2, at a rate of one pulse per revolution of spindle motor 5a, and the slave index pulses are input by period difference detector 9a and phase comparator 8a. The period difference detector 9a produces a period difference signal V.sub..theta. that corresponds to the period difference T.sub.3 (=T.sub.1 -T.sub.2) between the master index pulse (MIDX) and the slave index pulse (SIDX) as illustrated in FIG. 3c. When the SYNC-ON signal 600 has a low level (asynchronous state), switch 11a remains open and the period difference signal V.sub..theta. is sent to the buffer 10a where it is stored. The buffer 10a stores a value of the period difference signal V.sub..theta. that is successively sent thereto while updated by a newly sent signal. The phase comparator 8a receives the master index pulse (MIDX) and the slave index pulse (SIDX), and produces a phase difference signal V.sub..phi. that corresponds to the difference of phases of these signals. However, signal V.sub.100 is not sent to adder 3a when the SYNC-ON signal 600 has the low level (asynchronous state) because switch 12a remains open.

After the frequency of the spindle motors 5 and 5a of the master and slave sides are stabilized, the synchronous operation is started with the SYNC-ON signal 600 going to a high level. When the SYNC-ON signal 600 assumes a high level (synchronous state), switches 11a and 12a are closed, and switch 14a is opened. The buffer 10a is no longer updated to store the newly input period difference signal V.sub..theta. and sends the old period difference signal V.sub..theta. that has been held previously stored at that moment as a compensation value to the adder 3a. Further, since switch 12a is closed, the phase difference signal V.sub..phi. is sent to adder 3a. Then, the period difference signal V.sub..theta. and the phase difference signal V.sub..phi. are applied to the speed control feedback system of the slave side. The spindle motor 5a is controlled by the period difference signal V.sub..theta. so that the difference in the frequency of the spindle motors 5 and 5a during the steady operation is reduced. Motor 5 a is further controlled by the phase difference signal V.sub..phi. so as to have the same phase as that of the spindle motor 5.

The principle of controlling the speed of the spindle motor 5a of the slave side using the period difference signal V.sub..theta. and the phase difference signal V.sub..phi. will now be described in conjunction with FIGS. 4a to 4d which illustrate examples of controlling when the steady revolution speeds of the spindle motors 5 and 5a of the master side and the slave side are slightly different.

FIG. 4a shows a switching timing of the SYNC-ON signal 600. When the revolutions of the spindle motors 5 and 5a are stabilized, the SYNC-ON signal 600 changes from a low level to a high level, and the synchronous operation is started. Then, the control signal Vva produced from the velocity error detector 2a, changes as shown in FIG. 4b wherein the ordinate represents a voltage of control signal Vva. After the synchronous operation is started, the period difference signal V.sub..theta. and the phase difference signal V.sub..phi. are added to the adder 3a, and the velocity error detector 2a produces an error signal having a magnitude that corresponds to the difference between the frequency of reference frequency generator 1a and the frequency of the spindle motor generated by 7a.

In FIG. 4c, the output of phase difference signal V.sub..phi. is illustrated. When the synchronous operation is started, switch 12a is closed and the phase difference signal V.sub..phi. is applied to adder 3a. If it is now assumed that the period difference signal V.sub..theta. is not given to the adder 3a, there exists a difference in the number of steady revolutions between the two spindle motors 5 and 5a. Therefore, even if it is attempted to maintain synchronism of revolutions using index pulses (MIDX, SIDX) that are generated at a rate of one pulse per revolution of the spindle motors 5 and 5a, the difference readily develops in the revolutions immediately after the accomplishment of synchronism since the spindle motors 5 and 5a have different numbers of steady revolutions. That is, since the feedback control is carried out with repetition of the accomplishment of synchronism and out-of-phase, a steady phase difference exists that corresponds to a steady period difference T.sub.3 as indicated by a dotted line in FIG. 4c.

In this embodiment, as shown in FIG. 4d, the period difference signal V.sub..theta. is added to the adder 3a, to compensate for the difference in the number of steady revolutions between the two spindle motors 5 and 5a. The period difference signal V.sub..theta. is a compensation value which usually has a constant value proportional to the number of steady revolutions of the spindle motors 5, 5a measured when the SYNC-ON signal 600 is low (asynchronous state). With the period difference signal V.sub..theta. being applied in advance to the adder 3a as a compensation value for compensating the difference in the numbers of steady revolutions of the spindle motors 5 and 5a, as described above, it is allowed to compensate the phase using the phase difference signal V.sub..phi., preventing the generation of a steady state phase difference.

FIG. 5 is a block diagram of a synchronized motor control system for disk drives of an alternative embodiment of the present invention. According to this embodiment, the slave storage unit 200a is provided with a compensation circuit 15a which produces a compensation value corresponding to the period difference T.sub.3 instead of the provision of the period difference detector, switch 14a and buffer 10a. The period difference signal V.sub..theta. corresponding to the period difference T.sub.3 is produced when the SYNC-ON signal 600 assumes the high level. The operation will now be described in detail with reference to FIG. 6.

FIG. 6 is a flow chart which illustrates the operation of the synchronized motor control system for disk drives of FIG. 5. First, the SYNC-ON signal is set at the low level (step 61), and the spindle motors 5 and 5a are driven asynchronously (step 62). Then, it is detected whether the frequency of revolutions of the spindle motors 5 and 5a is stable at a steady value, for example, 3600 rpm (step 63). When a steady revolution is obtained, the compensation circuit 15a measures the rotational period difference T.sub.3 of the spindle motors 5 and 5a (step 64). Then, the compensation circuit 15a calculates a period difference signal V.sub..theta. based on the rotational period difference T.sub.3 (step 65). Instead of the method of the above calculation, the measurement may be carried out with a timer that is not shown to affect the calculation by a microprocessor. It is further allowable to store the compensation values corresponding to the rotational period difference T.sub.3 as a table in the ROM or the like in advance to find a value with reference to this table. Next, the SYNC-ON signal is set at the high level (step 66), and the period difference signal V.sub..theta. that is found is applied to the feedback system via the adder 3a (step 67). The operation is the same as that of FIG. 1 and will not be explained.

In the foregoing was described the invention accomplished by the present inventors by way of embodiments. It should, however, be noted that the present invention is in no way limited to the above-mentioned embodiments only but can be modified in a variety of other ways without departing from the gist and scope of the invention.

For instance, it is also allowable to arbitrarily set the value of period difference signal V.sub..theta. and to arbitrarily set the period difference between the slave storage unit and the master storage unit. This makes it possible to shift the phase by a time necessary for switching the operation for sending/ receiving the data to/from a plurality of storage units, in order to reduce the revolution wait time for the switching operation.