Semiconductor Memory Device Having Flash Write Function

1. Field of the Invention

The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a flash write function.

In a random access memory incorporated in a system, all bit contents are reset to "0" or "1", e.g., upon initialization or the like. In general, bits are sequentially designated and preset data is written in each bit to perform a reset operation. In this method, however, an address must be designated for each bit, and a reset time is undesirably long. In particular, this problem is serious in a RAM having a large capacity, and therefore, a flash write system for writing preset data in units of words has been proposed.

2. Description of the Related Art

The following cross references are related to the flash write system:

(i) U.S. Pat. No. 4,680,734, filed on Aug. 5, 1985, published on Jul. 14, 1987;

(ii) U.S. Pat. No. 4,587,629, filed on Dec. 30, 1983, and published on May 6, 1986;

(iii) Japanese Unexamined Patent. Publication No. 63 -106989, filed on Oct. 24, 1986 and published on May 12, 1988.

In a conventional semiconductor memory device having a flash write function, for example, a given word line is designated in response to an external address signal, and preset data is simultaneously written in a plurality of memory bits connected to the given word line. In such a device, as a memory bit count per word in, e.g., a 1-Mbit (=512 cycles x 2048 bits) dynamic RAM is 2048, a reset time is given as 512 cycles, and as a result, the reset time can be shortened.

In such a conventional semiconductor memory device, however, word lines are sequentially selected in response to an external address signal, and therefore, a flash write address generator must be arranged outside the semiconductor memory device, and the external circuit is undesirably complicated.

Therefore, an object of the present invention is to provide a semiconductor memory device which can perform a flash write operation without using an external address signal.

To achieve the above object, according to the present invention, there is provided a semiconductor memory device comprising: a plurality of word lines and bit lines; a plurality of memory cells connected between the word lines and the bit lines; a flash write mode designating unit for designating a flash write mode in accordance with external control signals; an internal address generating unit, operatively connected to the flash write mode designating unit and driven during a flash write mode, for sequentially generating internal address signals; a word-line selecting unit, operatively connected to the internal address generating unit, for sequentially selecting the word lines in accordance with the internal word address signals from the internal address generating unit; a preset data generating unit, for generating preset data; and a write unit, operatively connected to the preset data generating unit and driven during the flash write mode, for writing data from the preset data generating unit into all memory cells connected to the word line selected by the word-line selecting unit.

In the above-described semiconductor memory device, the unit is a control unit having input terminals for receiving the external control signals and having an output terminal for providing a flash write mode signal when the control signals are in a predetermined state. The address generating unit has an input terminal for receiving the flash write mode signal and an output terminal for providing the word address signals when the flash write mode signal is applied to the input terminal of the address generating unit.

In the above-described semiconductor memory device, the control unit has another output terminal for providing a refresh mode signal when the control signals are in another predetermined state, and the internal address generating unit has another input terminal for receiving the refresh mode signal. The output terminal of the internal address generating unit provides the address signal when the refresh mode signal is applied to the other input terminal of the address generating unit.

The semiconductor memory further comprises: an address input buffer unit for receiving external address signals; and an address switching unit for switching the output between the external address signals from the address input buffer unit and the internal address signals from the internal address generating unit.

The control unit has discriminating unit for discriminating whether the access mode is an external address access mode or an internal address access mode based on the external control signals; whereby, when the control unit discriminates that the access mode is the internal address access mode, the address switching unit selects the internal address signals from the internal address generating unit as the address signals for accessing the memory cells, and when the control unit discriminates that the access mode is the external access mode, the address switching unit selects the external address signals from the address input buffer unit as the address signals for accessing the memory cells.

In the above-described semiconductor memory device, the control unit has an, input for receiving a column address strobe signal and has, an input for receiving a row address strobe signal. The flash write mode signal or the refresh mode signal is generated in the internal access mode in which the column address strobe signal and the row address strobe signal have a predetermined relationship. The external access mode is that in which the column address strobe signal and the row address strobe signal have a different predetermined relationship.

In the above-mentioned semiconductor memory device, the control unit comprises a first flip flop for outputting the refresh mode signal when the column address strobe signal and the row address strobe signal have the predetermined relationship and when the flash write control signal is at a first level, and comprises a second flip flop for outputting the flash write mode signal when the column address strobe signal and the row address strobe signal have the predetermined relationship and when the flash control signal is at a second level different from the first level.

According to another aspect of the present invention, the address switching unit comprises: an OR gate circuit having a first input for receiving the refresh mode signal and a second input for receiving the flash write mode signal; and a switching gate circuit for outputting the internal address signal or the external address signal in response to the output signal of the OR gate circuit.

In the above-described semiconductor memory device, the address switching unit further comprises a gate circuit for receiving an external flash write control signal and the output signal from the OR gate circuit, the output of the gate circuit being connected to the input of the switching gate circuit, whereby when the external flash write control signal is at a predetermined level, the switching gate circuit selects the external address signals to be output regardless of the levels of the refresh mode signal or the flash write mode signal.

According to still another aspect of the present invention, the address switching unit comprises: an OR gate circuit for receiving the refresh mode signal or the flash write mode signal; a first NAND gate for receiving the output of the OR gate and the internal word address signals; a first NAND gate circuit for receiving the output signal from the OR gate circuit and the internal address signal; a second NAND gate circuit for receiving an inverted signal of the output signal from the OR gate circuit and the external address signal; and a third NAND gate circuit for outputting one of the output signals from the first NAND gate circuit or the second NAND gate circuit.

According to a still further aspect of the present invention, the address switching unit comprises: an OR gate circuit for receiving the refresh mode signal or the flash write mode signal; a gate circuit having a first input connected to the output of the OR gate circuit and a second input for receiving an external flash write control signal; a first NAND gate for receiving the output of the gate circuit and the internal word address signals; a second NAND gate circuit for receiving an inverted signal of the output signal from the gate circuit and the external address signal; and a third NAND gate circuit for outputting one of the output signals from the first NAND gate circuit or the second NAND gate circuit.

According to a further aspect of the present invention, the write unit comprises a column decoder for selecting all of the bit lines when the flash write mode signal is applied to the column decoder, whereby the preset data is written into the memory cells connected between the selected word line and all of the bit lines.

In the above-described semiconductor memory device, the write unit further comprises an input/output gate circuit for passing the preset data to the memory cells, and a data switching unit for selecting the preset data from the preset data generating unit when the flash write mode signal is applied to the data switching unit, and for selecting usual write data when the flash write mode signal is not applied to the data switching unit.

According to a still further aspect of the present invention, the write unit comprises: flash write transistors each connected between each of the bit lines and ground, and a switching unit for selecting the preset data from the preset data generating unit to be written into the flash write transistors when the flash write mode signal is applied to the switching unit, and for selecting usual data to be written into the memory cells when the flash write signal is not applied to the switching unit.

According to another aspect of the present invention, the write unit comprises: a bit line control circuit connected to the bit lines, including; first transistors which are turned ON in response to a first clock signal for connecting the bit lines to a 1/2 V.sub.cc power source; second transistors which are turned ON in response to a second clock signal for connecting the bit lines to a V.sub.cc power source; and third transistors which are turned on in response to a third clock signal for connecting the bit lines to a V.sub.ss power source; whereby, in a reset mode, the bit lines are reset to the 1/2 V.sub.cc level in response to the first clock signal, and in a flash write mode after the reset mode, the bit lines are reset at the V.sub.cc or V.sub.ss level in response to the second or third clock signal. According to the present invention, when control signals are externally input, a word address signal is generated inside the device and preset data is written in a plurality of memory cells connected to a word line selected in response to the word address signal. Therefore, a flash write address generator is not required for an external circuit, and thus the external circuit is simplified.

FIG. 1 to 7 are views showing a semiconductor memory device according to a first embodiment of the present invention, in which:

FIG. 1 is a block diagram for explaining a principle of the first embodiment,

FIG. 2 is a block diagram showing the entire arrangement of the semiconductor memory device;

FIG. 3 is a timing chart related to a refresh mode signal S.sub.RF ;

FIG. 4 is a timing chart related to a flash write mode signal S.sub.FW ;

FIG. 5 is a circuit diagram showing an arrangement of a main part of a controller;

FIG. 6 is a circuit diagram showing an arrangement of an address switching circuit; and

FIG. 7 is a circuit diagram showing another arrangement of the address switching circuit;

FIGS. 8 and 9 are circuit diagrams showing a semiconductor memory device according to a second embodiment of the present invention, in which;

FIG. 8. is a circuit diagram showing an arrangement of a main part, and

FIG. 9 is a circuit diagram showing an arrangement of a sense amplifier; and

FIG. 10 is a circuit diagram showing an arrangement of a main part of a semiconductor memory device according to a third embodiment of the present invention.

The present invention will be described hereinafter with reference to the accompanying drawings.

FIGS. 1 to 7 are views showing a semiconductor memory device according to an embodiment of the present invention. In FIGS. 1 to 7, the present invention is applied, as an example, to a dynamic random access memory (RAM).

FIG. 1 is a block diagram of an arrangement for explaining a principle of the first embodiment.

In FIG. 1, 2 denotes a control circuit for receiving a row address strobe signal RAS, a column address strobe signal CAS, and a flash write control signal FLW for effecting a flash write mode control; 3 is a row address input buffer for amplifying an external address signal A0-A9; 13 is an address generating circuit for generating an internal address; 4 is an address switching circuit for switching between the external address and the internal address in response to a control signal from the control circuit 2; and 5 is a row decoder.

Note that the internal address generated by this address generating circuit 13 is used, according to this embodiment, for the refresh operation and for the flash write operation. In contrast, in a conventional RAM, the internal address is used only for the refresh operation, and the address for the flash write operation is supplied from an external unit.

With the arrangement shown in FIG. 1, in the flash write mode, the internal address switched by the switching circuit 4 is supplied to the row decoder 5, and therefore, a row address of a memory cell designated in accordance with the internal address is subjected to a flash write operation. Accordingly, an external flash write address is not required, and thus the external circuit can be simplified. The address generating circuit 13 has a counter which increments or decrements a count value to prepare for the next flash write operation. This operation is performed by the control circuit 2.

The arrangement of the circuit shown in FIG. 1 is described in more detail in the following. Referring to FIG. 2, 1 denotes a dynamic RAM which includes a control circuit 2, an address input buffer 3, an address switching circuit 4, a row decoder 5, a column decoder 6, a sense amplifier & I/O gate 7, a memory cell array 8, a data input buffer 9, a flash write register 10, a data switching circuit 11, a data output buffer 12, and an address generating circuit 13.

Symbols RAS, CAS, WE, and FLW denote external control signals, wherein RAS is a row address strobe signal, CAS is a column address strobe signal, WE is a write enable signal, and FLW is a flash write control signal. Note that an external address flash write control signal EF/W is also one of the external control signals, in another embodiment to be described later.

The control circuit 2 receives the external control signals and generates various types of required internal control signals; for example, the control circuit 2 outputs control clock signals S.sub.A and S.sub.B, a data input clock signal S.sub.I, a data output clock signal S.sub.O, a refresh mode signal S.sub.RF, and a flash write mode signal S.sub.FW.

FIG. 3 is a time chart explaining when the refresh mode signal S.sub.RF is generated, and FIG. 4 is a time chart explaining when the flash write mode signal S.sub.FW is generated.

As shown in FIG. 3, the refresh mode signal S.sub.RF is generated when the signal CAS and RAS are in a CBR relationship in which the signal CAS becomes low (L) level before the signal RAS is made L level, and when the flash write signal FLW is at the L level. In contrast, when the signal RAS becomes L level before the signal CAS is made L level, a usual reading mode is recognized. On the other hand, as shown in FIG. 4, the flash write mode signal S.sub.FW is generated when the signals CAS and RAS are in the CBR relationship and when the flash write signal FLW is at the high (H) level. Accordingly, in the CBR relationship, when the signal FLW is L level, the refresh mode signal S.sub.RF is generated, and when the signal FLW is H level, the flash write signal S.sub.FW is generated. When the signals CAS and AS are not in the CBR relationship, a usual reading mode of the RAM is recognized.

FIG. 5 is a circuit diagram showing a preferred arrangement for generating the refresh mode signal S.sub.RF and the flash write mode signal S.sub.FW. The circuit shown in FIG. 5 is a main part of the control circuit 2, which includes inverters INV.sub.1 to INV.sub.3, 3-input NAND gates NAND.sub.1 and NAND.sub.2, and flip-flops FF.sub.1 and FF.sub.2. The flip-flop FF.sub.1 is set when all of the signals RAS, CAS, and FLW are "L", and is reset when the signal FLW is "H". The flip-flop FF.sub.1 outputs the refresh mode signal S.sub.RF during a set period. The flip-flop FF.sub.2 is set when the signals RAS and CAS are "L" and the signal FLW is "H", and is reset when the signal FLW is "L". The flip-flop FF.sub.2 outputs the flash write mode signal S.sub.FW during a set period. Referring again to FIG. 2, the address input buffer 3 buffers external addresses (A.sub.O to A.sub.n) input by multiplexing the row and column addresses, and the external row address is output to the address switching circuit 4 and the column address is output to the column decoder 6. The address switching circuit 4 normally selects the external row address supplied from the address input buffer 3 and transmits the selected external row address to the row decoder 5. When the signal S.sub.RF or S.sub.FW is input, however, the address switching circuit 4 selects an internal address (to be described later in more detail) from the address generating circuit 13, and transmits the selected internal address to the row decoder 5. The row decoder 5 decodes the transmitted external or internal address, and selects and activates one of a large number of word lines 8a in the memory cell array 8 in accordance with the decoded result. The column decoder 6 decodes the transmitted external address, and selects one of a large number of bit lines 8b in the memory cell array 8 in accordance with the decoded result. When the flash write mode signal S.sub.FW is input, all of the bit lines 8b are selected, and the sense amplifier & I/O gate 7 amplifies the potentials of the selected bit lines 8b to read data from memory cells 8c connected to the selected bit lines 8b, or to write data in these memory cells 8c. The data input buffer 9 buffers external data D.sub.IN, and supplies the data to the flash write register 10 and the data switching circuit 11. The flash write register 10 holds the supplied data, and supplies the held data to the data switching circuit 11 as preset data. The data switching circuit 11 normally selects data from the data input buffer 9. When the flash write mode signal S.sub.FW is input, however, the data switching circuit 11 selects the preset data from the flash write register 10, and supplies the selected data to the sense amplifier & I/O gate 7. The data output buffer 12 buffers the data read out by the sense amplifier & I/O gate 7 to output the buffered data as output data D.sub.OUT.

The address generating circuit 13 includes an internal address counter. When the refresh mode signal S.sub.RF or the flash write mode signal S.sub.FW is input, the address generating circuit 13 sequentially increments (or decrements) refresh or flash write internal addresses for designating word lines 8a in the memory cell array 8. An initial value of the internal address may be a predetermined value or may be a value preset by the external address from the address input buffer 3. The control circuit 2 serves as a designating means for outputting the flash write mode signal S.sub.FW in response to the various control signals (e.g., the signals CASRAS, or FLW) to designate a flash write mode. The address generating circuit 13 serves as an address generating means which is driven in the flash write mode in which the flash write mode signal S.sub.FW is generated, and which sequentially generates word address signals (internal addresses). The row decoder 5 serves as a selecting means for sequentially selecting word lines 8a in accordance with the word address signals (internal addresses).

The flash write register 10 serves as a data generating means for holding the external data D.sub.IN ("0" or "1") and outputting the "0" or "1" preset data while the data is held. The column decoder 6 and the sense amplifier & I/O gate 7 serve as writing means, driven in the flash write mode, for writing the preset data in all of the memory cells 8c connected to intersect the word lines 8a selected by the row decoder 5 as the selecting means.

FIG. 6 is a circuit diagram showing an arrangement of the address switching circuit 4. The address switching circuit 4 includes an OR gate 4a for outputting a switching signal SWCH when the refresh mode signal S.sub.RF or the flash write mode signal S.sub.FW is input, a NAND gate 4b for passing an internal address from the address generating circuit 13 when the signal SWCH is output, an inverter gate 4c for inverting the signal SWCH, a NAND gate 4d for passing an external address from the address input buffer 3 when neither the signal S.sub.FR nor the signal S.sub.RW is input, and a NAND gate 4e for supplying the passed internal or external address to the row decoder 5. The address switching circuit 4 selects the internal address in place of the external address when the signal S.sub.RF or S.sub.FW is input, i.e., in a refresh mode or a flash write mode. Note that the above arrangement corresponds to 1 bit among a plurality of bits corresponding to the addresses A.sub.O to A.sub.n.

An operation of the circuit shown in FIG. 2 will be described hereinafter.

When the signals RAS, CAS, and FLW have a relationship shown in FIG. 3, the refresh mode signal S.sub.RF is output from the control circuit 2, and the refresh mode operation is executed. In this mode, the address generating circuit 13 receives the refresh mode signal S.sub.RF to generate the internal address. The address switching circuit 4 selects the internal address in place of the external address. Therefore, a refresh operation is performed for each word line represented by the internal address and an external designation of a refresh address is not required.

On the other hand, when the signals RAS, CAS, and FLW have a relationship shown in FIG. 4, the flash write mode signal S.sub.FW is output from the control circuit 2, and the flash write mode is set. The address generating circuit 13 receives the flash write mode signal S.sub.FW to generate the internal address, and the address switching circuit 4 selects the internal address in place of the external address. When the signal S.sub.FW is input to the column decoder 6 and the data switching circuit 11, the column decoder 6 selects all of the bit lines 8b, and the data switching circuit 11 selects preset data from the flash write register 10, and therefore, the preset data ("0"or "1") is written in a plurality of memory cells 8c connected to one work line 8a designated in accordance with the internal address. This write operation is repeated for each word line upon an update operation of the internal address, and as a result, a reset operation is performed for each word line and the reset time can be shortened.

Therefore, in this embodiment, the dynamic RAM 1 includes the address generating circuit 13, and the address generating circuit 13 is driven not only in the refresh mode but also in the flash write mode, and accordingly, a flash write mode address generator need not be arranged outside the dynamic RAM 1, thus simplifying the external circuit. Although the internal address is forcibly used in the refresh or flash write mode in the above embodiment, the address to be used is not limited thereto, and the external address can be used as necessary. More specifically, as shown in another arrangement in FIG. 7, a NAND gate 4f and an inverter gate 4g are additionally arranged in the address switching circuit 4. The NAND gate 4f has an input terminal for receiving an external flash write control signal E F/W and another input terminal for receiving the output signal of the OR gate 4a. The output of the NAND gate 4f is inverted by the inverter 4g, and the output of the inverter 4g is connected to an input of the NAND gate 4b and to the input of the inverter 4c.

During a period when the refresh mode signal S.sub.RF or the flash write mode signal S.sub.FW is H level, when the signal EF/W is made H level, the signal S.sub.RF or S.sub.FW passes through the NAND gate 4f so that the internal address is selected by the NAND gate 4b. When the signal EF/W is made L level, the signal S.sub.RF or S.sub.FW does not pass through the NAND gate 4f, and thus the external address is selected by the NAND gate 4d.

Accordingly, the normally H level signal EF/W is supplied to an input terminal of the NAND gate 4f, and the signal EF/W is made L level as needed so that the external address can be used in the refresh or flash write mode. For example, when a specific area in the memory cell array 8 is to be refreshed or flash-written, the external address can be properly designated, thus improving the operability.

In place of the write means in the embodiment described above, the write means may be arranged as follows. More specifically , as shown in an arrangement of a main part of a second embodiment in FIG. 8, flash write transistors 20 serving as a write means are provided. Each of the transistors 20 is connected between each one of bit lines 8b in a memory cell array 8 and ground, and the gates of the flash write transistors 20 are commonly connected to a data switching circuit 21. The data switching circuit 21 includes two pairs of switching elements 21a and 21b for performing opposite operations in response to the flash write mode signal S.sub.FW. Note that, in FIGS. 2 and 8, the same reference numerals denote the same parts. Reference symbol T.sub.p denotes a P-channel transistor operating in response to a sense amplifier drive signal .phi..sub.SAP ; and T.sub.N denotes an N-channel transistor operating in response to a sense amplifier drive signal .phi..sub.SAN. These transistors T.sub.p and T.sub.n supply a power source voltage V.sub.cc and a ground voltage to a sense amplifier SA.

FIG. 9 shows an arrangement of the sense amplifier including a 1/2 V.sub.cc circuit as an example. The 1/2 V.sub.cc circuit includes transistors T.sub.1 to T.sub.3 which are operated in response to a precharge signal .phi..sub.pc for presetting the potentials of bit lines BL.sub.1 and BL.sub.1 at 1/2 V.sub.cc. The sense amplifier SA includes P-channel transistors T.sub.4 and T.sub.5 and N-channel transistors T.sub.6 and T.sub.7, and amplifies a voltage difference between the bit lines BL.sub.1 and BL.sub.1.

With the arrangement shown in FIGS. 8 and 9, in the flash write mode in which the signal S.sub.FW is input, the switching element 21a is turned ON at the same time as the switching element 21b is turned OFF, and each transistor 20 is operated in accordance with preset data from the flash write register 10. As a result, data in each memory cell 8c is updated in accordance with the preset data. According to this embodiment, a large modification of the sense amplifier & I/O gate 7, the column decoder 6, and the like, is not required.

FIG. 10 shows an arrangement of the main part of a third embodiment. Note that, in FIGS. 8 and 10, the same reference numerals denote the same parts. A bit line control circuit BC includes transistors T.sub.8 and T.sub.9 which are turned ON in response to a clock signal .phi..sub.1, for connecting bit lines BL.sub.1 and BL.sub.1 to a 1/2 V.sub.cc power source, transistors T.sub.10 and T.sub.11 which are turned ON in response to clock signals .phi..sub.2 and .phi..sub.2 for connecting the bit lines BL.sub.1 and BL.sub.1 to a V.sub.ss power source, and transistors T.sub.12 and T.sub.13 which are turned ON in response to clock signals .phi..sub.3 and .phi..sub.3 for connecting the bit lines BL.sub.1 and BL.sub.1 to a V.sub.cc power source.

The bit line controller BC resets the bit lines BL.sub.1 and BL.sub.1 at 1/2 V.sub.cc level in response to the signal .phi..sub.1 in a reset mode, and at this time, a sense amplifier SA' and the column decoder 6 are disabled. The sense amplifier SA' does not include a 1/2 V.sub.cc circuit shown in FIG. 8.

In a normal read mode, all of the signals .phi..sub.1 to .phi..sub.3 are disabled, a voltage difference between the bit lines BL.sub.1 and BL.sub.1 is amplified by the sense amplifier SA', and the column decoder 6 is enabled so that the data is transferred to a data bus in a read mode.

In a flash write mode, after the above-mentioned reset operation, the bit lines BL.sub.1 and BL.sub.1 are reset at the V.sub.cc or V.sub.ss level in response to the signal .phi..sub.2 or .phi..sub.3 and at this time, the column decoder 6 is still disabled. The sense amplifier SA' may remain disabled, or may be enabled to immediately reset the bit lines BL.sub.1 and BL.sub.1.

Note that, although a dynamic RAM is exemplified in the above embodiments, the present invention is not limited thereto, and can be applied to any semiconductor memory device requiring reset operation.

According to the present invention, a word address signal required for a flash write mode can be generated inside the device. Therefore, an external address signal is not required, and thus a flash write external address circuit is not required, whereby an external circuit is simplified.

While the invention has been particularly shown and described in reference to preferred embodiments thereof, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the invention.