Driving Circuit of Liquid Crystal Display Which Has Delay Means

The present invention relates to a driving circuit of liquid crystal displays.

Heretofore, liquid crystal displays utilizing ferroelectric liquid crystals have attracted interest of researchers since they have apparent hysteresis properties. The displays of this kind have memory functions which are desirable in some applications. However, if a displayed image remains for a long time in the liquid crystal display after the display system is switched off, the quality of images displayed is degraded when the operation of the system is resumed, due to the "printing" of the previous displayed image (after image).

It is an object of the present invention to provide a driving circuit for liquid crystal display without the adverse effect due to "after image" after the display system is switched off.

In order to accomplish the above and other objects, all the displayed image is clearly erased. The erasure is performed by applying driving signals which are biassed in order to output signals causing the pixels constituting the liquid crystal display to take "0" states.

FIGS. 1(A) and 1(B) are diagrams showing a driving circuit for liquid crystal display in accordance with the present invention.

FIGS. 2(A) and 2(B) are schematic diagrams showing the driving signal during operation and the erasing signal respectively.

FIG. 3 is a timing chart illustrating the operation of the driving circuit in accordance with the present invention.

Referring now to FIGS. 1(A) and 1(B), a driving circuit of liquid crystal display is illustrated in accordance with the present invention. The display to be driven by this circuit is a ferroelectric liquid crystal display comprising a number of pixels arranged in a matrix. The circuit consists of a voltage divider 1 and an operational circuit 3. The function of the voltage divider illustrated in FIG. 1(A) is to divide the voltage between Vdd (+5 V) and Vee connected to a voltage source of -20 V through a TR1 and output three intermediate voltage levels V.sub.1, V.sub.2 and V.sub.3 to the operational circuit illustrated in FIG. 1(B). The operational circuit produces necessary voltage levels by use of the three voltage levels and outputs driving signals 5 such as illustrated in FIG. 2(A) to the liquid crystal display 7. The signal portion 9 causes a pixel to take a "1" state while the signal portion 11 to take a "0" state. The four level appearing in FIG. 2(A) are obtained in the operational circuit by carrying out the addition and the subtraction among the voltage levels supplied thereto. A pixel of the display takes a "1" state at the lowest level and a "0" state at the highest level. The two intermediate states cause no change to the pixels.

The divider functions to modify the voltage levels supplied to the operational circuit in order to obtain driving signals as illustrated in FIG. 2(B), when the display device is closed. This is accomplished by shorting the terminals of V.sub.1 and V.sub.2. For example, in case that the highest level corresponds to V.sub.1 and the next high level to V.sub.2, the next high level is elevated to the highest level.

Next, the operation of the divider will be described. Four resistances R1, R2, R3 and R4 are connected between the Vdd terminal and the Vee terminal in series in order to produce divided levels at the V.sub.1 terminal, the V.sub.2 terminal and the V.sub.3 terminal. A TR5 is coupled with the R2 in parallel. The base terminal of the TR5 is connected to the Vdd terminal through a t4 and a R5. The base terminal of the TR4 is in turn connected to a power-off terminal Poff through a R6. The level at Poff is maintained at +5 V (=the Vdd level) during operation and grounded (OV) when the display system is switched off. During operation, the TR4 and the TR5 are turned off and a predetermined voltage is given across the R2. When the display system is switched off and the Poff level is ground, the TR4 and the TR5 are turned on and eventually the V.sub.1 terminal and the V.sub.2 terminal are shorted.

The voltage level at the Poff terminal indicative of the on-off condition of the display system is supplied also to the base terminal of a TR3 through a delay circuit comprising a R8 and a capacitor C8. The TR3 is connected between the Vdd terminal and the base terminal of a TR2 through a R8. The emitter terminal of the TR2 is connected to the Vdd terminal through a R9 and the collector terminal to the base terminal of the TR1. A R10 is connected between the base and emitter terminals of the TR1. During operation, the TR3 is turned off with the Poff level being 5 V and the TR2 and the TR1 are kept turned on. When the Poff level is ground, the TR3 is turned off after the delay time of the delay circuit, followed by turning off of the TR2 and the TR1. Eventually, the Vee terminal is disconnected from the voltage source of -20 V.

Accordingly, when the display system is switched off, the modified driving signals are supplied to the liquid crystal display 7 and then the system is completely closed after the time delay. This is schematically illustrated in FIG. 3.

While several embodiments have been specifically described, it is to be appreciated that the present invention is not limited to the particular examples described and that modifications and variations can be made without departure from the scope of the invention as defined by the appended claims. Particularly, although a driving signal pattern is illustrated in FIG. 2(A), various types of driving signal pattern have been employed and the present invention can be applied to any type of these pattern.