Semiconductor Device Having Low Source Inductance

This invention relates, in general, to semiconductor devices, and more particularly, to Radio Frequency (RF) semiconductor devices having a low source inductance.

RF power devices are used in communication applications, for example, as amplifiers in output stages of transmitters in cellular radios. RF amplifiers are used in a grounded source configuration. In typical RF power devices, the back side of the die is usually the drain of the device. It would be desirable to have the source be the back of the die because it can be easily grounded to a heatsink. This configuration is also desirable because heat may be conducted away by the heatsink. If the back side of the die is the drain, the die must be mounted on beryllium oxide or another insulator to separate the drain from the grounded heatsink. If the back side of the die is the source, then the die may be directly mounted to the heatsink or other groundplane. This would eliminate the use of beryllium oxide, which is expensive and highly toxic.

An RF power device having a back side source has been fabricated. In this device, electrical contact is made to a multitude of source regions on the top side of the die using a single metal interconnect layer. This metal interconnect layer connects the multitude of source regions to a single P+ region which is in contact with the substrate, or the back-side of the die. Although the back side source contact is advantageous, this particular configuration results in high source inductance, which means that the device will exhibit a lower gain. Thus, it would be desirable to fabricate an RF power device that has a low source inductance. In addition, this device requires the use of a double layer metal process. A separate metal layer is required to make electrical contact to the gate and the drain of the device. It would be desirable, in order to simplify and lessen the cost of manufacturing, to fabricate an RF power device having a back-side source, but with a single layer metal process.

A semiconductor device, comprising a substrate of a first conductivity type, an epitaxial layer of the first conductivity type formed on the substrate, a plurality of source and drain regions of a second conductivity type formed in the epitaxial layer, and a plurality of first regions of the first conductivity type, formed in the epitaxial layer which will be used in conjunction with an ohmic conductive means to connect the substrate to the source regions.

FIGS. 1-7 illustrate enlarged, cross-sectional views of a portion of an embodiment of the present invention in various stages of fabrication.

FIG. 1 illustrates an enlarged, cross-sectional view of a portion of an embodiment of the present invention in a beginning stage of fabrication. What is shown is a semiconductor substrate 10 of a first conductivity type. In this embodiment, substrate 10 is a P+ type silicon substrate and forms the back side of the semiconductor die. An epitaxial layer 12, also of the first conductivity type, is formed on substrate 10 by processes well known in the art. Epitaxial layer 12, in this embodiment, is preferably P- type epitaxial silicon. Next, a first region 14 of the first conductivity type is formed in epitaxial layer 12. First region 14 is preferably more heavily doped than epitaxial layer 12 or P+ type. First region 14 is also formed by processes well known in the art, such as ion implantation and diffusion. It is not necessary, but it is desirable, that first region 14 be in physical contact with substrate 10 now or at the end of the process because conductive means to substrate 10 is still provided by first region 14. Subsequently, a gate region comprising a gate oxide layer 15, a gate polysilicon layer 16, and an optional gate silicide layer 17 are formed on epitaxial layer 12, and gate polysilicon layer 16 and optional gate silicide layer 17 are patterned using standard photolithographic and etch techniques. Gate silicide layer 17 is preferably comprised of tungsten-silicon, however, other refractory metal silicides may be used.

FIG. 2 illustrates the structure of FIG. 1 further along in processing. A photoresist layer 18 is formed to prevent dopants from penetrating a portion of epitaxial layer 12. Photoresist layer 18 is formed partially over gate silicide 17 and over epitaxial layer 12 adjacent the side of gate polysilicon layer 16 and gate silicide layer 17 where first region 14 is not formed. A second region 20 of the first conductivity type is then formed in epitaxial layer 12 in the region where photoresist mask 18 is not disposed. Second region 20 is preferably formed by a standard ion implantation process. Second region 20 is preferably more lightly doped than first region 14.

FIG. 3 illustrates the structure of FIG. 2 further along in processing. A photoresist layer 21 is formed to prevent dopants from penetrating a portion of epitaxial layer 12. Photoresist layer 21 is formed over gate silicide 17 and over epitaxial layer 12 adjacent the side of gate polysilicon layer 16 and gate silicide layer 17 where first region 14 is not formed and partially over epitaxial layer 12 where second region 20 is formed. A third region 22 of the first conductivity type is then formed in epitaxial layer 12 in the region where photoresist mask 21 is not disposed. Third region 22 is also preferably formed by a standard ion implantation process. Third region 22 is preferably more heavily doped than second region 20, but more lightly doped than first region 14.

FIG. 4 illustrates the structure of FIG. 3 further along in processing. A photoresist layer 23 is formed to prevent dopants from penetrating a portion of epitaxial layer 12. Photoresist layer 23 is formed partially over gate silicide layer 17 and over epitaxial layer 12 adjacent the side of gate polysilicon layer 16 and gate silicide layer 17 where first region 14, second region 20 and third region 22 are formed. Subsequently, a fourth region 25 of a second conductivity type is formed in epitaxial layer 12 where photoresist layer 23 is not disposed. Fourth region 25 is also preferably formed by a standard ion implantation process, and preferably doped N type. Fourth region 25 acts as part of the drain of the device.

FIG. 5 illustrates the structure of FIG. 4 further along in processing. Second region 20, third region 22, and fourth region 25 are diffused further into epitaxial layer 12 together in one high temperature step. Of course, each region can be diffused after ion implantation, however, if done together, processing time is reduced. After the diffusion, a photoresist layer 27 is formed on epitaxial layer 12 a portion which extends partially over gate silicide 17 over a portion of fourth region 25 and another portion of which extends partially over first region 14, second region 20, and third region 22.

FIG. 6 illustrates the structure of FIG. 5 further along in processing. A fifth region 29a and a sixth region 29b are formed preferably by ion implanting a dopant of the second conductivity type into epitaxial layer 12 where photoresist layer 27 is not present. Fifth region 29a acts as the source, while sixth region 29b acts as the drain of the device. The drain region is thus comprised of a lightly doped region, region 25, and a more heavily doped region, region 29b. Fourth region 25 acts to increase the breakdown voltage capability of the device. Second region 20 acts as the channel region for the transistor. Third region 22 acts to increase the ruggedness of the device by lowering the series base resistance of the parasitic bipolar transistor formed by fourth region 25, second region 20 and fifth region 29a, and is not absolutely necessary for forming a working device.

FIG. 7 illustrates the structure of FIG. 6 further along in processing. An insulating layer 31 is formed and patterned over gate silicide layer 17 and on gate oxide layer 15 over a portion of epitaxial layer 12 surrounding gate silicide layer 17. Insulating layer 31 may be a single layer or a combination of different insulating layers. Subsequently, ohmic conductive means or a metal layer is formed and patterned to form a drain metal layer 32b, and a source metal layer 32a. Contact is also made to gate silicide layer 17 (not shown) with this same metal layer. The completion of such devices is well known in the art, and thus will not be further described.

As can be seen, a back-side source semiconductor device, having low source inductance has been fabricated. This power FET is optimized for use in RF applications. Source metal layer 32a electrically connects or shorts together fifth region 29a and first region 14 on the top surface of the die, therefore source region 29a is grounded to substrate 10 through first region 14. To fabricate a whole device, a plurality of cells, including a single region that is connected to the substrate. The device of the present invention also has the advantage that a back side source device has. Because the source is on the back side, the die may be directly mounted to a heatsink. Thus, the use of beryllium oxide is eliminated. Note also that a single level metal process has been used because only a single level of metal on the top surface is required to perform all necessary interconnects to the source, drain and gate regions, thus simplifying and lowering the cost of fabricating the device.