Multitask Processing Apparatus Utilizing a Central Processing Unit Equipped With a Micro-Program Memory Which Contains No Software Instructions

1. A multitask processing apparatus comprising: a data bus; a main memory coupled to said data bus and including a plurality of task control blocks each storing a status of a corresponding task; and a central processing unit including an execution unit coupled to said data bus, a ready queue managing means, coupled to said data bus, for registering and eliminating a task in an executable state. a task control block address generating means for generating an address of a task control block of said main memory, an instruction decoder, coupled to said data bus to receive an instruction through said data bus, generating an address of a microprogram corresponding to a received instruction, and a microprogram memory, coupled to said instruction decoder to receive said address of said microprogram, generating control signals for said execution unit, for said ready queue managing means and for said task control block address generating means; wherein a processing demand to a real time operating system required for execution of multitask processing is given through said data bus as an exclusive instruction including task identification information such that said instruction decoder generates an address of said microprogram corresponding to a received exclusive instruction, and said microprogram memory responds to said address supplied from said instruction decoder and generates control signals for said execution unit, for said ready queue managing means and for said task control block address generating means such that a task status is read out from a task control block designated by said task identification information under the control of said task control block address generating means, and is modified by said execution unit and then rewritten to the same task control block, and a task designated by said task identification information is registered as an executable task in said ready queue managing means, and thereafter, a task to be executed next is selected from said ready queue managing means, and wherein said real time operating system is implemented by hardware resources and microprograms stored in said microprogram memory without using a program composed of a combination of instructions to perform a system call.

2. An apparatus as claimed in claim 1, wherein when a first task being executed sends a processing demand to said real time operating system required for starting a second task, an exclusive instruction including an operating code for starting said second task and a task identification number corresponding to said second task is received and processed such that said instruction decoder generates an address of a microprogram corresponding to said received exclusive instruction, and said microprogram memory responds to an address supplied from said instruction decoder to control said task control block address generating means to cause said task control block address generating means to supply said main memory with an address of a task control block corresponding to said second task such that a task status is read out from said task control block corresponding to said second task through said data bus to said execution unit, said microprogram memory also operating to control said execution unit to modify said task status to an executable status and rewrite a modified task status to said task control block corresponding to said second task, said microprogram memory also operating to control said ready queue managing means to register said second task as an executable state, and to output an execution task selection signal to said ready queue managing means such that a task to be executed next is selected from said ready queue managing means.

3. An apparatus as claimed in claim 1, wherein when a first task being executed sends a processing demand to said real time operating system required for suspension of said first task, an exclusive instruction including an operation code for suspending said first task and a task identification number corresponding to said first task is received and processed such that said instruction decoder generates an address of said microprogram corresponding to said received exclusive instruction, and said microprogram memory responds to an address supplied from said instruction decoder to control said task control block address generating means to cause said task control block address generating means to supply said main memory with an address of a task control block corresponding to said first task such that a task status is read out from said task control block corresponding to said first task through said data bus to said execution unit, said microprogram memory also operating to control said execution unit to modify said task status to a wait status and to rewrite a modified task status to said task control block corresponding to said first task, said microprogram memory also operating to control said ready queue managing means to eliminate said first task as an executable state, and to output an execution task selection signal to said ready queue managing means such that a task to be executed next is selected from said ready queue managing means.

4. A multitask processing apparatus comprising: a data bus; a main memory coupled to said data bus and storing an application program; and a central processing unit including an execution unit coupled to said data bus, a ready queue managing means, coupled to said data bus, for registering and eliminating a task in an executable state, a group of register banks, coupled to said data bus, each corresponding to one task and having an area storing a status of a corresponding task, a register bank controller, coupled to said data bus, controlling said register banks, an instruction decoder, coupled to said data bus to receive an instruction through said data bus, generating an address of a microprogram corresponding to a received instruction, and a microprogram memory, coupled to said instruction decoder to receive said address of said microprogram, generating control signals for said execution unit, for said ready queue managing means and for said register bank controller; wherein a processing demand to a real time operating system required for execution of multitask processing is given through said data bus as an exclusive instruction including task identification information such that said instruction decoder generates an address of said microprogram corresponding to a received exclusive instruction, and said microprogram memory responds to an address supplied from said instruction decoder to generate control signals for said execution unit, for said ready queue managing means and for said register bank controller such that a task status is read out from a register bank designated by said task identification information under the control of said register bank controller, and is modified by said execution unit and then rewritten to the same register bank, and a task designated by said task identification information is registered as an executable task in said ready queue managing means, and thereafter, a task to be executed next is selected from said ready queue managing means, and wherein said real time operating system is implemented by hardware resources and microprograms stored in said microprogram memory without using a program composed of a combination of instructions to perform a system call.

5. An apparatus as claimed in claim 4, wherein when a first task being executed sends a processing demand to said real time operating system required for starting a second task, an exclusive instruction including an operation code for starting said second task and a task identification number corresponding to said second task is received and processed such that said instruction decoder generates an address of said microprogram corresponding to a received exclusive instruction, and said microprogram memory responds to an address supplied from said instruction decoder to control said register bank controller to cause a task status to be read out from a register bank corresponding to said second task through said data bus to said execution unit, said microprogram memory also operating to control said execution unit to modify said task status to an executable status and to rewrite a modified task status to said register bank corresponding to said second task, said microprogram memory also operating to control said ready queue managing means to register said second task as an executable state, and to output an execution task selection signal to said ready queue managing means such that a task to be executed next is selected from said ready queue managing means.

6. A multitask processing apparatus comprising: a bus; a main memory coupled to said bus and storing an application program; and a central processing unit including an address generator, coupled to said bus to receive an instruction through said bus, generating an address on the basis of a received instruction and supplying a generated address to said main memory, an execution unit coupled to said bus, an instruction decoding means, coupled to said bus to receive an instruction through said bus, for generating an address of a microprogram corresponding to a received instruction. a microprogram memory, coupled to said instruction decoding means to receive an address of said microprogram, generating control signals, a plurality of task control blocks, coupled to said bus, each holding a status of a corresponding task, a plurality of mailboxes, coupled to said bus, each temporally storing data, a ready queue, coupled to said bus and including a plurality of registers, holding an order of priority of tasks, an operand memory coupled to receive an operand included in an instruction supplied through said bus, selecting means, coupled to said operand memory to receive a control signal from said microprogram memory, for selecting one of said task control blocks and one of said mailboxes, a register bank including a plurality of banks each corresponding to one task and holding a context at a time of generation of an exclusive instruction for a system call, and register bank selecting means for selecting one bank of said plurality of banks; wherein a processing demand to a real time operating system required for execution of multitask processing is given through said bus as an exclusive instruction including task identification information without using a program composed of a combination of instructions to perform said system call such that said instruction decoding means generates an address of said microprogram corresponding to a received exclusive instruction, and said microprogram memory responds to said address supplied from said instruction decoding means to generate control signals for said selecting means and for said register bank selecting means, such that one mailbox is selected by said selecting means on the basis of a content of said operand memory regardless of whether data stored in a selected mailbox has been examined and a bank corresponding to a task which has generated said system call is selected from said register bank, and thereafter, said ready queue is examined such that a highest priority task is selected and a task having said highest priority is selected as a task to be executed next.

7. A multitask processing apparatus comprising: a bus; a main memory coupled to said bus and having a plurality of task control blocks each holding a status of a corresponding task and a plurality of mailboxes each temporally storing data; and a central processing unit including an address generator, coupled to said bus to receive an instruction through said bus, generating an address on the basis of a received instruction and supplying a generated address to said main memory, an execution unit coupled to said bus, an instruction decoding means, coupled to said bus to receive an instruction through said bus, for generating an address of a microprogram corresponding to a received instruction, a microprogram memory, coupled to said instruction decoding means to receive said address of said microprogram, generating control signals, a ready queue, coupled to said bus and including a plurality of registers holding an order of priority of tasks, an operand memory coupled to receive an operand included in an instruction supplied through said bus, control block address generating means, coupled to said operand memory and receiving a control signal from said microprogram memory, for controlling said address generator to select one of said task control blocks and one of said mailboxes in said main memory, a register bank including a plurality of banks each corresponding to one task and holding a context at a time of generation of an exclusive instruction for a system call, and register bank selecting means for selecting one bank of said plurality of banks; wherein a processing demand to a real time operating system required for execution of multitask processing is given through said bus as an exclusive instruction including task identification information without using a program composed of a combination of instructions to perform said system call such that said instruction decoding means generates an address of said microprogram corresponding to a received exclusive instruction, and said microprogram memory responds to said address supplied from said instruction decoding means to generate signals for said control block address generating means and for said register bank selecting means such that one mailbox is selected by said control block address generating means on the basis of a content of said operand memory regardless of whether data stored in a selected mailbox has been examined, and such that a bank corresponding to a task which has generated said system call is selected from said register bank, and thereafter, said ready queue is examined such that a highest priority task is selected and a task having said highest priority is selected as a task to be executed next.