Sigma-Delta Oversampled Analog-to-Digital Converter Network With Chopper Stabilization

This application is related in subject matter to U.S. patent application Ser. No. 505,382 filed April 6, 1990 by David B. Ribner and Richard D. Baertsch, entitled "High Order Sigma Delta Oversampled Analog-To-Digital Converter Integrated Circuit Network With Minimal Power Dissipation and Chip Area Requirements" and assigned to the instant assignee. The subject matter thereof is hereby incorporated by reference.

1. Field of the Invention

This invention generally relates to oversampling analog-to-digital converters of sigma-delta type and, more particularly, to oversampling analog-to-digital converters of sigma-delta type which use chopper-stabilized amplifiers in their Miller integrators.

2. General Description of the Prior Art High resolution analog-to-digital (or A/D) signal conversion can be achieved with lower resolution components through the use of oversampled interpolative (or sigma-delta) modulation followed by digital low pass filtering and decimation. Oversampling refers to operation of the modulator at a rate many times above the signal Nyquist rate, whereas decimation refers to reduction of the clock rate down to the Nyquist rate.

Sigma delta modulators (sometimes referred to as delta sigma modulators) have been used in analog-to-digital converters for some time. Detailed general information can be obtained from the following technical articles which are hereby incorporated by reference.

1) "A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital Converters", J. C. Candy, IEEE Transactions on Communications, Vol. COM-22, No. 3, pp. 298-305, March 1974

2) "Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator", J. C. Candy, et al., IEEE Transactions on Communications, Vol. COM-24, No. 11, pp. 1268-1275, November 1976

3) "A Use of Double Integration in Sigma Delta Modulation", J. C. Candy, IEEE Transactions on Communications, Vol. COM-33, No. 3, pp. 249-258, March 1985.

Substantial effort has been expended in the field of oversampled analog-to-digital converter design to develop plural-order sigma-delta modulators in order to obtain higher resolution for a given oversampling ratio. As the term "order" is used herein, the order of a sigma-delta modulator is determined directly by how many times the error between its output and input signals is integrated with respect to time, while the order of a sigma-delta converter stage within a plural-stage sigma-delta A/D converter is determined directly by how many times the input signal to that stage is integrated with respect to time in reaching the output connection of that stage.

In the above type of analog-to-digital converter, resolution is predominantly governed by two factors: (1) the ratio of the modulator clock to the Nyquist rate, henceforth referred to as the oversampling ratio, and (2) the "order" of the modulator. "Order" in this context is analogous to the order of a frequency selective filter and indicates the relative degree of spectral shaping that is provided by the modulator. As with a filter, higher selectivity is obtainable with a higher order at the expense of increased hardware complexity. In recognition of these two factors, recent implementations of high resolution oversampled analog-to-digital converters have employed both large oversampling ratios and high modulator order. However, practical considerations can limit the extent to which oversampling rate and modulator order can be taken. For instance, for a given modulator clock rate, the oversampling ratio is inversely proportional to the Nyquist rate after decimation and thus cannot be made arbitrarily high without sacrificing conversion rate. Different considerations set bounds on the modulator order. Implementations of order greater than two, using a single quantizer, can be shown to be only conditionally stable and are therefore not viable.

An alternative approach can be used to effectively provide high order noise shaping with cascaded low-order modulators to ensure stable operation. An improved third-order sigma-delta analog-to-digital converter which achieves third-order noise-shaping with reduced sensitivity to component mismatching, finite amplifier gain and other nonideal circuit attributes, herein referred to as "nonidealities" was sought by the present inventor. Improved architectures for third-order sigma-delta analog-to-digital converters which can be implemented as sampled data switched-capacitor circuits were sought. It was also sought to provide third-order quantization noise-shaping in a third-order sigma-delta analog-to-digital converter with a modulator network architecture that employs amplifiers of finite gain and is relatively insensitive to normal circuit nonidealities so that A/D converter resolution approaching the theoretical limits can be obtained. A new third-order sigma-delta analog-to-digital converter network was developed by the inventor that exhibits significantly reduced sensitivity to the practical nonidealities that normally limit resolution of prior-art third-order sigma-delta analog-to-digital converter networks, i.e., component mismatching, amplifier non-linearity, finite gain, excessive settling time, and limited signal dynamic range. Thorough simulations, taking into account nonidealities, indicate that 16-bit resolution at an 80 kHz conversion rate is achievable with the new A/D converter network operated at an oversampling ratio of 64. This performance is attainable despite component matching of only 2% and op amp gains as low as 1000. The realization of these performance levels despite only modest required circuit specifications indicate that a low cost, highly manufacturable A/D converter network is now practicable. MOS, CMOS, BiCMOS, GaAs. or Bipolar integrated circuit technologies can be used with this new A/D converter network to implement a completely monolithic A/D converter network with no external components other than decoupling capacitors. The modest complexity of the new A/D converter network provides for efficient implementation of digital signal processing chips with high resolution multi-channel analog interfaces.

The inventor finds that the practical realization of this new A/D converter network, as well as the practical realization of other A/D converter networks of sigma-delta type that are being developed, is much enhanced by employing chopper stabilization of the operational amplifier used in the initial integrator for error signal. F. Yassa, S. Garverick, G. Ngo, R. Hartley, J. Prince, J. Lam, S. Noujaim, R. Korsunsky and J. Thomas in their paper entitled "A Multi-Channel Digital Demodulator for LVDT and RVDT Position Sensors" appearing on pages 20.5.1-20.5.5 of the IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE DIGEST 0F TECHNICAL PAPERS, CH2671-6/89/0000-0125-$1.00 c. 1989 IEEE describe the use of chopper stabilization in a sigma-delta (or delta-sigma) modulator to eliminate amplifier offset and component mismatch and to generate a dither signal which is added to the input to achieve higher sensitivity to low-amplitude signals. The zero of the decimation filter Yassa et al. used after the sigma-delta modulator is matched to the frequency of the chopping signal, better to suppress the dither signal and other modulator artifacts produced at the chopping frequency. The chopper stabilization moves the flicker (or 1/f) noise of the amplifier in the frequency spectrum from baseband to sidebands of the chopping frequency, the lower of which sidebands aliases into baseband to a degree. As long as high resolution is not demanded from the oversampling A/D converter network, the 1/f noise aliased into the baseband is less than the difference between adjacent quantizing levels even if the frequency of the chopping signal in cycles per second is the same as the rate of the output from the decimation filter in samples per second.

As one strives for increased resolution in the digitized output, however, the 1/f noise aliased into the baseband becomes more than the difference between adjacent quantizing levels if the frequency of the chopping signal in cycles per second is the same as the rate of the output from the decimation filter in samples per second. The inventor finds that this problem is ameliorated if the chopping rate is increased to be a multiple, more than one, times the output rate from the decimation filter. Faster chopping rates introduce a tendency towards increased non-linearity arising from the settling of the chopper-stabilized amplifier after each switching thereof, the inventor finds. So, it is usually preferable not to increase the chopping rate to equal one half the oversampling rate. Rather, the inventor finds, it is usually preferable in an oversampling A/D converter network, from the standpoint of achieving the highest resolution in terms of bits, to choose the chopping rate to be a lower multiple of the rate of the output from the decimation filter. This lower multiple is preferably chosen as close as possible to where the characteristics associated with 1/f noise and with the non-linearity arising from the settling of the chopper-stabilized amplifier after each switching thereof, respectively, exhibit their cross-over in values. Then, the difference between adjacent quantizing levels can be minimized to make available the most number of bits of resolution.

In an oversampling interpolative analog-to-digital converter having a sigma-delta modulator followed in cascade by a decimation filter, the decimation filter supplies digital output signals for the oversampling analog-to-digital converter at an output rate that is a submultiple 1/R of an oversampling rate at which digital samples of an input signal for said decimation filter are supplied. Such an oversampling analog-to-digital converter in which the invention is embodied uses a sigma-delta modulator having therewithin a chopper-stabilized amplifier connected as a Miller integrator for generating an integrator output signal that is the time integral of an error signal, means for quantizing the integrator output signal to generate at an oversampling rate digital samples of the input signal for said decimation filter, a digital-to-analog converter for generating an analog feedback signal corresponding to the digitized input signal for the decimation filter, and means for differentially combining the analog feedback signal with an analog input signal for the oversampling analog-to-digital converter thereby to generate the error signal. The chopping rate of the chopper-stabilized amplifier is a multiple of the output sample rate of the decimation filter to place the fundamental and the harmonics of the chopping at the frequencies corresponding to the zeroes in the decimation filter response, better to keep remnants of the chopper stabilization from appearing in the output samples from the decimation filter. The chopper stabilization moves the flicker (or 1/f) noise of the amplifier in the frequency spectrum from baseband to sidebands of the chopping frequency, and the chopper-stabilized amplifier is operated at a chopping rate higher than said output rate, to reduce the amplitude of the lower sideband as aliased into the baseband. The chopper-stabilized amplifier is operated at a chopping rate lower than half said oversampling rate, to reduce non-linearities associated with the settling of the chopper-stabilzed amplifier after each switching thereof.

FIG. 1 is a circuit block diagram illustrating a known sigma-delta-analog-to-digital converter.

FIGS. 2(a), 2(b), 2(d) and 2(e) illustrate typical power spectra associated with operation of the analog-to-digital converter of FIG. 1, while FIG. 2(c) represents a typical filter characteristic for the decimation filter of FIG. 1.

FIG. 3 is a circuit block diagram illustrating a third-order sigma-delta analog-to-digital converter network.

FIG. 4 is a functional block diagram of one version of the FIG. 3 type of third-order sigma-delta analog-to-digital converter network.

FIG. 5 is a functional block diagram of a specific embodiment of the FIG. 3 type of third-order sigma-delta analog-to converter network.

FIG. 6 a circuit block diagram of a sampled data single-ended switched capacitor implementation of the third-order sigma-delta analog-to-digital converter network of FIG. 5.

FIG. 7 is a circuit block diagram of a sampled data differential switched capacitor implementation of the third-order sigma-delta analog-to-digital converter network of FIG. 5, which in accordance with the invention employs chopper stabilization of the operational amplifier in the first integrator for error signal.

FIG. 8 illustrates waveforms of clock signals employed in the circuit of FIG. 7.

FIG. 9 is a circuit block diagram of a decimation filter that can be used in the third-order sigma-delta analog-to-digital converter networks of FIGS. 3, 4 and 5.

FIG. 10 is a circuit block diagram illustrating a third-order sigma-delta analog-to-digital converter network, which is of a type alternative to the FIG. 3 type.

FIG. 11 is a functional block diagram of one version of the FIG. 10 type of third-order sigma-delta analog-to-digital converter network.

FIGF. 12 is a circuit block diagram of a decimation filter for use with the FIG. 10 or FIG. 11 circuitry.

FIG. 13 is a circuit block diagram illustrating a third-order sigma-delta analog-to-digital converter network, which is of a type alternative to the FIG. 3 and FIG. 9 types.

FIG. 14 is a functional block diagram of one version of the FIG. 13 type of third-order sigma-delta analog-to-digital converter network.

FIG. 15 is a circuit block diagram of a decimation filter for use with the FIG. 13 or FIG. 14 circuitry.

FIG. 1 shows a known embodiment of sigma-delta analog-to-digital converter in which an oversampled interpolative (sigma-delta) modulator 10 is coupled to a low pass decimation filter 12 which, in turn, is coupled to a sampling-rate compressor 14. The role of modulator 10 is to shape spectrally the quantization noise of a low resolution analog-to-digital converter so that it is predominantly concentrated at high frequency. The input signal x(n) to modulator 10 is a pure sinusoid of frequency F.sub.S and is sampled by modulator 10 at a sampling rate F.sub.M. Subsequent low pass filtering and decimation can be used to remove the bulk of the quantization noise, resulting in a high resolution digital output signal at a reduced conversion rate F.sub.M /R where R is the oversampling ratio, or ratio of the output clock rate (F') to the input clock (or sample) rate F.sub.M.

In FIG. 1, the following functions are represented: input signal x(n), modulator output signal u(n), filter output signal w(n), and A/D converter output signal y(n) along with the filter impulse response characteristic h(n). The corresponding frequency spectra .vertline.X(f).vertline., .vertline.U(f).vertline., .vertline.W(f).vertline., and .vertline.Y(f).vertline., and filter characteristic .vertline.H(f).vertline., respectively, are shown in FIGS. 2(a), 2(b), 2(d), 2(e) and 2(c), respectively, and represent the conditions in the circuit of FIG. 1 at locations (a), (b), (d), (e) and (c), respectively. These frequency spectra illustrate the noise shaping provided by modulator 10 and the high frequency noise rejection provided by low pass decimation filter 12 prior to the sampling rate conversion performed by compressor 14.

A simplified block diagram of a third-order sigma-delta analog-to-digital converter network is shown in FIG. 3 and includes a second-order modulator 20 coupled to a first-order modulator 30. Second-order modulator 20 includes a pair of cascaded integrators 22 and 24, an analog-to-digital converter 26 coupled to the output of integrator 24, and a digital-to-analog (D/A) converter 28 coupled in a first feedback loop between the output of analog-to-digital converter 26 and the input of integrator 22 via a subtractive summing unit 32 and in a second feedback loop between the output of analog-to-digital converter 26 and the input of integrator 24 via an amplifier 23 having a gain of 2 and a subtractive summing unit 34 connected in series.

Second-order modulator 20 responds to an analog input signal x(t) and at low frequencies .OMEGA.<<.pi./T, where T is the sampling period and T=1/F.sub.M, produces a digital output signal of approximately

containing a component x, which is a digital representation of the ideal analog input signal, along with a shaped quantization noise signal d.sup.2 Q.sub.1 /dt.sup.2. The quantizing noise Q.sub.1 generated during analog-to-digital conversion by the analog-to-digital converter 26 within the second-order modulator 20 is doubly differentiated by the two-integrator loop and pushed to substantially higher frequency in the output signal from the second-order modulator 20. The signal applied to analog-to-digital converter 26 is an analog signal

equal to the digital output signal x+d.sup.2 Q.sub.1 /dt.sup.2 less the additive quantization noise Q.sub.1 and is applied to first-order modulator 30.

First-order modulator 30 includes a single integrator 36 coupled to an analog-to-digital converter 38. A digital-to-analog converter 40 is coupled in a feedback loop between the output of analog-to-digital converter 38 and the input of integrator 36 via a subtractive summing unit 42. The quantizing noise Q.sub.2 generated during analog-to-digital conversion by the analog-to-digital converter 38 within the first-order modulator 30 is differentiated by the single-integrator loop and pushed to higher frequency in the output signal from the first-order modulator 30. First-order modulator 30, at low frequencies .OMEGA.<<.pi./T, produces a digital output signal of approximately

which is equal to an exact replica of its input signal plus the differentiated additive quantization noise signal dQ.sub.2 /dt.

A digital subtractor 44 is coupled to the outputs of second-order modulator 20 and first-order modulator 30 to determine the difference between the digital output signals from modulators 20 and 30. A digital double differentiator 46 is coupled to the output of digital subtractor 44 for twice differentiating the digital difference signal from digital subtractor 44. A digital adder 48 is coupled to the outputs of second-order modulator 20 and digital double differentiator 46 to add the digital output signal from modulator 20 to the resultant digital output signal produced by digital double differentiator 46. The digital output signal produced by adder 48 is applied to a digital decimation filter 50.

Ignoring for now the output quantization noise dQ.sub.2 /dt of modulator 30, the difference between the two digital output signals from modulators 20 and 30 is exactly equal to minus the quantization noise (-Q.sub.1) of second-order modulator 20. A double differentiated signal (-d.sup.2 Q.sub.1 /dt.sup.2) from digital double differentiator 46 is added to the digital output signal of second-order modulator 20 by digital adder 48 to effect the cancellation of the quantization noise Q.sub.1 of modulator 20.

Considering now the quantization noise signal dQ.sub.2 /dt that was previously ignored, the noise signal Q.sub.2 has been differentiated once by first-order modulator 30, generating a signal dQ.sub.2 /dt. It is further differentiated two more times by digital differentiator 46 so that, in the output signal y(t) from adder 48, the only noise is the triple differentiated noise signal d.sup.3 Q.sub.2 /dt.sup.3. This amounts to a third-order shaping of the quantization noise which greatly attenuates its baseband components and emphasizes its high frequency power. The triple differentiated noise signal d.sup.3 Q.sub.2 /dt.sub.3 is effectively eliminated from the final digital output signal by digital decimation filter 50.

The intended implementation of the third-order sigma-delta analog-to-digital converter network is in a sampled data switched capacitor circuit in accordance with the discrete-time domain functional block diagram of FIG. 4. A design objective with oversampled modulators is the scaling of analog signal levels to be on the order of the reference voltage. Therefore, a discrete time version is shown in FIG. 4 to indicate that such version is possible for the new converter network.

In FIG. 4, each of integrators 22, 24 and 36 is shown as a one-cycle delay register 60 preceded by an adder (or summing) unit 62. Digital double differentiator 46 is shown as a pair of cascaded differentiators 78, each comprising a delay register 80 followed by a digital subtractor 82.

An amplifier 84 having a gain coefficient k.sub.1a is situated in second-order modulator 20 at the input to an integrator 22 and following a summing unit 32. An amplifier 86 with a gain coefficient k.sub.1b couples the output of integrator 22 to the input of an integrator 24 through a summing unit 34. Another amplifier 88 with a gain coefficient 2.sub.k1a -k.sub.1b is situated in a feedback loop of second-order modulator 20 between the output of a digital-to-analog converter 28, and a negative input to summing unit 34, while a second feedback loop in modulator 20 is provided by coupling the output of converter 28 to a negative input of summing unit 32. An amplifier 92 of gain j.sub.1 couples the output of integrator 24 to a subtractive summing unit 42 in first-order modulator 30, while an amplifier 90 having gain coefficient k.sub.2 is situated at the input of integrator 36 after summing unit 42 in modulator 30.

A digital multiplier 74 having a multiplier coefficient g.sup.1 couples the output of analog-to-digital converter 38 of first-order modulator 30 to digital subtractor 44, while digital-to-analog converter 40 couples the output of analog-to-digital converter 38 to subtractive summing unit 42. The output of analog-to-digital converter 26 of second-order modulator 20 is connected through a delay register 76 to the negative input of digital subtracter 44 and to digital adder 48. A dashed line 9 designates the separation between digital circuitry 21 and analog circuitry 19.

In FIG. 4, coefficients k.sub.1a, k.sub.1b, k.sub.2, and j.sub.1 are analog scaling coefficients, whereas g.sup.1 is a digital multiplier coefficient. These coefficients must be related according to:

These relationships have meaning only for the case where only one-bit analog-to-digital converters and only one-bit digital-to-analog converters are used. Normally the k coefficients are selected to be less than one so as to reduce the level of internal voltages within the modulator and thereby avoid clipping. Analysis of the network of FIG. 4 results in an input signal/output signal relationship in the discrete time domain of ##EQU1## and of

in the corresponding frequency domain, where n represents the discrete time instant nT (T being the sample period), z is the discrete time frequency variable and E.sub.2 is the quantization error of the second stage. It should be noted that a trade-off exists between voltage levels and output noise intensity; specifically, if scaling is employed, then the condition k.sub.1a k.sub.1b <1 imposes g.sub.1 >1, and the output error is increased proportionately as indicated by Equations 2 and 3.

While the implementation shown in FIG. 4 implies the use of one-bit A/D converters and D/A converters, improvements in performance can be achieved by using multiple bit A/D and D/A converters. For cases where the quantization levels are greater than one bit, then k.sub.1a =k.sub.1b =k.sub.2 =1 in FIG. 4 and j.sub.1 g.sub.1 =1.

A specific implementation of the new third-order sigma-delta oversampled A/D converter network is shown in FIG. 5, with L=1, k.sub.1a =k.sub.1b =k.sub.2 =1/2, j.sub.1 =1 and g.sub.1 =4. Thus amplifiers 84 and 86 in second-order modulator 20 and amplifier 90 in first-order modulator 30 each have a gain coefficient of 1/2, and digital multiplier 74 has a multiplier coefficient of 4. (Amplifier 92 with a gain coefficient j.sub.1 =1 and amplifier 88 with a gain coefficient 2k.sub.1a k.sub.1b =1/2, employed in the circuit of FIG. 4, are not shown in the circuit of FIG. 5.) This implementation requires only one bit A/D and D/A converters.

A switched capacitor implementation of the network of FIG. 5 is shown in FIG. 6 and employs a single-ended signal flow and stray-free integrators. Such integrators are described, for example, in R. Gregorian, "Analog MOS Integrated Circuits for Signal Processing", pp. 277-280, Wiley, N.Y., 1986, incorporated herein by reference. In second-order modulator 20, integrator 22 is embodied as a high gain differential amplifier (op amp) 100 provided with a feedback capacitor 102 and a switched input capacitor 104. A switch S.sub.1 is provided for switching a capacitor 104 between the analog input signal and the feedback loop of modulator 20. A switch S.sub.2 is provided for switching the output voltage of capacitor 104 between the two inputs of differential amplifier 100. Similarly, integrator 24 is embodied as a high gain differential amplifier (op amp) 110 provided with a feedback capacitor 112 and a pair of switched input capacitors 114 and 103. A switch S.sub.3 is provided for switching capacitor 114 between the analog output signal from differential amplifier 100 and ground while a switch S.sub.9 is provided for switching capacitor 103 between the feedback loop of modulator 20 and ground. A switch S.sub.4 is provided for switching the output voltage of capacitors 114 and 103 between the two inputs of differential amplifier 110. A comparator 116 operated at a sampling rate .phi..sub.1 converts the analog output signal from differential amplifier 110 into a binary output signal. This binary output signal is stored by a latch 118 and applied via a delay register 76 to the negative input of digital subtractor 44 and to digital adder 48. The output signal from latch 118 also controls a switch S.sub.5 for switching the feedback loop between a positive reference voltage +V.sub.ref and a negative reference voltage -V.sub.ref depending on whether the polarity of the latched output signal from comparator 116 is positive or negative. In first-order modulator 30, integrator 36 is embodied as a high gain differential amplifier (op amp) 120 provided with a feedback capacitor 122 and a switched input capacitor 124. A switch S.sub.6 is provided for switching capacitor 124 between the analog output signal from differential amplifier 110 and the feedback loop of modulator 30. A switch S7 is provided for switching the output voltage of capacitor 124 between the two inputs of differential amplifier 120. A comparator 126 operated on a sampling phase .phi..sub.1 converts the analog output signal from differential amplifier 120 into a binary output signal. This binary output signal is stored by a latch 128, multiplied by four by multiplier 74, and applied to digital subtractor 44. The output signal of latch 128 also controls a switch S.sub.8 for switching the feedback loop between a positive reference voltage +V.sub.ref and a negative reference voltage -V.sub.ref depending on whether polarity of the latched output signal from comparator 126 is positive or negative. The digital difference signal produced by digital subtractor 44 is differentiated twice by digital double differentiator 46 and the resultant differentiated signal is applied to digital adder 48. The switches, which may be implemented by metal-oxide-semiconductor switching devices, as known in the art, are all shown in a common phase .phi..sub.1.

Switches S.sub.1 -S.sub.4, S.sub.6, S.sub.7 and S.sub.9 are analog switches controlled by clock phase signals .phi..sub.1, .phi..sub.2 which are derived from an oscillator or clock circuit (not shown). The clock signals are nonoverlapped and 180.degree. out of phase.

When switches S.sub.1 -S.sub.4, S.sub.6, S.sub.7 and S.sub.9 are in the positions illustrated in FIG. 6, capacitor 104 charges to the amplitude of the analog input signal while capacitor 114 charges to the output voltage of amp 100 and capacitor 124 charges to the output voltage of op amp 110. At the same time capacitor 103 is totally discharged.

Switches S.sub.5 and S.sub.8, both shown connected to a positive reference voltage, are controlled by the output signal of latch 118 and 128, respectively. Thus, when the latched value of the output signal of comparator 116 or 126 is high, switch S.sub.5 or S.sub.8, respectively, is connected to a positive reference voltage, and is connected to a negative reference voltage when the latched value of the output signal of comparator 116 or 126, respectively, is low.

Upon occurrence of phase .phi..sub.2, the positions of switches S.sub.1 -S.sub.4, S.sub.6, S.sub.7 and S.sub.9 reverse from that shown in FIG. 6. Thus D/A converter 28 supplies a selected reference voltage through switch S.sub.5, shown as being of positive polarity, which is added to the voltage on capacitor 104 and applied to the inverting input of amplifier 100. This input signal is integrated up in capacitor 102 until reoccurrence of clock phase .phi..sub.1. At the same time, the previous (i.e., phase .phi..sub.1) output voltage of amplifier 100, stored in capacitor 114, plus the reference voltage from switch S.sub.5 which is now stored on capacitor 103, are supplied to the inverting input of amplifier 110, and the previous (i.e., phase .phi..sub.1) output voltage of amplifier 110, stored on capacitor 124, is supplied to the inverting input of amplifier 120. Each of amplifiers 100, 110 and 120 thus performs an integration of the input voltage supplied to its respective inverting input terminal until phase .phi..sub.1 again occurs.

If the signal at the input to comparator 116 is positive, switch S.sub.5 is connected to the positive reference +V.sub.ref, while if the signal is negative, switch S.sub.5 is connected to the negative reference -V.sub.ref. The signal at the comparator input is determined by an integration of a difference between the voltage developed on capacitors 103 and 114. The voltage on the output of integrator 22 is an integration of the difference between the input signal and either the positive or negative reference depending on the position of switch S.sub.5. The output signal of integrator 22 can also be viewed as the integrated difference between the analog input signal and the digital representation of the analog input signal.

Integrator 22 acts as a noninverting integrator for the analog input signal, and as an inverting integrator for one-bit D/A converter 28 controlled by comparator 116. The output signal of integrator 22 changes every phase .phi..sub.2 by an amount (V.sub.in -V.sub.D/A1)k.sub.1a, where V.sub.D/A1 is the output voltage of D/A converter 28 while, during phase .phi..sub.1, the output signal of integrator 22 remains held at the value established on the previous phase .phi..sub.2. Integrator 36 operates in a similar manner, except that its input signal is the output signal of integrator 24 less the output signal of D/A converter 40; that is, the integrator 36 output signal changes every phase .phi..sub.2 by an amount (V.sub.2 -V.sub.D/A2)k.sub.2, where V.sub.2 is the output voltage of integrator 36 and is held on phase .phi..sub.1, and V.sub.D/A2 is the output voltage of D/A converter 40.

The configuration of integrator 24 is slightly different from that of integrators 22 and 36 in that it uses separate capacitors 114 and 103 for its two input signals. This is necessary since different capacitor ratios are required for the two input signals to integrator 24. Specifically, the output signal of integrator 22 should be integrated with ratio k.sub.1b while the output signal of D/A converter 28 needs to be integrated with ratio -2.sub.k1a k.sub.1b, and therefore a combination of a noninverting and inverting switched capacitor integrator is employed as integrator 24. Through use of superposition, multiple input signals are accommodated by common connection at switch S.sub.4 adjacent to the summing junction of op amp 110. Since each separate input capacitor 114 and 103 switches between ground and the op amp 110 negative input, switch S.sub.4 can be shared, though individual switches S.sub.3 and S.sub.9 are needed for connection to the two input signals. The output signal of integrator 24 changes every phase .phi..sub.2 by an amount k.sub.1b V.sub.2 -2k.sub.1a k.sub.1b V.sub.D/A2 and is held during phase .phi..sub.1. In the circumstance that k.sub.1a =1/2, the two input capacitors 114 and 103 have the same value and a single capacitor may be used instead, as with integrators 22 and 36.

The circuit of FIG. 6 is quite tolerant of capacitor mismatch errors. Each of the two switched capacitor integrators 22 and 36, respectively, employs a single switched capacitor 104 and 124, respectively, to take the difference of its two input signals. Therefore, the subtraction operation is immune to error. The remaining switched capacitor integrator 24 uses separate switched capacitors 114 and 103 to take the difference of its two input signals; however, matching errors here are negligible when referred to the input. The other remaining summation or difference operations are implemented digitally and are also error free. The only component mismatch related error is the departure of the product k.sub.1a k.sub.1b from equaling 1/j.sub.1g1. This has the effect of leaking in the quantization noise from the first stage by the amount

to make the overall output voltage Vo(z) become ##EQU2## where E.sub.1 represents the quantization noise of the first stage. Since the degree of mismatch, namely, 1-j.sub.1g1 /(k.sub.1a k.sub.1b), multiplies a term that already has second-order noise shaping, i.e , (1-z.sup.-1).sup.2 E.sub.1 (z), a relatively large error in k.sub.1a or k.sub.1b can be tolerated without undue degradation. For instance, it can be shown that a 5% error in the product k.sub.1a k.sub.1b would raise the total quantization noise by less than 1 dB at an oversampling ratio of 64 to 1.

Extension simulations have been performed on a version of this new oversampled modulator. The parameters of the new analog-to-digital converter are as follows:

The simulation results are summarized below:

An improved modulator network that achieves third-order noise shaping and yet exhibits significantly reduced sensitivity to component matching and most other practical nonidealities is herein described. Simulations have shown that a 16-bit signal-to-noise ratio can be attained despite component matching of 2% and op amp gains of 1000. It is contemplated that integrated circuits containing this modulator can be manufactured with high yields, without trimming or calibration, and without any stringent process specifications. Thus the invention contemplates a high resolution, multi-channel analog-to-digital converter which can be economically achieved.

Although the modulator components, i.e., the integrators, the analog-to-digital converters, and the digital-to-analog converters, are so far illustrated with single-ended outputs, the third-order sigma-delta analog-to-digital converter can advantageously be implemented by employing a differential signal path using integrators with differential outputs for improved rejection of power supply noise. This is shown in FIG. 7.

FIG. 7 illustrates a network employing differential amplifiers which is representative of the circuitry used in a third-order sigma-delta oversampled A/D converter network test chip, while FIG. 8 illustrates the clock waveforms employed in the circuit of FIG. 7. The circuit of FIG. 7 differs from the single-ended switched-capacitor A/D converter network shown in FIG. 6 in that it uses three-phase instead of two-phase clocking, it makes use of a fully-balanced (or differential) signal path for better rejection of spurious power supply noise and common mode signals, it employs a chopper stabilization circuit 200 for suppression of low frequency op amp noise, and it can be operated as a single-ended input circuit even though it is a differential circuit. Each of integrators 22, 24 and 36 employed in the circuit of FIG. 7 is a Miller integrator comprising a respective op amp provided with respective balanced inputs; respective balanced outputs; and respective Miller feedback capacitors C.sub.1P and C.sub.1N, C.sub.2P and C.sub.2N, or C.sub.3P and C.sub.3N ;.

In considering operation of the circuit of FIG. 7, the presence of chopper 200 as part of integrator 22 will be ignored initially by assuming chopper phase .phi..sub.CHP is always asserted. A balanced input signal is also assumed. In these circumstances, operation is similar to that of the single-ended circuit of FIG. 6 with the clock phases defined differently; i.e., clock phases .phi..sub.1 and .phi..sub.2 in the circuit of FIG. 6 now correspond to phases .phi..sub.3 and .phi..sub.1, respectively. Operation is the same as described for FIG. 6, if phase .phi..sub.2 is temporarily ignored, except that when the input signal is sampled during phase .phi..sub.3 by the two input capacitors 201 and 202, their output sides are connected together through switch S.sub.10, instead of to ground. This connection is made so that only the differential component of the input signal is acquired. A common mode signal, if present, would also be sampled if capacitors 201 and 202 were switched to ground instead of to each other; however, in the configuration shown, the charge stored on input capacitors 201 and 202 depends only on the difference between the two input signals, not on their average value. Similar effects occur with regard to input capacitors 203 and 204 for the second stage integrator 24 of the network and input capacitors 205 and 206 for the third stage integrator 36 of the network.

As just described, the output sides of the input capacitors for each of the integrator stages would never be connected to a voltage source or ground, and hence the voltages on each of these capacitors would be arbitrary. Similarly, the voltage level at the input to the op amp receiving a signal from its input capacitors would be undefined. Therefore, to establish the potential at the output (or right-hand) side of the input capacitors, a connection to ground during phase .phi..sub.2 is employed while the input (or left-hand) side of each input capacitor remains connected to receive the reference signals.

Another minor difference from the circuit of FIG. 6 is that the one-bit D/A converters 210, 211 and 212 are implemented directly at the input (or left-hand) sides of input capacitors 201 and 202, 203 and 204, and 205 and 206, respectively, instead of by employing the single pole double-throw switches S.sub.5 and S.sub.8 shown in the network of FIG. 6. The effect, however, is the same since the switches in each of D/A converters 210, 211 and 212 are controlled by a signal that is equal to the desired clock phase which is logically ANDed with the latched comparator signal. This implementation avoids need for a series connection of two switches and its associated speed penalty in high frequency circuit operation.

The logic for the individual switch positions in D/A converters 210, 211 and 212 is as follows: ##EQU3## Where CMPlD and CMP2D are the output signals from comparator 216 at the output of second stage integrator 24, as latched by a latch circuit 218, and the output signals from comparator 226 at the output of third stage integrator 36, as latched by a latch circuit 228, respectively. Clock waveform .phi..sub.12 is shown in FIG. 8.

In considering the role of the chopper, the MOS switching devices represented by double-pole, double-throw switches 200 on either side of the first op amp 222 perform a periodic reversal of signal polarities at the input and output of the op amp as controlled by the .phi..sub.CHP and .phi..sub.CHN chopper clock signals. Clocks .phi..sub.CHP and .phi..sub.CHN, illustrated in the waveform drawings of FIG. 8, may alternate at any rate that is an integer multiple of the output conversion rate, up to a maximum rate of the modulator frequency. When clock .phi..sub.CHP is high, a noninverting path through op amp 222 is selected by the chopper at both input and output, while when phase .phi..sub.CHN is high, an inverting configuration is produced. Since inversion takes place simultaneously at both the input and output of the op amp whenever clock .phi..sub.CHN is high, there is no effect on signals traversing the integrator. However, noise from the op amp itself goes through only the output switches of the chopper and, as such, alternates in polarity at a rate determined by the frequency of the chopper clocks. This is equivalent to multiplying the noise by a periodic square wave signal with an amplitude of .+-.1, which amounts to a modulation of the op amp noise up to the frequency of the chopper square wave and all of its harmonics. As a result, the severe low frequency flicker (or 1/f) noise is largely moved out of the baseband frequency of the modulator through heterodyning. Flicker noise is discussed in R. Gregorian, "Analog MOS Integrated Circuits for Signal Processing", previously cited, at pages 500-505, and the discussion therein is hereby incorporated by reference. Subsequent digital filtering by the decimation filter (not shown in FIG. 7) removes the modulated 1/f noise. In fact, chopping at a rate equal to the output rate of the decimation filter or a higher, integer multiple of that rate, places the fundamental and harmonics of the square wave at the frequencies of the zeros of the decimation filter (if a comb-type filter is used), facilitating removal of the modulated noise. As previously noted, in the present invention the chopping is done at a higher, integer multiple.

FIG. 9 shows a form the digital decimation filter 50 of FIG. 3 may take. FIG. 9 shows a comb filter of the sinc.sup.n type of the type described by E. Dijkstra, O. Nye, C. Piguet and M. Degrauwe in their Paper "On the Use of Modulo Artithmetic Comb Filters in Sigma Delta Modulators" in pages 2001-2004 of the PROCEEDINGS OF THE IEEE CONFERENCE ON ACOUSTICS, SPEECH & PROCESSING, 1988. The FIG. 3 third-order sigma-delta analog-to-digital converter network shapes its quantization noise spectrum with a sixth-order sinusoidal characteristic

where k.sub.QN is the power-spectral density (PSD) of the unshaped (white) quantization noise and L=3 is the order of the sigma-delta modulator. A comb filter of the sinc.sup.n type can adequately suppress this quantization noise, if n exceeds L by one. The FIG. 9 comb filter, wherein n equals four, will adequately suppress the k.sub.QN [2 sin(.OMEGA.T/2)].sup.6 quantization noise in the sum output signal of the adder 48 in the third-order sigma-delta analog-to-digital converter network of FIG. 3.

The FIG. 9 comb filter receives as its input signal the sum output signal from the digital adder 48 of the FIGS. 3, 4 or 5 sigma-delta modulator to be quadruply integrated in a cascade of n integrators, n equalling four in the FIG. 9 comb filter, each integrator 300 comprising a respective digital adder 301 and a respective delay register 302 for feeding back the sum output of the adder 301 to an input thereof. In a decimation procedure, the quadruply integrated response of this cascade is subsampled n:1 in a digital sampler 310 as may be provided by a plural-bit latch. The subsampled response of the digital sampler 310 is quadruply differentiated in a cascade of n differentiators, n equalling four in the FIG. 9 comb filter, each differentiator 320 shown as comprising a digital adder 321 for adding together the current sample of differentiator 320 input signal to the previous sample as stored in a delay register 322, thereby to generate a sum output signal that is the derivative respective to time of the differentiator 320 input signal. The response from the final differentiator 320 is scaled down in amplitude by n.sup.n in a digital scaler 330 is the ultimate decimation filter 50 response.

FIG. 10 shows a variant of the FIG. 3 third-order sigma-delta analog-to-digital converter network. Rather than doubly differentiating the subtractor 44 difference output signal with respect to time and adding the result to the second-order modulator 20 output signal to cancel the quantization noise from the second-order modulator 20, the second-order modulator 20 output signal is doubly integrated in a digital double integrator 51, and the response of digital double integrator 51 is added in an digital adder 52 to the second-order modulator 20 output signal. The sum output signal from adder 52 includes a low-pass filtered (twice integrated) digitization of analog input signal plus first-order quantization noise from the first-order modulator 30. The quantization noise from the second-order modulator 20 does not appear in the sum output signal from adder 52, which is supplied to a digital decimation filter 53 that responds with a digital output signal y(t).

FIG. 11 shows a variant of the FIG. 4 third-order sigma-delta analog-to-digital converter network, which variant is of the type shown generally in FIG. 10. The digital double integrator 51 is shown more particularly in FIG. 10 as a pair of cascaded integrators 54, each integrator 54 comprising a digital adder 55 and a delay register 56 for feeding back the sum output of the adder 55 to an input thereof.

FIG. 12 shows a form the digital decimation filter 53 can take. The digital decimation filter 53, connected to receive as its input signal the sum output signal from the digital adder 52 of FIGS. 10 or 11, supplies the same response as the digital decimation filter 50, connected to receive as its input signal the sum output signal from the digital adder 48 of FIGS. 3 or 4. The leading two integrators 300 of the digital decimation filter 50 are dispensed with in the digital decimation filter 53, which is possible owing to the FIGS. 10 or 11 third-order sigma-delta analog-to-digital converter network having the digital double integrator 51 for the output signal of the second-order modulator 20 and not having the digital double differentiator 46 for the output signal from the digital subtractor 44.

FIG. 13 shows a variant of the FIG. 3 and FIG. 10 third-order sigma-delta analog-to-digital converter networks.

The subtractor 44 difference output signal is differentiated only once with respect to time in a single digital integrator 78, the second-order modulator 20 output signal is integrated only once in a digital integrator 54, and the responses of of digital integrator 78 and digital integrator 54 are added together in an digital adder 57. The sum output signal from adder 57 includes a low-pass filtered (once integrated) digitization of analog input signal plus second-order quantization noise from the first-order modulator 30. The quantization noise from the second-order modulator 20 does not appear in the sum output signal from adder 57, which is supplied to a digital decimation filter 58 that responds with a digital output signal y(t).

FIG. 14 shows a variant of the third-order sigma-delta analog-to-digital converter networks of FIG. 4 and FIG. 11, which variant is of the type shown generally in FIG. 13. The differentiator 78 is shown as comprising a digital adder 82 for adding together the current sample of difference signal from subtractor 44 to the previous sample as stored in a delay register 80, thereby to generate a sum output signal that is the derivative respective to time of the difference signal from subtractor 44. The integrator 54 is shown as comprising a digital adder 55 and a delay register 56 for feeding back the sum output of the adder 55 to an input thereof.

FIG. 15 shows a form the digital decimation filter 58 can take. The digital decimation filter 58, connected to receive as its input signal the sum output signal from the digital adder 52 of FIGS. 13 or 14, supplies the same response as the digital decimation filter 50, connected to receive as its input signal the sum output signal from the digital adder 48 of FIGS. 3 or 4. The leading integrator 300 of the digital decimation filter 50 is dispensed with in the digital decimation filter 58, which is possible owing to the FIGS. 13 or 14 third-order sigma-delta analog-to-digital converter network having the digital integrator 54 for the output signal of the second-order modulator 20 and having only the single digital differentiator 78 for the output signal from the digital subtractor 44.

While the features of the invention have been specifically illustrated and described herein with particular regard to improved third-order sigma-delta modulators, many modifications and changes will occur to those skilled in the art in light of the teaching of this specification, as will permit adapting those features to other high-resolution sigma-delta modulators using chopper-stabilized amplifiers in their construction. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.