CMOS Bus Driver Circuit With Improved Speed

Related copending application of particular interest to this invention is application Ser. No. 07/486,443, filed Feb. 28, 1990, on behalf of Lloyd P. Mathews entitled "Data Processor Circuit and Method for Controlling Voltage Variation of a Dynamic Node".

This invention relates generally to communication bus driver circuits, and more particularly, to CMOS bus driver circuits for use in a data processor.

An integrated circuit often uses a communication bus to route groups of signals between different parts of the integrated circuit. The bus comprises several signal lines made of a low-impedance conductor, typically metal, and couples to a plurality of circuits for either receiving signals therefrom or providing signals thereto. Buses are used in microprocessor integrated circuits to internally route address and data signals between blocks. For example, in response to an instruction, a microprocessor data register couples its contents onto a data bus and the data is received from the bus by an arithmetic logic unit.

In order to optimize the speed of the integrated circuit, it is generally necessary to preset or precharge the voltage level on the bus prior to the data transfer. Typically, each bus line is precharged to a logic high. Then when the data is transferred, each driver circuit connected to a bus line either maintains the precharged level of the bus line if the logic level to be provided is a logic high, or discharges the bus line if the logic level to be provided is a logic low. Therefore, the time it takes to discharge the bus line determines the speed. Furthermore, a control signal must be provided to enable a corresponding driver circuit so that the driver circuit can provide the voltage level on the bus line only at desired times.

The nature of a precharged bus creates limitations in the speed in which the driver circuit provides its data bit to a bus line. Because a bus routes groups of signals to different blocks which may be located on different sides of the integrated circuit, each bus line is relatively long and therefore may be modeled as a transmission line with a large distributed capacitance. In order for the driver circuit to discharge the bus quickly, the transistors in the driver circuit must also be large. However, the capacitance which the transistors add to the bus lines to which they are connected, and the capacitance which the transistors add to the data and control signals received on their gates, are both proportional to transistor size. Thus, for a particular driver circuit, the improvement in speed due to an increase in transistor size to discharge the bus faster, eventually equals the decrease in speed due to the increased capacitance added to the bus line and to the data and control signals. Therefore, no further improvement in speed is provided.

Accordingly, there is provided, in one form, a bus driver circuit comprising first, second, and third transistors. The first transistor has a first current electrode coupled to a data signal, a control electrode for receiving a control signal, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving the control signal, and a second current electrode coupled to a power supply voltage terminal. The third transistor has a first current electrode coupled to a bus line, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode coupled to the power supply voltage terminal.

These and other objects, features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 illustrates in partial schematic form a known bus driver circuit;

FIG. 2 illustrates a top view diagram of a portion of a data processor integrated circuit embodying two transistors of FIG. 1 in accordance with the prior art;

FIG. 3 illustrates in block form a data processor which uses the present invention; and

FIG. 4 illustrates in partial schematic form a CMOS bus driver circuit in accordance with the present invention.

FIG. 1 illustrates in partial schematic form a known bus driver circuit 20 connected to a bus line 25. Also shown in FIG. 1 are an N-channel transistor 26, a capacitor 27, a NAND gate 28, and an inverter 29. Circuit 20 comprises an N-channel transistor 21 having a drain connected to bus line 25, a gate connected to a node 30, and a source connected to a node 22; and an N-channel transistor 23 having a drain connected to the source of transistor 21, a gate for receiving a signal labelled "DATA", and a source connected to a power supply voltage terminal labelled "V.sub.SS ". Connected to bus line 25 is transistor 26 having a drain connected to a positive power supply voltage terminal labelled "V.sub.DD ", a gate for receiving a signal labelled "PRECHARGE", and a source connected to bus line 25. Capacitor 27 has a first electrode connected to bus line 25, and a second electrode connected to V.sub.SS. NAND gate 28 has a first input terminal for receiving a clock signal labelled "CLOCK", a second input terminal for receiving an enable signal labelled "ENABLE", and an output terminal. Inverter 29 has an input terminal connected to the output terminal of NAND gate 28, and an output terminal which is connected to node 30 and which provides a control signal labelled "CONTROL" thereon.

In operation, circuit 20 is a driver circuit for a capacitively loaded, logic high precharged bus. Capacitor 27 represents a distributed capacitance along bus line 25, rather than a discrete capacitor. Since bus line 25 is predominantly capacitively loaded, a small distributed resistance associated with bus line 25 is omitted for ease of illustration. Transistor 26 precharges bus line 25 during a precharge period. The precharge period occurs when signal PRECHARGE is asserted as a logic high. Since transistor 26 is an N-channel transistor connected to positive power supply voltage terminal V.sub.DD, the voltage on bus line 25 only rises to approximately an N-channel transistor threshold voltage below V.sub.DD. Subsequent to the precharge period, both signals CLOCK and ENABLE are asserted as a logic high, which cause signal CONTROL to be asserted and to enable circuit 20. The output terminal of NAND gate 28 is at a logic low, and the output terminal of inverter 29, node 30, is at a logic high. The voltage level on bus line 25 is then determined by signal DATA.

If DATA is a logic low, then transistor 23 is nonconductive, and the voltage on the source of transistor 22 rises until the gate-to-source voltage (V.sub.GS) of transistor 21 causes transistor 21 to no longer be conductive. The V.sub.GS at which transistor 21 becomes nonconductive is approximately a V.sub.GS threshold voltage of transistor 21. The voltage on bus line 25 remains at substantially the precharge voltage. If DATA is a logic high, however, transistor 23 becomes conductive, and the voltage on node 22 falls to approximately V.sub.SS. The V.sub.GS of transistor 21 is now greater than a threshold voltage, so transistor 21 also becomes conductive. The speed of circuit 20, measured from the assertion of signal DATA as a logic high to the assertion of a logic low on bus line 25, is determined by, among other things, the relative gate sizes of transistors 21, 23, and 26.

Several features of circuit 20 limit the speed at which a logic low may be driven onto bus line 25. Firstly, in order to increase the speed at which circuit 20 switches, transistors 21 and 23 must have large gate widths. However, as the gate widths of transistors 21 and 23 increase, both the surface area of the polysilicon connected to node 30 and the capacitance thereof increase. The effect of a large capacitance on node 30 is especially deleterious if signal CONTROL enables bus drivers for a large number of data bits. Secondly, as the gate width of transistor 23 increases, the capacitance on signal DATA increases, which increases the signal propagation time and slows the circuit. Thirdly, as the gate width of transistor 21 increases, the capacitance on bus line 25 also increases.

Fourth, circuit 20 has a charge sharing problem, due to the way transistors 21 and 23 are laid out. Transistors 21 and 23 collectively form a "two-stack" pair of transistors because the source of transistor 21 is shared with the drain of transistor 23. The common terminal is designated node 22. FIG. 2 illustrates a top view diagram of a portion 32 of an integrated circuit embodying transistors 21 and 23 of FIG. 1 in accordance with the prior art, and is laid out as a two-stack pair of transistors. Portion 32 shows a drain region 33, a polysilicon gate 34, a combined source/drain region 35, a polysilicon gate 36, and a source region 37. Drain region 33, polysilicon gate 34, and source/drain region 35 correspond to transistor 21 of FIG. 1; source/drain region 35, polysilicon gate 36, and source region 37 correspond to transistor 23 of FIG. 1. Source/drain region 35 itself corresponds to node 22 of FIG. 1. Neither a connection corresponding to the drain connection of transistor 21 to bus line 25 of FIG. 1, nor a connection corresponding to the source connection of transistor 23 to V.sub.SS, is shown in FIG. 2. Other features of portion 32 such as oxide and other conductor layers, which are not necessary to understand the charge sharing problem, are omitted. Returning to FIG. 1, the charge sharing problem occurs when driver 20 is enabled, but DATA is a logic low. Under this condition, there is charge sharing between the bus capacitance, modeled by capacitor 27, and the capacitance on source/drain region 35 shown in FIG. 2. The ratio of the capacitance on source/drain region 35 to the capacitance of capacitor 27 is critical to the operation of circuit 20. If the capacitance of capacitor 27 is relatively small, and if the bus is precharged to an N-channel precharge level (by transistor 26) which is already less than V.sub.DD, a transient reduction of the voltage on bus line 25 may occur because of the the charge sharing problem. If the reduction of voltage on bus line 25 is great enough, a failure occurs because an incorrect logic state is recognized on bus line 25.

Fifthly, inverter 29 must be added at the output of NAND gate 28 to provide the signal CONTROL as an active-high signal, since transistors 21 is an N-channel MOS transistor. Inverter 29 adds extra layout space. A known solution to the problems concerning the generation of signal CONTROL is to use a circuit known as a "bootstrap driver". The bootstrap driver circuit uses a charge pumping technique to increase a voltage at the gate of an N-channel pullup transistor above the positive power supply voltage. When the voltage on the gate is thus raised, the voltage on the source may rise to approximately the voltage on the drain, to provide a higher CONTROL voltage. However, in smaller device geometry processes, increasing a voltage on a transistor gate beyond a positive power supply voltage creates reliability problems in a thin oxide layer underneath a polysilicon gate. For smaller device geometries, the necessity of inverting the output of NAND gate 28 cannot be solved by using a bootstrap driver circuit.

FIG. 3 illustrates in block form a data processor 40 which uses the present invention. Data processor 40 comprises a CPU 41, a cache 42, an address bus 43, and a data bus 44. Other elements of data processor 40, such as control signals, blocks to couple address and data signals externally, and other functional blocks, are not shown in FIG. 3. CPU 41 is a central processing unit of data processor 40, and performs read and write accesses with memory (not shown). CPU 41 provides a plurality of address signals labelled "ADDRESS" to address bus 43, and receives a plurality of signals labelled "DATA" from data bus 44. Cache 42 is an on-chip high-speed memory provided to improve performance of data processor 40. Cache 42 receives a plurality of address signals labelled "CACHE ADDRESS" from address bus 43, and provides a plurality of signals labelled "CACHE DATA" to data bus 44.

Data bus 44 is a predominantly capacitively loaded bus which routes signals between cache 42 and CPU 41. While a data path only from cache 42 to CPU 41 is provided by data bus 44, in other embodiments other blocks may couple signals to data bus 44. Cache 42 comprises a plurality of bus driver circuits in accordance with the present invention (not shown in FIG. 3) which provide CACHE DATA to data bus 44.

FIG. 4 illustrates in schematic form a CMOS bus driver circuit 50 in accordance with the present invention. Also shown in FIG. 4 is a bus line 55, an N-channel transistor 56, a capacitor 57, and an inverter 58. Circuit 50 comprises a P-channel transistor 51, and N-channel transistors 52 and 53. Circuit 50 drives capacitively loaded bus line 55, which is precharged to a logic high. Transistor 51 has a source for receiving DATA, a gate, and a drain connected to a node 54. Transistor 52 has a drain connected to the drain of transistor 51 at node 54, a gate connected to a node 60, and a drain connected to V.sub.SS. Transistor 53 has a drain connected to bus line 55, a gate connected to the drain of transistor 51, and a source connected to V.sub.SS. Transistor 56 has a drain connected to V.sub.DD, a gate for receiving precharge signal PRECHARGE, and a source connected to bus line 55. Capacitor 57 represents a distributed capacitance along bus line 55, and has a first electrode connected to bus line 55, and a second electrode connected to V.sub.SS. NAND gate 58 has a first input terminal for receiving clock signal CLOCK, a second input terminal for receiving enable signal ENABLE, and an output terminal connected to node 60 for providing a signal labelled "CONTROL" thereon.

In operation, circuit 50 is enabled in the same manner as circuit 20 of FIG. 1, namely by the assertion of both signals ENABLE and CLOCK. Unlike circuit 20 of FIG. 1, however, when signals ENABLE and CLOCK are asserted, active-low signal CONTROL is asserted. When circuit 50 is disabled, a logic high on CONTROL makes transistor 52 conductive, which couples the gate of transistor 53 to approximately V.sub.SS to keep transistor 53 nonconductive. When circuit 50 is enabled, a logic low on CONTROL makes transistor 52 nonconductive. Transistor 51 may be conductive or nonconductive, depending on the logic state of DATA. If DATA is a logic low, transistor 51 remains substantially nonconductive. The voltage at the gate of transistor 53 is a logic low because any logic high voltage was previously discharged by transistor 52 when CONTROL was a logic high. If DATA is a logic high, transistor 51 is conductive, and provides a logic high on the gate of transistor 53. Transistor 53 becomes conductive, and couples bus line 55 to approximately V.sub.SS. In the illustrated embodiment, the gate (control electrode) size of transistor 51 is substantially smaller than the gate (control electrode) size of transistor 53, and the gate (control electrode) size of transistor 52 is substantially smaller than the gate (control electrode) size of transistor 53.

Circuit 50 improves the speed of circuit 20 of FIG. 1 by eliminating, or reducing the effect of, each of the problems previously described. Firstly, the size of transistor 51 may be much smaller than the size of transistor 21 of FIG. 1 because transistor 51 is not in the conduction path between bus line 55 and V.sub.SS. The smaller gate size of transistor 51 greatly reduces the capacitance on the CONTROL signal line, node 60. Secondly, transistors 21 and 23 of circuit 20 operate in series, but transistor 53 of circuit 50 alone discharges bus line 55. Thus the size of transistor 53 may be approximately half that of either transistor 21 or transistor 23 to obtain comparable speed, and the loading on DATA due to the capacitance of transistor 53 is approximately halved. Thirdly, since transistor 53 may be approximately half the gate size of either transistors 21 or 23, the capacitive loading on bus line 55 due to transistor 53 is approximately one-half that on bus line 25 due to transistor 21. Fourthly, the charge sharing problem which exists on node 22 between transistors 21 and 23 in FIG. 1, and as more particularly illustrated in FIG. 2, is eliminated, since circuit 50 has no nodes which bus line 25 may share capacitance with. Note also that while FIG. 4 shows N-channel transistor 56 precharging bus line 55, a different precharge scheme could be used. For example, a P-channel transistor could be used instead on transistor 56 to provide a higher precharge voltage. While precharging bus line 55 to a higher voltage would reduce the effect of the precharging problem, circuit 50 eliminates it. An additional benefit to eliminating the two-stack transistor pair is that a polysilicon gate of a single transistor may be easily laid out as a ring, with the source or drain connection inside the ring, to further reduce capacitance. Finally, transistor 51 is a P-channel transistor made conductive by a logic low, allowing the signal CONTROL to be developed from a logical NAND of signals CLOCK and ENABLE. P-channel transistor 51 eliminates the need for an extra level of inversion. Note that in some embodiments the speed of signal CONTROL is not critical, and other considerations may affect the generation of CONTROL. For example, the output of NAND gate 58 could be coupled to two inverters to buffer CONTROL.

It should be noted circuit 50 could be coupled to other types of signal lines instead of bus line 55. For example, circuit 50 could couple to a common signal line which is shared with one or more other circuits in a multiplexer. The common signal line differs from bus line 55 in that multiple driver circuits, which may be coupled to the common signal line, are physically close to one another. On the other hand, a typical bus line routes signals between distant parts of the integrated circuit. However, the common signal line of a multiplexer and bus line 55 share the characteristic of being predominantly capacitive loaded.

It should be apparent by now that a bus driver circuit which improves speed of providing a data signal on a predominantly capacitively-loaded bus line has been provided. The improvement results from five different sources of speed limitation, related to capacitive effects on different signal lines due to the large transistors needed in the prior art design. While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.