US 5,147,775 AGrant
Method of Fabricating a High-Frequency Bipolar Transistor
Issue Date:1992-09-15
•6 Claims
•4 Drawing Sheets
Abstract
A bipolar transistor with improved high-frequency performance is invented. The improvement is attained by eliminating a parasitic base-collector capacitance. The invented transistor is constructed upon a semi-insulating substrate, and wherein a region which underlies an extrinsic base region is semi-insulative such that the extrinsic base region does not substantially overlap the collector contact region and the collector region when viewed in the direction perpendicular to the substrate. Here, it's worthwhile to point out that a portion under the extrinsic base region is made completely semi-insulative down to the substrate. As a result, the transistor has substantially no parasitic base-collector capacitance. Also, a novel method, utilizing a self-align technique which uses a "first mask" for defining a collector contact region and a collector region, a "second mask" for defining an extrinsic base region, and a "third mask" determined by self-alignment using the first and the second mask for defining an emitter region, is disclosed to fabricate the bipolar transistor mentioned above.
Metadata
Assignee
- Matsushita Electric Industrial Co., Ltd.
Inventors
- Yorito Ota
- Masanori Inada
- Manabu Yanagihara
Application Information
Application Number:US 570958&
Filing Date:1990-08-21
Priority Date:1987-07-24
Art Unit:114
Classifications
IPC:
H01L 21265
Field of Search:
35743714834;5831;126;133DIG. 9;DIG. 10;DIG. 72
Patent Drawings (4 sheets)
Description
Background of the Invention
1. Field of the Invention
This invention relates to a transistor and more particularly to a high-frequency bipolar transistor, and to a method of fabricating the transistor.
2. Description of the Prior Art
A trend of semiconductor device technology is toward high speed and high frequency, as well as high integration. As is well-known, the high-frequency limitation of a bipolar transistor is usually described by the maximum oscillation frequency f.sub.max, which is expressed as follows:
where R.sub.b is the base resistance, C.sub.bc is the base-collector junction capacitance and t.sub.ec is the emitter-to-collector delay time. Since t.sub.ec also contains the term proportional to C.sub.bc, f.sub.max is especially sensitive to C.sub.bc. Accordingly, the reduction of C.sub.bc is essential to improve the high-frequency performance of a bipolar transistor. In the case of an emitter-top transistor whose emitter is located on top of the transistor, C.sub.bc is expressed by the sum of an intrinsic capacitance C.sub.bci and a parasitic capacitance C.sub.bcp, as follows:
The portion of a base region which underlies an emitter region is called an intrinsic base region, the rest of the base region, which is extended from the intrinsic base region, is called an extrinsic base region. Therefore, the intrinsic base region is an active region, and the extrinsic base region is an inactive region. C.sub.bci is the junction capacitance formed between the intrinsic base region and the collector region. C.sub.bcp is the junction capacitance formed between the extrinsic base region and the collector region. Reduction of C.sub.bci is, however, quite difficult because C.sub.bci is almost automatically determined by the requirement to realize a fundamental transistor action. Accordingly, the possible choice is limited to reduce C.sub.bcp.
Recently, AlGaAs/GaAs heterojunction bipolar transistors (HBT's) have been attracting much interest because of its outstanding possibilities for high-frequency devices. In such HBT's, the bandgap of a material of the emitter region is wider than that of a material of the base region, so that the emitter-base junction forms a heterojunction. The principal advantage of the HBT's over Si homojunction bipolar transistors is that sufficiently high base-doping is possible without sacrificing the emitter injection efficiency, because the minority carrier injection from the base region to the emitter region is suppressed by the wider emitter bandgap of the heterojunction. Accordingly, both the base width and R.sub.b can simultaneously be reduced. As is well-known, the reduction of the base width is especially effective to decrease the base transit time, which is generally the most important component of t.sub.ec. As a consequence, f.sub.max can be increased according to the formula (1). The other advantage is that the electron mobility of GaAs is faster than that of Si.
One of the conventional methods to reduce C.sub.bcp in HBT's is, as shown in FIG. 1, to introduce a semi-insulative region 20 between an extrinsic base region 21 and a collector contact region 11. (Ref. P. M. Asbeck, D. L. Miller, R. J. Anderson and F. H. Eisen, IEEE Electron Device Letters, vol. EDL-5, p. 310, 1984.) Here the semi-insulative region means that its resistivity is sufficiently high compared with those of n-type or p-type transistor regions. In the prior art cited above, a collector contact region 11 made of n.sup.+ -GaAs, a collector region 12 made of n-GaAs, a base region 13 made of p.sup.+ -GaAs, an emitter region 14 made of n-AlGaAs and an emitter contact region 15 made of n.sup.+ -GaAs are fabricated in this order on a semi-insulating (s. i.) substrate 10. Be.sup.+ is implanted in the extrinsic base region 21 to reduce R.sub.b. A collector electrode 17, double base-electrodes 18 and an emitter electrode 19 are formed upon the collector contact region 11, the extrinic base region 21 and the emitter contact region 15, respectively. The conduction property of the portion 20 sandwiched between the extrinsic base region 21 and the collector contact region 11 is changed from n-type to semi-insulative by 0.sup.+ implantation. Accordingly, C.sub.bcp is reduced as the base-collector junction is thus changed from p.sup.+ -n to p.sup.+ -i-n.sup.+.
In the above structure, however, the reduction of C.sub.bcp is limited to a certain extent, because the overlap between the extrinsic base region 21 and the collector contact region 11, which makes the p.sup.+ -i-n.sup.+ junction, still remains.
Summary of the Invention
An object of this invention is to improve the high-frequency performance of a emitter-top (collector-top) bipolar transistor by eliminating the parasitic capacitance C.sub.bcp (C.sub.bep) of a bipolar transistor.
This object is accomplished by a transistor which is constructed upon a semi-insulating substrate and wherein the region which underlies the extrinsic base region is semi-insulative such that the extrinsic base region does not substantially overlap the collector (emitter) contact region and the collector (emitter) region when viewed in the direction perpendicular to the substrate. Here, it's worthwhile to point out that a portion under the extrinsic base region is made completely semi-insulative down to the substrate. As a result, the transistor has substantially no parasitic capacitance C.sub.bcp (C.sub.bep).
Another object of this invention is to provide a novel method which fabricates the bipolar transistor mentioned above.
This object is accomplished in a self-align technique which uses a "first mask" for defining the collector (emitter) contact region and the collector (emitter) region, a "second mask" for defining the extrinsic base region, and a "third mask" determined by self-alignment using the first and second masks for defining the emitter (collector) region.
Brief Description of the Drawing
FIG. 1 is a cross-sectional view of a conventional GaAs bipolar transistor.
FIG. 2 is schematic views of an emitter-top GaAs bipolar transistor improved with this invention; (a) is a top view of the transistor seen in the direction perpendicular to a substrate; (b) is a cross-sectional view of the same transistor cut at A--A'; (c) is a cross-sectional view of the same transistor cut at B--B'.
FIG. 3 shows schematic self-aligned processing steps of this invention, where the viewpoints of (a-), (b-) and (c-) correspond to those of (a), (b) and (c) of FIG. 2, respectively.
FIGS. 4, 5 and 6 show the top views of three variations of the GaAs bipolar transistors improved with this invention.
FIG. 7 is a cross-sectional view of a collector-top GaAs bipolar transistor improved with this invention.
Description of the Preferred Embodiments
The transistor improved with the present invention is shown FIG. 2, taking up an emitter-top HBT with double base-electrodes and double collector-electrodes as an embodiment.
The transistor is constructed upon a semi-insulating substrate 10. A collector contact region 11, a collector region 12, an intrinsic base region 13, an emitter region 14 and an emitter contact region 15 are formed on the substrate 10 in this order. An extrinsic base region 21 is formed on a first semi-insulative region (1st. 0.sup.+) 31. A second semi-insulative region (2nd. 0.sup.+) 32 is formed around the extrinsic base region 21. Double collector-electrodes 17, double base-electrodes 18 and an emitter electrode 19 are formed on the collector contact region 11, the extrinsic base region 21 and the emitter contact region 15, respectively. Here, to reduce both the collector resistance R.sub.c and the base resistance R.sub.b, both the collector electrodes 17 and the base electrodes 18 are divided into two portions arranged at both sides of the emitter region 14.
A fabrication method of the transistor is described along FIG. 3. The method, utilizing self-align technique, is especially suitable for realizing the proposed transistor. The process steps are as follows.
First of all, a multilayer structure is constructed by means of, for example, molecular-beam epitaxy. This multilayer structure comprises an n.sup.+ -GaAs (e.g., 5.times.10.sup.18 cm.sup.-3 doped, 0.5 .mu.m thick) collector contact layer, an n-GaAs (e.g., 5.times.10.sup.16 cm.sup.-3 doped, 0.4 .mu.m thick) collector layer, a p.sup.+ -GaAs (e.g., 2.times.10.sup.19 cm.sup.-3 doped, 0.1 .mu.m thick) base layer, an n-AlGaAs (e.g., 1.times.10.sup.18 cm.sup.-3 doped, 0.2 .mu.m thick) emitter layer and an n.sup.+ -GaAs (e.g., 5.times.10.sup.18 cm.sup.-3 doped, 0.1 .mu.m thick) emitter contact layer, which are stacked on a semi-insulating GaAs substrate 10 in this order. This initial structure is not shown in FIG. 3.
Then, in order to define a collector contact region 11 and a collector region 12, the portions 31 of the collector contact layer and the collector layer are changed semi-insulative by deep-implanting 0.sup.+ (e.g., 1.times.10.sup.15 cm.sup.-2 dosed at an energy of 500 keV) from the surface of the multilayer structure, using SiO.sub.2 1 (e.g., 2 .mu.m thick) as a mask (see FIG. 3 (a-1), (b-1) and (c-1)). For convenience, the portion 31 is called "first 0.sup.+ -implanted region", and the mask made of SiO.sub.2 1 is called "first mask". Accordingly, the initial collector contact layer and collector layer are divided into the collector contact region 11, the collector region 12 and the first 0.sup.+ -implanted region 31. The transistor region with the highest resistivity, that is the collector region 12, shows resistivity of about 0.03 .OMEGA..multidot. cm, whereas the semi-insulative region 31 prepared according to the above condition shows the resistivity of about 10.sup.5 .OMEGA..multidot. cm, which is in fact sufficiently higher than the former.
After that, to reduce an extrinsic base resistance, the region 21 upon the first 0.sup.+ -implanted region 31 is ion-implanted with Be.sup.+ (e.g., 1.times.10.sup.14 cm.sup.-2 dosed at an energy of 100 keV), again using the first mask 1, as shown in FIG. 3 (a-1), (b-1) and (c-1). The region 21 becomes p-type by this Be.sup.+ implantation. Part of the region 21 is to become an extrinsic base region 21 in the next step. Here, it's worthwhile to point out that a portion under the region 21 has been made completely semi-insulative down to the substrate 10 (see FIG. 3 (a-2), (b-2) and (c-2)).
As a next step, the extrinsic base region 21 in which Be.sup.+ has been implanted is defined as follows. The second mask 2 made of Al (e.g., 1 .mu.m thick) is formed on top of the multilayer structure, which crosses over the first mask 1 as shown in FIG. 3 (a-2). Then the part of the first mask 1 which is not covered with the second mask 2 is removed by dry etching (e.g., reactive ion etching of CHF.sub.3). After that, the portion 32 which is not covered with the second mask 2 is changed semi-insulative by shallow-implanting 0.sup.+ (e.g., 1.times.10.sup.15 cm.sup.-2 dosed at an energy of 200 keV). For convenience, the portion 32 is called "second 0.sup.+ -implanted region".
As a next step, an emitter region 14 and an emitter contact region 15 are defined with self-alignment technique as follows. Removing the second mask 2 by wet etching (e.g., HCl), SiO.sub.2 3 is exposed as shown in FIG. 3 (a-3). The SiO.sub.2 3 is the part of the first mask 1 which have been covered with the second mask 2. Then the initial emitter layer and emitter contact layer are removed by wet etching (e.g., H.sub.2 SO.sub.4 :H.sub.2 O.sub.2 :H.sub.2 O=1:1:12) using the SiO.sub.2 3 as a mask (see FIG. 3 (a-3), (b-3) and (c-3)). For convenience, the SiO.sub.2 3 is called "third mask". As is described above, the shape of the third mask is determined by the first and second mask, that is, determined by self-alignment. This self-alignment ensures the extrinsic base region 21 not to overlap the collector contact region 11 and the collector region 12 at all. As a result, the parasitic capacitance C.sub.bcp can be substantially eliminated.
After removing the third mask 3 by wet etching (e.g., HF), the sample is annealed (e.g., 800.degree. C. for 10 seconds) to recrystallize all of the implanted regions 21, 31 and 32.
Then, the collector, emitter and base electrodes are formed in this order. Via holes 40 reaching the collector contact region 11 are first formed by wet etching using photoresist 4 as a mask, as shown in FIG. 3 (a-4), (b-4) and (c-4). Then evaporating AuGe/Ni/Au and using lift-off technique by resist 4, the double collector-electrodes 17 are formed upon the collector contact region 11. The emitter electrode 19 is next formed upon the emitter contact region 15 by evaporating the same metal and using lift-off technique. After alloying the electrodes 17 and 19 with heat treatment, the double base-electrodes 18 are last formed upon the extrinsic base region 21 by evaporating AuZn/Au and using lift-off technique (see FIG. 3 (a-5), (b-5) and (c-5)).
In case that the transistor described above is applied to integration circuits, each of the electrodes 17, 18 and 19 is led to an outer area by multi-level metallization technique.
The HBT improved with this invention is easily fabricated with the self-aligned process as described above. The structure and the process have the following advantages: (1) the invented transistor has substantially no base-collector parasitic capacitance C.sub.bcp ; (2) the above fabrication method utilizes simple but useful self-alignment technique, owing to which the extrinsic base region 21 does not substantially overlap the collector contact region 11; (3) excessive device isolation process for integration circuits needs not be formed because each transistor area is defined by the first mask and the second mask in this process; (4) the layout scheme of the base and the collector electrodes can be set up freely.
FIGS. 4, 5 and 6 show top views of other layout schemes of those electrodes. The HBT shown in FIG. 4 has a single collector-electrode. This transistor has an advantage that each of the electrodes can be directly led to an outer area without multi-level metallization technique. The HBT shown in FIG. 5 has a single collector-electrode 17 and a single base-electrode 18. In this transistor, the base electrode 18 which surrounds the emitter contact region 15 is very effective to reduce R.sub.b. The HBT shown in FIG. 6 has an single collector-electrode 17 and an single base-electrode 18, which both surround the emitter contact region 15. The scheme of this transistor enables to reduce the R.sub.c and R.sub.b even if adopting a single electrode configuration.
In the previously-mentioned process, the Be.sup.+ -implanting step is not necessary if the conditions of the first deep 0.sup.+ -implanting are decided such that this implantation does not affect the extrinsic base region. Also, the implanting ions other than 0.sup.+ and Be.sup.+ may be used. For example, B.sup.+, H.sup.+, N.sup.+ or Cr.sup.+ may be used to form the semi-insulative region in place of 0.sup.+, and Mg.sup.+, Zn.sup.+ or C.sup.+ may be used to form a p-type region in place of Be.sup.+. The conditions of ion implanting and annealing depend on the kind of the implanting ions and on the thickness and doping of the multilayer structures.
The HBT may be fabricated by other method than that described above. For example, the extrinsic base region may be delineated by wet etching, instead of the second 0.sup.+ -implanting.
The previously-mentioned structure and process can be applied to a homojunction bipolar transistor without any alteration, and also to a collector-top transistor whose collector is located on top of the transistor. In the collector-top transistor, the reduction of the parasitic base-emitter capacitance C.sub.bep becomes important, just like the reduction of the parasitic base-colletor capacitance C.sub.bcp was important in the emitter-top transistor.
FIG. 7 shows another embodiment of the present invention applied to a collector-top transistor. An emitter contact region 15, an emitter region 14, a base region 13, a collector region 12 and a collector contact region 11 are formed on a semi-insulating substrate 10 in this order, and a first 0.sup.+ -implanted region 31, a second 0.sup.+ -implanted region 32 and a Be.sup.+ -implanted region 21 are also formed by the self-aligned process described above. That is, in the description of the process made in connection with FIG. 2 and FIG. 3, the terms "emitter" and "collector" may be changed to "collector" and "emitter", respectively, to form the transistor shown in FIG. 7. Obviously, C.sub.bep is essentially eliminated with the concept of the present invention.
Claims
What is claimed is:
1. A method of fabricating a bipolar transistor comprising the steps of: 1) forming a multilayer structure by sequentially stacking on a semi-insulating substrate, a collector contact layer, a collector layer, a base layer, and an emitter layer in this order; 2) forming a first mask on a part of the multilayer structure; 3) changing the collector contact layer and the collector layer to be a first semi-insulative region by a deep ion-implantation at portions except for portions below the first mask so that the portions of the collector contact layer and the collector layer below the first mask become a collector contact region and a collector region, respectively; 4) forming a second mask on a part of the multilayer structure to partly overlap a part of the first mask; 5) removing the first mask except for the part overlapped with the second mask; 6) changing the base layer to be second semi-insulative region by a shallow ion-implantation at a portion except for a portion below the second mask so that the portion of the base layer below the second mask becomes a base region having an extrinsic base region formed on the first semi-insulative region; 7) removing the second mask so that the part of the first mask which was overlapped with the second mask remains as a third mask; 8) etching off the emitter layer at a portion except for a portion below the third mask so that the portion of the emitter layer below the third mask remains as an emitter region; and 9) removing the third mask.
2. The method of claim 1, wherein the bandgap of a material of the emitter layer described in the step 1) is wider than that of a material of the base layer.
3. The method of claim 1, further comprising, between the step 3) and step 4), an additional step of implanting ions into the extrinsic base region upon the first semi-insulative region such that the resistance of said extrinsic base region is reduced.
4. A method of fabricating a bipolar transistor comprising the steps of: 1) forming a multilayer structure by sequentially stacking on a semi-insulating substrate, an emitter contact layer, an emitter layer, a base layer, and a collector layer in this order; 2) forming a first mask on a part of the multilayer structure; 3) changing the emitter contact layer and the emitter layer to be a first semi-insulative region by a deep ion-implantation at portions except for portions below the first mask so that the portions of the emitter contact layer and the emitter layer below the first mask become an emitter contact region and an emitter region, respectively; 4) forming a second mask on a part of the multilayer structure to partly overlap a part of the first mask; 5) removing the first mask except for the part overlapped with the second mask; 6) changing the base layer to be a second semi-insulative region by a shallow ion-implantation at a portion except for a portion below the second mask so that the portion of the base layer below the second mask becomes a base region having an extrinsic base region formed on the first semi-insulative region; 7) removing the second mask so that the part of the first mask which was overlapped with the second mask remains as a third mask; 8) etching off the collector layer at a portion except for a portion below the third mask so that the portion of the collector layer below the third mask remains as a collector region; and 9) removing the third mask.
5. The method of claim 4, wherein the bandgap of a material of the emitter layer described in the step 1) is wider than that of a material of the base layer.
6. The method of claim 4, further comprising, between the step 3) and the step 4), an additional step of implanting ions into the extrinsic base region upon the first semi-insulative region such that the resistance of said extrinsic base region is reduced.
Patent Citations (7)
Non-Patent Literature (2)
- AlGaAs/GaAs Heterojunction Bipolar Transistors with Small Size Fabricated by a Multiple Self-Alignment Process Using One Mask IEEE Transactions on Electron Devices, vol. ED-34 No. 12, Dec. 1987.
- GaAs/(Ga, Al) As Heterojunction Bipolar Transistors with Buried Oxygen-Implanted Isolation Layers IEEE Electron Device Letters, vol. EDL-5, No. 8, Aug. 1984.