Converter Comparator Cell With Improved Resolution

The present invention relates to analog-to-digital converters and more specifically to an improved comparator circuit for use in analog-to-digital converters.

The comparator circuit of an analog-to-digital converter includes an input signal compared against a reference signal and subsequently digitized. One form of analog-to-digital conversion includes a flash quantization. As illustrated in FIG. 1, a parallel string of comparators is used to compare the analog input voltage directly to voltage steps on a resistive ladder. The results of the comparison are provided to a latch which indicates whether the output of the comparator is high or low. These results are then decoded by a tap detection logic or decoder and provided as digital output signals. A typical single latch configuration of the prior art is illustrated in FIG. 1.

A flash converter is rapid because the signal is propagated in parallel connected comparators and decoding logic. As a tradeoff, the flash converter is more complex requiring a greater number of comparators, a decoding logic dependent upon the number of bits and an input resistor string.

As discussed in U.S. Pat. No. 4,691,189 to Dingwall, et al, single latch circuits may provide erroneous results. The Dingwall, et al patent suggests using a D type master-slave flip-flop (DMSFF) following a two stage autozero comparator. The use of DMSFF gives poor resolution since the threshold of the first D latch stage varies with the processing temperature and supply voltage. The same clock that is used in the autozero comparator is used in the DMSFF latches.

Thus it is an object of the present invention to provide a flash converter with improved accuracy and resolution.

Another object of the present invention is to provide a flash converter whose resolution is independent of processing and temperature induced changes.

These and other objects are achieved by providing a comparator circuit wherein the circuit includes a comparator for comparing the input signal to the reference signal, a sense amplifier connected to the output of the comparator for sensing and providing an amplified signal and an output circuitry connecting the output of the sensed amplifier for receiving and latching the amplified signal. The comparator would include a two-stage autozero comparator. The sense amplifier includes a differential amplifier having a first input connected to the output of the comparator and a second input connected to a second reference signal. A reference signal generator would produce the second reference signal. The output stage of the reference signal generator would match the output stage of the comparator. Thus the sense amplifier will not be affected by processing or temperature variations since the reference signal generated will track the output of the comparator stage. The sense amplifier would include input and output buffer circuits. The sense amplifier minimizes loading on the autozero comparator stage and achieves the speed of a D-type latch while providing greater accuracy and resolution since true differential amplification is taking place.

The output stage of the comparator would include a decoder having its input connected to the output of the sense amplifier and a latch connected to the output of the decoder. By providing the decoding after the sense amplifier and before the latch circuitry, the delay of the latch circuitry occurs after the decoding. The latch circuitry preferably is a DMSFF so as to provide a valid output for the entire clock period instead of the validity for only half the clock period as would be true if using a single D-latch. A clock signal is used to control the comparator circuits while a strobe signal is used to control the sense amplifier and latches. This provides independent control of the input sampling and holding as well as the subsequent signal processing. The strobe signal leads the clock signal with respect to phase.

When a plurality of the comparator circuits is used in a flash analog-to-digital converter, a common second reference signal generator may be used for one or more of the comparators. Thus for example, each row column may include its own reference signal generator.

Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of a flash analog to-digital converter of the prior art;

FIG. 2 is a schematic of a flash analog-to-digital converter according to the principles of the present invention;

FIG. 3 is a detailed schematic of a comparator according to the principles of the present invention;

FIG. 4 is a schematic of the decoding logic and latch circuit according to the principles of the present invention;

FIG. 5 is a timing diagram according to the principles of the present invention.

As illustrated in FIG. 2, the input signal is provided to a plurality of parallel comparators wherein they are compared to voltage steps on a resistive ladder. As in the prior art of FIG. 1, preferably the comparators are autozero comparators. The output of the comparators are provided respectively to a first input of a plurality of parallel sense amplifiers. A second input of the sense amplifier is from a reference generator. The reference generator may be the same for all the comparators or one or more reference generators may be connected to a group of sense amplifiers. As will be discussed with respect to FIG. 3, the output stage of the reference generator is identical to the output stage of the last autozero stage of the comparator circuit. This increases the resolution of the comparator since true differential amplification is produced by the sense amplifier. Also as will be discussed with respect to FIG. 3, the sense amplifier includes a source following stage to minimize loading on the autozero comparators.

The output of the sense amplifier is connected directly to the tap detection or decoding logic. The decoded output is then provided to the latches. This is a reversal of the signal processing of the output signals from that of FIG. 1 of the prior art. As in the Dingwall U.S. Pat. No. 4,691,189 the output latch is preferably a D-type master-slave flip-flop (DMSFF). By providing the decoding logic of adjacent cells after the sense amplifier and before the DMSFF, one stage of delay is removed from the decoding process. Also, by selecting the output latch to be a DMSFF, a valid output for the entire clock period is provided instead of the validity for only half of a clock period as in D-type latches. This is necessary to achieve high clock rates.

As illustrated in FIG. 3, the comparator includes an input stage having transmission switches P1, N1 and P2, N2 providing the input signal VIN and the reference signal VRN for the particular stage to a first capacitor Cl. A clock signal CLK is connected to P1 and N2 and the inverse clock signal CLKB is connected to N1 and P2. Thus the transmission switches P1, N1 and P2, N2 are out of phase. The resulting difference signal on capacitor C1 is provided to an inverter P4, N4 having a transmission gate P3, N3 which provide the autozeroing capability. The output of the first inverter P4, N4 is provided to a second capacitor C2 which is connected to the input of a second inverter P6, N6. A transmission switch P5, N5 connects the input and output of the inverter P6, N6 and also provides autozeroing. The transistors P3, N3 and P5, N5 of the transmission gates are driven by CLK and CLKB signals such that they are both on during the same phase of the clock's signal. The operation of the autozero comparators is well known and is described in the U.S. Pat. No. 4,691,189.

The output of the autozero comparator stage is provided to a sense amplifier illustrated in FIG. 3. The sense amplifier includes parallel connected amplifier transistors P7 and P8 having regenerative active loads N7 and N8 in series therewith. Enable switch N9 having its gate controlled by the strobe signal STR activates the sense amplifier P7, P8, N7, N8. Sense amplifier transistor P7 is connected to the output stage P6, N6 of the comparators by a buffer including series connected transistors N10, N11. The gate of N11 is connected to the output of the last stage P6, N6 of the comparator. The gate of transistor of N10 of the input buffer is connected to a reference value VREF produced by reference generator P14, N14. The reference signal VREF is also connected to the transistor P8 through an input buffer N12, N13.

The transistors P14 and N14 are matched to P6 and N6 such that the reference signal provided to P8 is matched for processing variation and temperature to the output stage P6, N6 of the comparator. Thus the reference voltage is matched to the autozero comparator output voltage regardless of temperature and processing variations. The reference generator P14, N14 provides a reference signal which is proportional to the geometrical relationship of P14 to N14. This reference value through input buffers N12 and N13 maintains P8 at the desired switching point. Since the reference voltage is also applied to N10, input to P7 is a function of the output signal of the comparators and to gate of N11. By matching transistors N10, N11, N12 and N13, the inputs are completely balanced to the differential sense amplifiers P7 and P8. This allows accurate switching of the differential sense amplifier P7, P8. The output of the sense amplifier is from the drains of P7 and P8 through output buffer P15, N15 as QN and P16, N16 as QBN.

When the strobe signal STR is low, N9 is off. This allows A and B to charge up to the positive power supply VDD. As the strobe signal STR goes high, the differential signal is applied by P7 and P8 into the regenerative active loads N7 and N8. The voltages of nodes A and B will then charge to the appropriate and complementary output values which are buffered and inverted by the buffers P15, N15 and P16, N16.

As illustrated in FIG. 5, the strobe signal STR leads in phase the clock signal CLK by a delay TD. Thus the strobe signal STR rises before the clock signal CLK to ensure sensing of a valid comparator output. The time delay TD must be non-zero. This allows all the switches in the autozero comparators to be clocked with a single clock signal, either CLK or its complement CLKB. Thus delayed and non-overlapping clock signals are avoided in the autozero comparator stages. This allows shorter clock periods and faster clock rates.

The output QN and QBN of each comparator and strobed sense amplifier stage are provided to a three-input NOR gate for decoding as illustrated in FIG. 4. The three-input NOR gate includes transistors P20, P21, P22 and N20, N21, N22. The inputs for three adjacent stages include QBN-1, QBN and QN+1.

The output of the NOR gate is provided to a D-type master-slave flip flop (DMSFF). The first stage of the master-slave flip-flop includes a transmission gate P23, N23 connected to an inverter P24, N24. The output of inverter P24, N24 is latched by a feedback including feedback inverter P25, N25 and transmission switch P26, N26. The output of the latch P24, N24 is provided to transmission switch P27, N27 to the second latch P28, N28. A feedback inverter P29, N29 and transmission switch P30, N30 latch the inverter P28, N28. The output of a latch stage N28, P28 is the digital data signal DN.

The transmission switches of the DMSFF are controlled by the strobe STR and the complementary strobe signal STRB. The transmission switches of the first stage are out of phase with the transmission switches of the second stage. The timing interrelationship of the operation of the two stages is described in U.S. Pat. 4,691,189.

As with the sense amplifier, by using the strobe signal instead of the clock signal, the switches of the autozero comparator can be clocked with a single signal and delay and non-overlapping signals are avoided. This allows shorter clock periods and faster clock rates. By providing the adjacent cell decoding logic after the sense amplifier and before the DMSFF, one level of switching delays before decoding is eliminated. Also the use of a DMSFF allow a valid output for an entire clock period instead of a valid output for only half the clock period as would be the case with a single D-latch. This also allows the use of higher clock rates.

Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only, and is not to be taken by way of limitation. The spirit and scope of the present invention are to be limited only by the terms of the appended claims.