Apparatus for Forming Composite Images

1. Field of the Invention

The present invention relates to a panorama photographing device having an electronic viewfinder, such as a camera.

2. Related Background Art

Conventionally, panoramic photography has required a photographer to remember the position of the juncture between adjacent sections of an object or scenery which are to be photographed in successive frames of pictures. It has also been necessary to fix the camera by, for example, a tripod. It is very troublesome to remember the juncture between adjacent object sections. In addition, it is very difficult to smoothly connect the successive shots because the photographer has to compose the panoramic image in such a manner that the juncture which is on one end. e.g., right end, of the picture frame photographed has to be located on the other end, e.g., left end, of the picture frame in the next shot. This problem is serious particularly when the object to be photographed is a monotonous one having no particular characteristic as in the case of a landscape. In such a case, the photographer encounters difficulty in smoothly connecting the successive images If the photographer has forgotten the position of the juncture, he has to repeat the photographing from the beginning, i.e., from the first object section. In some cases, panoramic photography requires the photographer to connect images not only in the horizontal direction but also in the vertical direction. It is not easy to obtain a smooth connection of images both horizontally and vertically without the aid of a tripod. Namely, panoramic photography may fail even with a slight change in the position of the camera held by the photographer.

Accordingly, an object of the present invention is to provide a panorama photographing device improved in such a way as to obviate these problems of the prior art.

To this end, according to the present invention, there is provided a panorama photographing device comprising: display means for displaying an image to be photographed; memory means for storing data concerning an image which has been already photographed; and control means for enabling the display means to display, substantially simultaneously, both the image to be photographed and the image already photographed and stored in the memory means.

With this arrangement, the image which has been already photographed and the image which is to be photographed subsequently are simultaneously displayed so as to enable the photographer to smoothly connect both images thereby ensuring high quality of the panorama photograph.

In a further aspect of the invention, there is provided display means, imaging means, memory means and control means. The display means is arranged to display an image of an object. The imaging means generates image signals corresponding to the object. The memory means stores the image signals generated by the imaging means. The control means causes the display means to simultaneously display (1) at least a portion of the image which corresponds to the stored image signals, and (2) at least a portion of a subsequent image.

In yet a further aspect of the present invention, there is provided imaging means, memory means, display means, and control means. The imaging means converts a first image into an image signal. The memory means stores the image signals, and the display means displays a second image which is substantially a real-time image. The control means causes the display means to simultaneously display (1) at least a portion of the first image, that portion derived from the image signal stored in the memory means, and (2) the second image.

The above and other objects, features and advantages of the present invention will become clear from the following description of the preferred embodiments when read in conjunction with the accompanying drawings.

FIG. 1 is a perspective view of a camera;

FIG. 2 is a circuit diagram of a principal circuit incorporated in the camera shown in FIG. 1;

FIGS. 3(a) and 3(b) are illustrations of a first example of a display on the camera shown in FIG. 1;

FIGS. 4(a) and 4(b) are illustrations of horizontal addresses of successive images corresponding to FIGS. 3(a) and 3(b);

FIGS. 5(a), 5(b) and 5(c) are illustrations of a second example of the display on the camera shown in FIG. 1;

FIGS. 6(a), 6(b) and 6(c) are illustrations of a third example of the display on the camera shown in FIG. 1;

FIG. 7 is a circuit diagram of a circuit for forming the image on display as shown in FIG. 6;

FIGS. 8(a) and 8(b) are illustrations of a fourth example of the display on the camera shown in FIG. 1;

FIG. 9 is a circuit diagram of a circuit for forming the image on display as shown in FIG. 8;

FIG. 10 is an illustration of a fifth example of the display on the camera shown in FIG. 1;

FIG. 11 is a circuit diagram of a circuit for forming the image on display as shown in FIG. 10;

FIGS. 12(a) and 12(b) are illustrations of a sixth example of the display on the camera shown in FIG. 1;

FIG. 13 is an illustration of a circuit for forming the image on display as shown in FIG. 12;

FIG. 14 is an illustration of a seventh example of the display on the camera shown in FIG. 1;

FIG. 15 is an illustration of an eighth example of the display on the camera shown in FIG. 1;

FIG. 16 is an illustration of a ninth example of the display on the camera shown in FIG. 1;

FIG. 17 is an illustration of a tenth example of the display on the camera shown in FIG. 1; and

FIG. 18 is an illustration of another circuit which incorporates a microcomputer.

FIG. 1 shows a camera incorporating a panorama photographing device in accordance with the present invention. In the following description, the same reference numerals are used to denote the same parts or elements. The camera shown in FIG. 1 has a camera body 1, a release button 2, a display device 3, a left scroll switch button 4, a right scroll switch button 5, and a lens 6 for focusing an image on a photographic film or on an imaging device.

FIG. 2 illustrates an example of a circuit incorporated in the camera. The circuit has an imaging address generating device 404 which generates and then superimposes electrical signals, in the form of image addresses, on the image signal imaged by the imaging device 401. The image signals are converted into digital signals by an A/D (Analog-to-Digital) converter 402 and these digital signals are stored in RAMs (Random Access Memory) 403. There are 36 RAMs, RAM1 to RAM36 which are adapted to be selected by a RAM selecting device 411 in accordance with information given by a film counter 412.

The image signals stored in the RAMs 403 are delivered to D/A (Digital to Analog) converter 409 and the analog signals output from the D/A converter 409 are displayed at a position on display device 410 designated by the address generated by the display address generating device 406. A phase control device 405 operates to provide a phase difference between the displayed address and the imaging address so that the display device 410 displays the image as if the start address has been materially changed, as will be explained later in connection with FIG. 4. The phase control device 405 delivers a signal to the RAM select device 411 to enable the display device 410 to display the data in the next or adjacent RAM 403 in accordance with the address information as will be explained later, whereby display images as shown in FIGS. 3(a) and 3(b) are obtained.

The switches 407 and 408 shown in FIG. 2 are selection switches which enable the photographer to select either a rightward panorama mode or a leftward panorama mode, whereby a display image as shown in FIG. 3(a) or a display image as shown in FIG. 3(b) is obtained.

FIGS. 3(a) and 3(b) illustrate an example of the display obtained in the camera shown in FIGS. 1 and 2. The display as shown in FIG. 3(a) is obtained when the rightward panorama mode has been selected through the manipulation of the switch 407. In this case, only the hatched area of the n-TH picture frame showing the previously photographed image is shown at the left end of the frame now appearing in the viewfinder, whereas the image to be photographed next, i.e., the object section to be photographed on the (n+1)TH picture frame is dynamically displayed on the right portion of the frame now appearing in the viewfinder. The photographer therefore can precisely join the image on the n-TH picture frame and the image on the (n+1)TH frame at the expected juncture. Although the rightward panorama mode has been described, the user can equally select the leftward mode in which the camera is swung from right to left, by operating the leftward panorama switch 408. In such a case, the hatched left end portion of the picture on the n-TH frame is displayed on the right end of the frame now appearing in the viewfinder, while the hatched area of the (n+1)TH frame is displayed on the left end of the viewfinder, whereby panoramic photographing of the image is possible by swinging the camera from the right to the left.

FIGS. 4(a) and 4(b) show the horizontal addresses of the n-TH and (n+1)TH images displayed in the viewfinder, corresponding to the display images shown in FIGS. 3(a) and 3(b), respectively.

Referring first to FIG. 4(a), it is assumed here that a single image has horizontal addresses extending from 00.sub.H to FF.sub.H. In such a case, the display as shown in FIG. 3(a) can be obtained by displaying, in the address region 00.sub.H to 3F.sub.H on the viewfinder, the image of the n-TH frame addressed between CO.sub.H to FF.sub.H, while displaying the portion of the image of the (n+1)TH frame between the addresses 00.sub.H to BF.sub.H on the region of the viewfinder addressed between 40.sub.H and FF.sub.H. The display as shown in FIG. 3(b) can be obtained in a similar manner by making use of the address information as shown in FIG. 4(b).

From these facts, it is understood that the display as shown in FIGS. 3(a) and 3(b) can be obtained by suitably shifting the address information.

FIGS. 5(a), 5(b), and 5(c) illustrate a second example of the display. In this case, entire portions of two adjacent images are displayed in a side-by-side relation on a frame in the viewfinder. More specifically, in this example, data are read from alternating RAMs 403 both in the vertical and horizontal directions by the operation of the address generating device 404 in the circuit of FIG. 2, and the phase shift device 405 and the RAM select device 411 are suitably operated such that the start addresses for the n-TH frame and the (n+1)TH frame are set in a manner corresponding to the display shown in FIGS. 5(a), 5(b) and 5(c) causing the display address generating device 406 to designate the vertical range of the display address.

FIGS. 6(a) to 6(c) illustrate a third example of the display. In contrast to the display of FIGS. 3(a) and 3(b) in which the phase difference is fixed, the example shown in FIGS. 6(a), 6(b) and 6(c) enables the size or area of display of the image of the preceding picture frame to be varied by scrolling the images progressively from the state of FIG. 6(a) to the state of FIG. 6(b) and then to the state of FIG. 6(c) by means of the buttons 4 and 5 shown in FIG. 1. Thus, the image to be photographed in the next frame, i.e., (n+1)TH frame, is dynamically displayed on the right portion of the area in the viewfinder, whereas the static image which has been photographed in the preceding frame, i.e., n-TH frame, is shown on the left portion of the area in the viewfinder.

The display as shown in FIGS. 6(a) to 6(c) can be realized by, for example, a circuit which will be described hereinunder with reference to FIG. 7.

The object image is converted into image signals by the imaging device 401 which are processed by the A/D converter 402 to become digital signals. These digital signals are input to the DI terminals of the RAMs 703 to 705. RAMs 703 to 705 comprise the RAM 403 explained before. Actually, there are many RAMs corresponding in number to the number of the frames of the photographic film, although only some of them are shown. The vertical transfer clock pulses .phi.V for the imaging device 401 are counted by a vertical address counter 717 so as to transfer the vertical addresses to the imaging device 401 and to the RAMs 703 to 705. The counter 717 is adapted to be reset by a vertical blanking signal VD when a predetermined number of transfer clock pulses oV have been counted. Similarly, the horizontal transfer clock pulses oH for the imaging device 401 are counted by a horizontal address counter 718 so as to transfer the horizontal addresses to the imaging device 401 and to the RAMs 703 to 705. The counter 717 is adapted to be reset by a horizontal blanking signal HD when a predetermined number of transfer clock pulses oH have been counted.

The film counter 412 delivers a signal representing the number of frames of the photographic film. In response to this signal, the decoder 715 delivers a signal to the WE terminals of the RAMs 703 to 705 so that one of the RAMs 703 to 705 is selected into which the image signals from the imaging device are delivered. The content of the film counter 412 is incremented by one in response to the exposure timing signal delivered by a shutter control device 729 so that the output of the decoder 715 is switched, whereby the image data is recorded in the form of a still image in the RAM which was selected by the decoder 715. The present image data are successively delivered to the D/A converter 409 through the RAMs so as to be converted into analog signals and are dynamically displayed on the display device 410 as the present image.

The RAM from which the data is to be read is selected by inputting a signal to the OE terminal of the RAM to be selected from a select gate comprised of AND gates 709 to 714 and OR gates 706 to 708 in response to the outputs from the decoder 715 and the exclusive OR gates 726, 727 which will be explained later.

The switches 723 and 724 are adapted to be operated in response to the pressing of the buttons 4 and 5 shown in FIG. 1. These switches, when turned on, enable a clock generating device 730 to deliver a clock signal to UP and DOWN counters of an address difference counter 720 so that the counter 720 conducts up-counting and down-counting, respectively. The value counted by the address difference counter is used as the amount of scroll, i.e., the value of offset of the juncture between the image on the n-th frame and the image on the (n+1)th frame. A direction detecting device 728 detects the direction of the scroll so as to determine whether the image of the n-th frame is to be displayed on the right side or the left side of the display area of the display device 410.

A comparator 719 compares the content of the imaging horizontal address counter 718 and the content of the address difference counter 720. The results of the comparison are delivered to exclusive OR circuits 726 and 727, respectively. The value counted by the address difference counter 720 is thus compared with the content of the imaging horizontal address counter 718. When the output from the direction detecting device 728 indicates that rightward scrolling is being conducted, the exclusive OR gate 726 provides an output "H" while the exclusive OR circuit 727 provides an output of "L" level, as long as the content of the imaging horizontal address counter 718 is greater than the value counted by the address difference counter 720. If the content of the film counter 412 is (n+1) in this state, the AND gate 712 is selected in accordance with the output from the decoder 715, so that the image data on the n-TH frame is read from the RAM 704 and is delivered to the display device 410 through the D/A converter 409. The display device 410 performs the displaying operation in accordance with the addresses designated by the display horizontal address counter 721 and the display vertical address counter 722. The display horizontal address counter 721 is reset at the moment of the coincidence signal (=) is from the comparator 719.

Thereafter, the content of the imaging horizontal address counter 718 becomes greater than the count value of the address difference counter 720 and the image data in the RAM 704 corresponding to the addresses in the imaging horizontal address counter in this state, i.e., the right portion of the image on the n-TH frame, is displayed on the left portion of the display area on the display device 410. Thereafter, the imaging horizontal address counter 718 is reset to the initial state by the horizontal blanking signal HD and the content of the imaging horizontal address counter 718 becomes smaller than the value counted by the address difference counter 720. As a result, the exclusive OR gates 726 and 727 output "L" and "H" signal, respectively, in accordance with the output of the comparator 719, so that the AND gate 713 is selected and the image data on the present frame, i.e., on the (n+1)TH frame is read from the RAM 705 and input to the display device 410 through the D/A converter 409.

In consequence, the display device 410 displays images in such a manner that the image data corresponding to the first address in the imaging horizontal address counter 718 is displayed at the position which corresponds to the address designated by the display horizontal address counter 721 at this moment. In consequence, a left end portion of the image on the (n+1)TH frame is displayed on the right side of the n-TH frame in contact with the latter as shown in FIG. 6(b).

In case of a leftward scroll, the output of the direction detecting means 728 is inverted so that the condition of switching of the outputs from the exclusive OR gates 726 and 727 is reversed from that in the rightward scroll. In consequence, a right end portion of the image on the (n+1)TH frame is displayed on the left portion of the display area of the display device 410, while the left end portion of the image on the n-TH frame is displayed on the right side of the display area on the display device 410.

The imaging address generating device 404 used in the circuit shown in FIG. 2 can be obtained by combining the imaging vertical address counter 717 and the imaging horizontal address counter 718 of this embodiment. At the same time, the phase control device 405 of the circuit shown in FIG. 2 may comprise the address difference counter 720 with fixed up-count and down-count values, direction detecting device 728, comparator 719 and the exclusive OR gates 726 and 727, all of which are used in this embodiment. In addition, the RAM select device 411 used in the circuit of FIG. 2 may comprise the combination of OR gates 706 to 708, AND gates 709 to 714 and the decoder 715. Finally, the address generating device 406 of the circuit shown in FIG. 2 may comprise a combination of the display horizontal address counter 721 and the display vertical address counter 722 of this embodiment.

FIGS. 8(a) and 8(b) illustrate a fourth example of the display, in which a border line is drawn between both images so as to facilitate the discrimination between two images. The border line enables the photographer to easily find the position of the juncture between two images even when these two images are substantially continuous as shown in FIG. 8(b).

A method for obtaining this type of display will be explained with reference to FIG. 9. The coincidence signal (=) from the comparator 719 is inverted by an inverter 1201 and the inverted signal is input to one of the inputs of an AND gate 1202, while the other input receives the data from the RAM 403. The output from the AND gate 1202 is delivered to the D/A converter 409. In consequence, when the coincidence signal is output from the comparator 719, the AND gate 1202 inhibits the delivery of the data of the RAM 403 to the D/A converter 409 and the inhibited portion of the data is displayed as the border line shown in FIG. 8.

FIG. 11 illustrates an improvement in the scroll function explained in connection with FIG. 7. In this case, the address difference counter 720, which is the same as that shown in FIG. 7, is controlled by a decoder 1203 such that it counts down or up frame numbers when the scroll has proceeded beyond the preceding frame or the subsequent frame and delivers the counted value to the decoder 715 thus enabling scrolling of the film over a multiplicity of frames. Namely, with reference to FIG. 10, after conducting panorama photographing on the (n-2)TH frame, (n-1)TH frame and the n-TH frame, the display region A is shifted to the left and right in response to the manipulation of the scroll buttons, thereby displaying the desired image on the viewfinder. This arrangement enables the photographer to confirm the state of the panorama photograph in the electronic viewfinder after a series of shots.

FIGS. 12(a) and 12(b) illustrate a sixth example of the display in which a portion of the image in the preceding frame, i.e., n-TH frame, is left on the display and the image in the next frame, i.e., the (n+1)TH frame is superposed on the left image of the preceding frame. More specifically, FIG. 12(a) shows the state in which the duplicate portions do not correctly overlap each other, while FIG. 12(b) shows the state in which the duplicate portions precisely overlap each other so that the image of the preceding frame has become invisible. It may seem that this measure is not preferred because the prints of the photographed image contain overlapping portions. This problem, however, can be overcome by designing the imaging device such that it can form an image portion out of the area to be printed. It will be understood that this example enables the photographer to check at a glance whether the successive images are continuous or not, thus facilitating the connection of images on successive frames.

FIG. 13 shows a circuit which is capable of forming the display images explained in connection with FIGS. 12(a) and 12(b).

The address data in a display address counter 1111 is delivered to a RAM 1102 which picks up the present image, i.e., the image on the (n+1)TH frame, and also to the display device 410, so that the data from a RAM 1102 is displayed on the display device 410 at the same address as that in the RAM 1102. A RAM 1101 is adapted for picking up the data of an image on the preceding frame, i.e., the n-TH frame. The address offset value is set in a panorama address generating device 1104 by a pre-set device 1103 and the RAM 1101 reads the data in accordance with this offset value. The data from the RAM 1102 and the data from the RAM 1101 are input to the exclusive OR gate 1107 and, when coincidence between these data is obtained, the exclusive OR gate delivers an output of "L" level. Thus, the exclusive OR gate 1107 outputs the overlapping portion between the image data from the RAMs 1101 and 1102. On the other hand, the comparator 1105 compares the value counted by the panorama address generating device 1104 with the content of the display address counter 1111. The comparator 1105 delivers an output of "H" level when the image data from the RAM 1101 has been scrolled to the right end of the display area, i.e., to the address FF.sub.H. Before such a condition is obtained, the AND gate 1109 receives a signal of "H" level through the inverter 1106 so that the output of the exclusive OR gate 1107 is delivered to the A/D converter 409 through the AND gate 1109 and the OR gate 1110, so that a display as shown in FIG. 12(a) is formed on the left portion of the display area of the display means 410. When the image data from the RAM 1101 has been moved to the right end, i.e., to the address FF.sub.H as described above, the output from the comparator 1105 is inverted so that the OR gate 1110 receives through the AND gate 1108 only the output of the RAM 1102, whereby a display as shown in FIG. 12(b) is formed on the right portion of the display area in the display means 410.

FIG. 14 illustrates a manner in which the panorama picture is scrolled or developed in vertical directions. This can be realized by applying the control of the horizontal address counter in the described embodiment to the vertical address counter.

FIG. 15 shows the manner of scrolling shown in FIG. 10 developed in the vertical direction. This also can be realized by applying the control of the horizontal address counter in the circuits of FIGS. 7 and 11 to the vertical address counter.

FIG. 16 illustrates a manner in which the images are scrolled both up and down and to the left and right. It will be clear to those skilled in the art that such a four-way scroll can be easily attained by suitably combining the arrangements described hereinbefore. This arrangement enables an object to be photographed in perspective view as shown in FIG. 16.

FIG. 17 illustrates a modification of the example of FIG. 16 designed for reading characters or letters. The number of letters which can be displayed on and recognized through a single picture frame is limited by the number of pixels in the imaging device 401 or the display device 410 of FIG. 7. For storing voluminous textual information in a written document, therefore, it is necessary to divide the written document into a plurality of sections and to record them in frames which are successive both vertically and horizontally. The panorama photographing device of the invention makes it possible to easily recognize the juncture between the images on the adjacent frames. By storing these image data in a memory and suitably controlling the memory by, for example, a microcomputer, the sections of the object which is in this case a written document are automatically and visually connected to enable the user to read through the content of the document.

FIG. 18 shows a different embodiment which incorporates a microcomputer. The microcomputer 1701 fetches information concerning the direction of panorama photographing from a direction detecting device 728 and stores the information in a direction RAM 1702. In reproducing the panorama image, the microcomputer delivers address data to the RAM 403 in accordance with the data from the direction RAM 1702 in accordance with the scrolling operation.

The specific structural details of the devices represented by blocks in the schematic diagrams of FIGS. 2, 7, 9, 11, 13 and 18 are per se well known or could be readily constructed by the person of ordinary skill in this field without undue experimentation. Therefore, the exact structure of the blocks in the schematics is not described in further detail in order to more clearly describe the present invention, and since such details are not critical to the best mode of carrying out the present invention.

While the present invention has been described with respect to what is presently considered to be the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.