Control and Monitoring Device for a Power Switch

The present invention relates to the control and monitoring of power switches. It more particularly relates to the control of power switches, one terminal of which is at a floating reference voltage, and level translating circuits designed to transmit, from a control circuit at a fixed reference voltage, orders to a power switch control circuit, or conversely, to receive monitoring information.

FIG. 1 very schematically shows the control of a power switch 1 arranged in series with another power switch 2 connected to the ground, these two switches being part, for example, of a bridge circuit. The junction of these two switches is at a floating voltage V.sub.F liable, on the one hand, to reach high voltages and, on the other hand, to be submitted to very abrupt voltage variations, for example several tens of thousands volts per microsecond. The control unit comprises, on the one hand, a control circuit 10 receiving external orders on a terminal 11 and connected to the ground and, on the other hand, a gate control circuit corresponding to each switch, and especially a gate control circuit 20 for switch 1. Between circuits 10 and 20 is inserted a level translating circuit 30 connected to the ground, as well as to a floating voltage V'.sub.F varying with the floating voltage V.sub.F.

The gate control circuit 20 is necessarily connected to the floating voltage V.sub.F. Therefore, problems are encountered as regards the level translation between the control and monitoring circuits and there generally are two drawbacks, on the one hand, energy consumption when switch 1 is conductive, due to current then flowing in translator 30 submitted to voltage V'.sub.F and, on the other hand, sensitivity to parasitic pulses resulting from fluctuations of the floating voltage V.sub.F and therefore of V'.sub.F.

In order to solve consumption problems, pulse control circuits, such as the one illustrated in FIG. 2, have been provided. In this circuit, the portion of the gate control 20 comprises a RS flip-flop 21, the output of which is applied through an amplifier 22 to the gate of the power transistor 1. Each input R and S of the flip-flop receives one of the outputs of the level translating circuit, 31 and 32, respectively. The whole set of circuits 21, 22, 31 and 32 is connected to the floating voltage V'.sub.F. The level translating circuits 31 and 32 receive control pulses from the control circuit 10 through circuit 33 and 34.

The advantage of this type of circuit is to avoid a significant dissipation of energy in the translating circuit 30 but the circuit is sensitive to parasitic pulses on source V.sub.L or to abrupt variations in voltage V.sub.F. In fact, there unavoidably are stray capacitances, for example MOS transistors capacitances 35 and 36, liable to get charged due to abrupt voltage variations and, on account of abrupt variations in the floating voltage value, to let appear parasitic pulses across the terminals or inside circuits 31 and 32, which may cause spurious triggering of the RS flip-flop 21.

An object of the invention is to provide a circuit which permits avoiding the effect of these stray capacitances.

While the usual approach for achieving this result consists in minimizing values of the stray capacitances, the applicant has established that efforts in this way are unavoidably limited; so, the invention provides to transmit orders, between the control circuit connected to the ground and the gate control circuit connected to the floating voltage, through a coding/translating/decoding unit designed to supply operation signals to either input of the RS flip-flop only when one of the inputs receives a predetermined coded signal.

More particularly, the invention relates to a control and monitoring circuit for a power switch comprising a first portion coupled to this switch and fed with reference to the floating voltage of an electrode of this switch, a second portion coupled to circuits external to the switch and fed with reference to a fixed voltage, a coder arranged near the second portion and a suitable decoder arranged near the first portion. The connection between the two portions is made by two paths respectively connected to the inputs R and S of a flip-flop, and the coder comprises means for simultaneously sending at least one pulse on each path, then at least one pulse on a selected path, the decoder comprising suitable decoding means.

According to an embodiment of the invention, the first and second portions each comprises a coder/decoder.

The foregoing and other objects, features and advantages of the invention will be apparent from the following detailed description of preferred embodiments as illustrated in the accompanying drawings wherein:

FIGS. 1 and 2, already described, are designed to illustrate the state of the art and the problem the invention aims to solve;

FIG. 3 is a block diagram showing the overall arrangement of a circuit according to the invention;

FIG. 4 shows an embodiment of the coding circuit according to the invention;

FIG. 5 shows an embodiment of the decoding circuit according to the invention;

FIG. 6 shows signals at various positions of the coding circuit during a switching on order; and

FIG. 7 shows signals at various positions of the coding circuit during a switching off order.

In these various figures, same reference numerals designate identical or analogous components.

FIG. 3 globally illustrates in the form of diagrams a circuit according to the invention. This circuit comprises, on the side of the control circuit 10 connected to the ground, a pulse coder 40 and, on the side of the gate control circuit 20 connected to the floating voltage V.sub.F, a decoder 50, separated by a level translating circuit 30. The decoder is illustrated at the input of circuit 20. In fact, it will be embedded in this circuit in order to be arranged behind the places where parasitic pulses are liable to appear, to make it possible to differentiate coded pulses from coder 40 from parasitic pulses, as will clearly appear in the following description.

An exemplary coding circuit 40 as part of control circuit 10 is illustrated in FIG. 4. This circuit 40 comprises a pulse generating oscillator 41, the output of which is applied to the input C of a counter 42. The control signal determining the circuit output appears on its input IN and is set from a low level to a high level when it is desired to determine switching on of the power switch 1. The outputs OUTA and OUTB of this circuit appear at the output of OR gates O1 and O2. Signal IN is applied to the input of an AND gate A1 and, through an inverter I1, to the input of an AND gate A2. The output of gate A1 is sent to a first input of an OR gate O3, and AND gate A3, an AND gate A4 and an AND gate A5. The output of AND gate A2 is sent to the second input of OR gate O3, and to the first inputs of the AND gates A6, A7 and A8.

The output of AND gate A5 is sent to the input R of a D-type flip-flop 43 and to the input C of a D-type flip-flop 44. The output of AND gate A8 is sent to the input C of flip-flop 43 and to the input R of flip-flop 44. Inputs D of flip-flops 43 and 44 are set to a positive voltage and the reverse outputs Q of these flip-flops are respectively sent to each of the second inputs of AND gates A1 and A2. The output of the OR gate O3 is sent to the input R of counter 42. The output of rank 0 of this counter 42 is sent to a first input of a 3-inputs AND gate A9, the second and third inputs of which receive the outputs of rank 1 and 2 of counter 42 through inverters I2 and I3. The fourth output of counter 42 is sent to the second inputs of gates A5 and A8. The output of rank 0 of counter 42 is also sent to the second inputs of gates A3 and A6. The output of gate A9 is sent to the second inputs of gates A4 and A7. Gate O1 receives the outputs of gates A3 and A7 and gate O2 receives the output of gates A4 and A6.

The operation of this circuit will be explained in case of a switching on order of the power switch 1. For this purpose, one has indicated in FIG. 6 signal IN, which passes from a low level to a high level during the reception of a switching on order and the resulting coded output signals OUTA and OUTB, and by numbers, labelled in the same way, the signals appearing at various positions of the circuit.

It is assumed that initially output Q of flip-flop 44 (1') is at a high level and that output Q of flip-flop 43 (2') is at a low level. The switching of input IN causes the output (3') of AND gate A1 to be set to high level and the output (4') of AND gate A2 remains set to low level. The output (5') of gate O3 is also set to high level, simultaneously with the output (3') of AND gate A1. The output (6') of oscillator 41 continuously supplies square pulses. The signal (7') on the counting output 0 of counter 42 supplies square pulses at a frequency half of that of the oscillator 41. The output (8') of AND gate A9 only supplies the first square wave and the output signal (9') of the counting output 4 of counter 42 supplies a pulse when four square waves are obtained at the counting output 0 (7'). This signal (9') applied to gates A5 and A8 causes signals (1') and (2') to change their state (at outputs Q of the D-type flip-flops 44 and 43). This results in the switching of the output state (3') of AND gate A1, and therefore of the output (5') of the OR gate O3, and inhibition of counter 42. It can be seen that the output OUTA of gate O1 corresponds to signal (7') and that the output OUTB of gate O2 corresponds to signal (8'). Therefore, one finally obtains at the circuit output a signal OUTA constituted by four successive pulses and a signal OUTB constituted by one pulse coinciding with the first pulse on output OUTA.

FIG. 7 similarly shows signals appearing at input IN, at positions (1') to (9') and on outputs OUTA and OUTB when signal IN passes from high level to low level for determining the switching off of the power switch 1. This figure can easily be understood by referring to the detailed description of FIG. 6. FIG. 7 shows that a switching off order will correspond to the emission on output OUTA of one pulse, and on output OUTB to emission of four successive pulses, the first of which coincides with the pulse on output OUTA.

Those skilled in the art will note that there are very numerous methods for realizing logic circuits supplying output signals such as those labelled OUTA and OUTB.

However, the choice of the type of control signals supplied at the output of the coding circuit 40 constitutes one of the aspects of the invention. Indeed, according to the invention, and as will be seen later on, it has been noted that it was particularly advantageous to emit as coded signals, first, at least one simultaneous pulse onto the two output paths and, then, a succession of coded pulses on the only path that has to be specifically controlled.

FIG. 5 shows a general diagram of the circuit according to the invention, wherein the decoding part is illustrated in greater detail. Control circuit 10 supplying an input signal IN to a coder 40 provided with outputs OUTA and OUTB. These outputs are sent to level translators corresponding to components 31-34 of FIG. 3. These level translators send signals to inputs S and R of a flip-flop 21 through a decoding circuit 50.

Level translators 31, 33 and 32, 34 are conventional circuits, similar to those that would be used in case of FIG. 2. Therefore, they will be not be described in detail. Their outputs are labelled OUT31 and OUT32. In the absence of parasitic pulses, signals on outputs OUT32 and OUT31 respectively correspond to output signals OUTA and OUTB of coder 40.

In the figure, black triangles with their tip oriented downwardly represent the points connected to the floating reference V.sub.F.

Decoder 50 receives on its two inputs signals OUT32 and OUT31. Signal OUT32 is sent through two successive inverters I11 and I12 to the input C of a counter 51 and signals OUT31 is sent through two successive inverters I13 and I14 to the input C of a D-type flip-flop 52. The junction of inverters I11 and I12 is connected to the first input of an AND gate A11, the second input of which is connected to the junction of inverters I13 and I14 and the output is connected to the reset terminals R of counter 51 and flip-flop 52. The two outputs 0 and 1 of counter 51 are sent to two inputs of an AND gate A12, the output of which is connected to the input S of flip-flop 21. The Q output of flip-flop 52 is sent to the R input of the RS flip-flop 21. The Q output of flip-flop 52 is sent to its input D.

This circuit operates as follows. Signals OUTA and OUTB respectively appear at the output of inverters I12 and I14. AND gate A11 transmits the first pulse which is identical in OUTA and OUTB and resets counter 51 and flip-flop 52. Then:

in case of a switching on order, the signal at the output of inverter I12 exhibits a succession of zero crossing (pulses) while the signal at the output of inverter I14 remains set to high level. As a result, counter 51 supplies simultaneous high outputs after counting a predetermined number of pulses (here 3) and then AND gate A12 controls the S input of flip-flop 21, the Q output of which then passes to high level.

in case of a switching off order, inverter I14 supplies a succession of pulses at the clock input C of flip-flop 52 and, as soon as there is a first non-simultaneous pulse on the other path, the output Q of this flip-flop is set to high level and resets flip-flop 21.

It will be noted that parasitic pulses on the floating reference V.sub.F, resulting for example from very high voltage gradients, cause simultaneous pulses to occur at outputs OUT32 and OUT31 of the level translators. With the coding system according to the invention, providing simultaneous resetting pulses of the decoder before any information signal is sent, such parasitic pulses will have no effect on the circuit operation.

According to another advantage of the invention, the switching on signal resulting from the output of counter 51 sent to input S of flip-flop 21 is delayed while the switching off signal resulting from the output Q of flip-flop 52 is sent to the input R of flip-flop 21 and is immediately transmitted. Then, a slight delay inherently occurs between a switching on and a switching off order, this delay being adjustable with the oscillation frequency of coder 40. Since, as explained above, a circuit according to the invention is designed to be inserted in a bridge-connected control circuit, this prevents two bridge power switches from being simultaneously switched on, which might cause shorting of a bridge leg.

Whereas a coder arranged on the side of circuits connected to the ground and a decoder arranged on the side of circuits connected to the floating voltage have been described, each of these components can be replaced by a coder/decoder for sending back monitoring information about the operating state of a floating power switch.