Adjustable Analog Filter Circuit With Temperature Compensation

1. Field of the Invention

The present invention relates to an analog filter circuit incorporated in a semiconductor integrated circuit and, more particularly, to an improvement of a filter adjusting circuit.

2. Description of the Related Art

FIG. 1 shows a conventional analog filter circuit. In FIG. 1, reference numeral 20 denotes a filter adjusting circuit; and 21, a filter circuit.

The filter circuit 21 is constituted by amplifying npn transistors Q15 and Q22, the collectors of which are connected to a VCC potential, npn transistors Q16 and Q23, the emitters of which are commonly connected and collectors and bases are connected to each other, a resistor R8 connected between the emitter of the transistor Q15 and the collector of the transistor Q16, a resistor R12 connected between the emitter of the transistor Q22 and the collector of the transistor Q23, an npn transistor Q18 for current source and a resistor R9 connected in series between a common emitter connecting point of the transistors Q16 and Q23 and a ground potential GND, an npn transistor Q17, the base of which is connected to the base of the transistor Q16, and the collector of which is connected to the VCC potential, an npn transistor Q20, the emitter of which is connected to the emitter of the transistor Q17 and the base of which is connected to the base of the transistor Q23, a resistor R10 and a pnp transistor Q19 connected in series between the VCC potential and the collector of the transistor Q20, a capacitor C connected between the collector of the transistor Q19 (a signal output node 22) and the VCC potential, and an npn transistor Q21 for current source and a resistor R11 connected in series between a common emitter connecting point of the transistors Q17 and Q20 and the ground potential GND.

An analog input voltage VIN is applied to the base of the amplifying transistor Q15. The base of the transistor Q22 is connected to the collector of the transistor Q19. An output voltage VOUT is output from the output node 22 to which the collector of the transistor Q19 is connected.

On the other hand, the filter adjusting circuit 20 is constituted by a constant current source I0 connected in series between the VCC potential and the ground potential GND, an npn transistor Q0, the collector and base of which are connected to each other, and a resistor R0, an npn transistor Q1, the base of which is connected to the base of the transistor Q0, a resistor R1 connected between the emitter of the transistor Q1 and the ground potential GND, a pnp transistor Q2 which is connected between the VCC potential and the collector of the transistor Q1, and the base and emitter of which are connected to each other, a pnp transistor Q3, the base of which is connected to the base of the transistor Q2, and the emitter of which is connected to the VCC potential, a resistor R2 connected between the collector of the transistor Q3 and the ground potential GND, an npn transistor Q8, the base of which is connected to the collector of the transistor Q3, an npn transistor Q10, the emitter of which is connected to the emitter of the transistor Q8, a resistor R4 connected between a common emitter connecting point of the transistors Q8 and Q10 and the ground potential GND, a pnp transistor Q7 which is connected between the VCC potential and the collector of the transistor Q8, and the base and emitter of which are connected to each other, a pnp transistor Q9, the base of which is connected to the base of the transistor Q7, the emitter of which is connected to the VCC potential, and the collector of which is connected to the collector of the transistor Q10, an npn transistor Q12, the base of which is connected to the collector of the transistor Q9, and the emitter of which is connected to the base of the transistor Q10, a resistor R5 and a pnp transistor Q11 connected in series between the VCC potential and the collector of the transistor Q12, a pnp transistor Q13, the base of which is connected to the transistor Q11, a resistor R6 connected between the VCC potential and the emitter of the transistor Q13, an npn transistor Q14, the collector and base of which are connected to each other and a resistor R7, the npn transistor Q14 and the resistor R7 being connected in series between the collector of the transistor Q13 and the ground potential GND, and a variable resistor VR which is connected outside the integrated circuit between the base of the transistor Q10 and the external ground potential for the integrated circuit, and which has an extremely low temperature coefficient.

The transistors Q8 and Q10 constituting a differential pair form a buffer amplifier circuit. The transistors Q0 and Q1 form a current mirror circuit CM1. The transistors Q2 and Q3 form a current mirror circuit CM2. The transistors Q7 and Q9 form a current mirror circuit CM3 to be a load of the buffer amplifier circuit. The transistors Q11 and Q13 form a current mirror circuit CM4. The transistors Q11 and Q13 forming the current mirror circuit CM4 have emitter areas twice those of other transistors, respectively.

The bases of the transistors Q0 and Q14 in the filter adjusting circuit 20 are respectively connected to the bases of the transistors Q18 and Q21 in the filter circuit 21. Resistances of the resistors R2, R8 and R12 are set so as to satisfy relation R2=R8=R12. The base of the transistor Q11 in the filter adjusting circuit 20 is connected to the base of the transistor Q19 in the filter circuit 21. Resistances of the resistors R5, R6, and R10 are set so as to satisfy relation R5=R6=R10/2.

Note that, temperature coefficients of the resistors R0 to R2 and R4 to R12 in the integrated circuit are equal to each other.

In the filter adjusting circuit 20, the base potential of the transistor Q0 of the current mirror circuit CM1 receiving a current from the constant current source I0 is supplied to the base of the transistor Q18 in the filter circuit 21. A current from the constant current source I0 is supplied to the resistor R2 through the current mirror circuits CM1 and CM2, so that a potential difference appears across both terminals of the resistor R2. The voltage across the resistor R2 is supplied to both terminals of the variable resistor VR outside the integrated circuit by the buffer amplifier circuit. A current proportional to a current supplied to the variable resistor VR is supplied to the transistor Q14 and the resistor R7 through the current mirror circuit CM4. The base potential of the transistor Q14 is supplied to the base of the transistor Q21 in the filter circuit 21.

In the filter circuit 21, a potential difference proportional to the first potential difference generated across the resistor R2 in the filter adjusting circuit 20 appears across each of the resistors R8 and R12. Characteristics of the filter circuit 21 are controlled by a current supplied to the transistor Q21 receiving a base current from the filter adjusting circuit 20. A transfer function of the filter circuit 21 can be obtained by the following equation. ##EQU1## where, ##EQU2##

re0 is the A.C. emitter equivalent resistance of Q18,

IC18 is a collector current of the transistor Q18, ##EQU3##

re1 is the A.C. emitter equivalent resistance of Q21,

IC21 is a collector current of the transistor Q21, ##EQU4##

k is a Boltzmann's constant,

q is an electric charge of an electron, and

T is an absolute temperature.

In addition, a time constant T0 of the filter circuit 21 is given by: ##EQU5## In addition, since equation (6) can be established, equation (7) can be obtained. ##EQU6## Since equation (7) includes a term V.sub.T, T0 changes with a change in temperature.

That is, the filter circuit 21 constitutes a low-pass filter, so that a ratio between the currents IC18 and IC21 of the filter circuit 21 is adjusted by the adjustment of the variable resistor VR connected outside the integrated circuit through the filter adjusting circuit 20, so that the current IC18 is kept constant. Therefore, by adjusting a magnitude of the current IC21, an error of the time constant T0 caused by the fluctuation of the capacitor C of the filter circuit 21 can be adjusted so that the time constant T0 can be kept to be a predetermined value at a predetermined temperature.

In the conventional filter circuit, however, the characteristics of the transistors of the filter circuit 21 are changed by the change in temperature, so that the time constant is changed.

As described above, the conventional analog filter circuit has a problem that characteristics of transistors of a filter circuit are changed by a change in temperature, so that a time constant is changed.

It is, therefore, an object of the present invention to provide an analog filter circuit capable of compensating for a time constant error caused by a fluctuation of a capacitance of the filter circuit to keep the time constant at a predetermined value at a predetermined temperature, and stabilizing the time constant of the filter circuit against a change in temperature, by adjusting a current of the filter circuit through a filter adjusting circuit by adjustment of a variable resistor.

According to the present invention, there is provided an analog filter circuit comprising a filter circuit for receiving an analog voltage, a filter adjusting circuit for adjusting a time constant in the filter circuit, and a filter compensation circuit for compensating for a time constant error in the filter circuit on the basis of a change in temperature.

In addition, according to the present invention, there is provided an analog filter circuit comprising a filter adjusting circuit having first circuit means for generating a first current, second circuit means for generating a first potential difference proportional to the first current, voltage buffer means for receiving the first potential difference, a variable resistor, both sides of which receive an output from the voltage buffer means, and third circuit means for generating a second current proportional to a current supplied to the variable resistor, a filter compensation circuit having forth circuit means for generating a second potential difference proportional to an absolute temperature and adding the second potential difference to an input of the voltage buffer means, and a filter circuit which has a capacitor and a time constant of which is adjusted in accordance with the second current.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

FIG. 1 is a circuit diagram showing a conventional analog filter circuit;

FIG. 2 is a circuit diagram showing an arrangement according to an embodiment of the present invention;

FIG. 3 is a block diagram showing a part of the circuit of the embodiment;

FIG. 4 is a circuit diagram showing an arrangement according to another embodiment of the present invention; and

FIG. 5 is a circuit diagram showing an arrangement according to still another embodiment of the present invention.

The present invention will be described in detail with reference to embodiments in conjunction with the accompanying drawings hereinafter.

An analog filter circuit according to the present invention shown in FIG. 2 is different from the conventional circuit shown in FIG. 1 in comprising a filter compensation circuit 23 for generating a potential difference having temperature characteristics which cancel changes in characteristics of transistors in a filter circuit 21 caused by a change in temperature. The same reference numerals as in FIG. 1 denote the same parts in FIG. 2, and a detailed description thereof will be omitted.

More specifically, in the filter compensation circuit 23 added to the filter circuit in FIG. 2, an npn transistor Q4, the collector and base of which are connected to each other, is connected between the collector of a transistor Q3 and a resistor R2. The base of an npn transistor Q5 is connected to the base of the transistor Q4. The collector of the transistor Q5 is connected to a VCC potential. The transistors Q4 and Q5 form a current mirror circuit CM5. In this case, an emitter area of the transistor Q4 is equal to that of a transistor Q0 or the like. An emitter area of the transistor Q5 is, however, set to be e.sup.4 (e: the base of a natural logarithm) times that of the transistor Q4. That is, emitter current densities of the transistors Q4 and Q5 in the current mirror circuit CM5 are set to be e.sup.4 :1.

A collector-emitter path of an npn transistor Q6 and a resistor R3 are connected in series between the emitter of the transistor Q5 and a ground potential GND. A base potential of the transistor Q0 is supplied to the base of the transistor Q6. The emitter of the transistor Q5 is connected to the base of a transistor Q8.

An operation of the filter circuit is essentially the same as the operation of the conventional filter circuit described with reference to FIG. 1. However, a second potential difference proportional to an absolute temperature appears between the emitters of the transistors Q5 and Q4 on the basis of a voltage difference between the base-emitter paths of the transistors Q5 and Q4 having different current densities. Assume the current flowing through resistor R2 is I0. In this case, the first potential difference generated across the resistor is R2*I0. The second potential difference generated between the emitters of transistors Q4 and Q5 is given by the difference between the base-emitter voltages V.sub.BE thereof. Here the base-emitter voltages V.sub.BE4 and V.sub.BE5, of transistors Q4 and Q5, can be expressed as:

where I.sub.E is an emitter current and I.sub.S is a saturated current which is proportional to the emitter area. Since the second potential difference is defined as V.sub.BE5 -V.sub.BE4, V.sub.BE5 -V.sub.BE4 =V.sub.T ln(e.sup.4 /1). The sum of a first potential difference generated across both the terminals of the resistor R2 and the second potential difference generated between the emitters of the transistors Q5 and Q4 are supplied to a variable resistor VR through a buffer amplifier circuit. A current proportional to the current supplied to the variable resistor VR is supplied to a transistor Q14 and a resistor R7 through a current mirror circuit CM4. A base potential of the transistor Q14 is supplied to the base of a transistor Q21 in the filter circuit 21.

As a result, even if a time constant T0 of the filter circuit 21 is changed by a change in characteristics of the transistors in the filter circuit 21 caused by a change in temperature, a potential difference having temperature characteristics for canceling the change in characteristics of the transistors in the filter circuit 21 caused by the change in temperature is generated in a filter adjusting circuit 20. The potential difference is supplied to the filter circuit 21. Therefore, the time constant T0 is kept at a predetermined value against the change in temperature.

More specifically, in the filter circuit of the above embodiment, a current IC21 of the transistor Q21 in the filter circuit 21 is given by: ##EQU7## Therefore, the time constant T0 of the filter circuit can be obtained by the following equation. ##EQU8## As described above, the time constant T0 of the filter circuit 21 is determined by only a capacitor C of the filter circuit 21 and a resistance of the variable resistor VR outside the integrated circuit. Therefore, the time constant T0 is kept at a predetermined value against the change in temperature.

As described above, according to the analog filter circuit of the present invention, a time constant error caused by a fluctuation of a capacitance of the filter circuit can be compensated, the time constant is kept at a predetermined value at a predetermined temperature, and the time constant of the filter circuit is kept at a predetermined value against a change in temperature by adjusting a ratio of currents in the filter circuit through a filter adjusting circuit by adjustment of the variable resistor.

As shown in FIG. 3, the filter circuit 21 in the circuit of the embodiment described above is arranged using a so-called gm amplifier 24 wherein the base of the transistor Q15, the base of the transistor Q22, and the collector of the transistor Q19 respectively serve as a non-inverting input terminal, an inverting input terminal, and an output terminal. The inverting input terminal and the output terminal of the gm amplifier 24 are short-circuited, and the output terminal is virtually grounded by a capacitor C.

In the present invention, as a filter circuit 21, various circuits having various arrangements can be used, and the filter circuit 21 is not limited to the arrangement shown in FIG. 2.

FIG. 4 shows another embodiment of a filter circuit 21. In this case, two voltage buffer circuits 25 and 26 are arranged instead of the transistors Q15 and Q22. An analog input voltage VIN is supplied to one voltage buffer circuit 25, and an output from the voltage buffer circuit 25 is supplied to one terminal of a resistor R8. A voltage VOUT at an output node 22 is supplied to the voltage buffer circuit 26, and an output from the voltage buffer circuit 26 is supplied to one terminal of a resistor R12.

When a filter circuit having such an arrangement is used, in equation (7) about a time constant T0, 4.sub.VT is replaced with 2V.sub.T. As a result, in this embodiment, an emitter area of a transistor Q5 in a filter compensation circuit 23 is set to be e.sup.2 times that of a transistor Q4 to compensate for an effect of a temperature voltage V.sub.T. That is, emitter current densities of the transistors Q4 and Q5 in a current mirror circuit CM5 are set to be e.sup.2 :1.

FIG. 5 shows still another embodiment of the filter circuit 21. In this case, an npn transistor Q24, the base and collector of which are connected to each other, is connected between a transistor Q16 and a resistor R8. An npn transistor Q25, the base and collector of which are connected to each other, is further connected between a transistor Q23 and a resistor R12.

When the filter circuit having such an arrangement is used, in equation (7) about a time constant T0, 4V.sub.T is replaced with 6V.sub.T. As a result, in this embodiment, an emitter area of a transistor Q5 in a filter compensation circuit 23 is set to be e.sup.6 times that of a transistor Q4 to compensate for an effect of a temperature voltage V.sub.T. That is, emitter current densities of the transistors Q4 and Q5 in a current mirror circuit CM5 are set to be e.sup.6 :1.