Modulated Range Tone System

FIG. 1 illustrates a range tone system including a ground station and a spacecraft;

FIG. 2 illustrates a prior art range tone generator which may be used in the system of FIG. 1;

FIG. 3 illustrates a prior art range tone signal processor for processing return signals in the arrangement of FIG. 1;

FIG. 4 illustrates a range tone generator in accordance with the invention which may be used in the arrangement of FIG. 1;

FIG. 5 illustrates a range tone processor in accordance with the invention which may be used in the arrangement of FIG. 1;

FIG. 6 is a simplified block diagram of a high-resolution ON-OFF counter useful with the arrangement of FIG. 5; and

FIG. 7a illustrates an amplitude-time plot of a 3968 Hz sinusoid, and FIG. 7b is a corresponding plot of a 27 KHz sinusoid frequency-modulated by the 3968 Hz signal of FIG. 7a.

FIG. 4 is a simplified block diagram of a range tone generator in accordance with an aspect of the invention, which may be used in place of range tone generator 40 of FIG. 1. In FIG. 4, an 8 MHz clock signal is applied over a conductor 400 to a divide-by-nine counter 462. Counter 462 produces an 888.888 KHz signal on a conductor 410 for application to an address generating counter 414 and a further divide-by-seven counter 412. Address generating counter 414 recurrently counts and produces a recurrent stream of sequential five-bit addresses which are applied over a data path 416 to a programmable ROM (PROM) 418. Counter 414 also produces a 444.44 . . . KHz output which is coupled to a conductor 484 for use as a clock signal as described below. PROM 418 is preprogrammed at each addressable memory location with data representing the instantaneous amplitude of a 27.77 KHz (hereinafter "27 KHz") range tone. Samples are produced about 32 times per nominal cycle of the 27 KHz range tone. The amplitude-representative samples produced by PROM 418 in response to the 5-bit addresses are applied over a 10-bit data path 420 to an input of a multiplexer 422, and are also applied to a digital-to-analog converter (DAC) 424. DAC 424 converts the ten-bit amplitude-representative data generated by PROM 418 into a quantized analog signal. The quantized analog signal produced by DAC 424 is filtered by a 27 KHz bandpass filter 426 and is applied by way of a conductor 428 to start a counter associated with the range tone processor 500 of FIG. 5 for purposes described below.

The 888.888 . . . KHz signal produced by divider 462 of FIG. 4 is divided by seven in divider 412 to produce a 126.98 KHz clock signal on a conductor 430 for application to address generators 432, 434 and 436. The 444.444 . . . Khz clock signal on conductor 484 is applied to address generators 478, 480 and 482. Address generator 478 produces 7-bit addresses which are applied to the address inputs of a PROM 438. PROM 438 is preprogrammed at each addressable memory location with data representing the instantaneous amplitude of a 27 KHz range tone, frequency-modulated by a 3968 Hz range tone. In a particular embodiment of the invention, the deviation is .+-.1 KHz. FIG. 7a illustrates an amplitude versus time plot of a 3968 Hz sinusoid, and FIG. 7b illustrates a corresponding plot of a 27 KHz sinusoid FM-modulated by the 3968 Hz. An amplitude-representative sample is generated by PROM 418 about 32 times per nominal cycle of the 27 KHz range tone. The 10-bit data produced by PROM 438 is applied over a data path 440 to an input of multiplexer 422. PROM 440 receives addresses from address generator 432, and is preprogrammed with data representing the baseband 3968 Hz range tone (FIG. 7a). Ideally the 3968 Hz range tone represented by the data in PROM 440 is the same phase as the phase of the 3968 Hz modulating signal included in the data programmed into PROM 438. Since both PROM 438 and 440 are addressed by the same clock albeit at different frequencies, the 3968 Hz components which each produces will be phase coherent, but not necessarily in the same phase. The 3968 Hz data produced by PROM 440 is applied over a data path 456 to a multiplexer 466.

The 444.444 . . . KHz clock signal on conductor 484 is applied to an address generating counter 480 for generating 12-bit sequential addresses which are applied to a PROM 444. PROM 444 is preprogrammed with data representing the amplitude of a 27 KHz tone frequency-modulated with a 283-Hz tone. When addressed, PROM 444 produces 10-bit signals which are applied over a data path 448 to an input of multiplexer 422. The 126.98 KHz clock signal on conductor 430 is applied to an address generating counters 434 for generating 12-bit sequential addresses. The 12-bit address signals produced by address generating counter 434 are applied to PROM 446, which is preprogrammed with data representing the amplitude of the 283 Hz modulating signal. As in the case of PROMS 438 and 440, the 283 Hz components produced by PROMS 444 and 446 are phase coherent. The data produced by PROM 446 is applied over a data path 458 to an input of multiplexer 466. Similarly, the 444.444 . . . KHz clock signal produced by address counter 414 is applied over conductor 484 to an address generating counter 482, which produces 16-bit addresses for addressing PROM 450. PROM 450 is preprogrammed with data representing the amplitude of the 27 KHz tone frequency-modulated by the 35 Hz tone, and its data is applied to multiplexer 422 over a data path 454. The 126.98 KHz clock signal on conductor 430 is applied to an address generating counter 436, which generates 12-bit sequential addresses. The addresses from counter 436 are applied to a PROM 452. PROM 452 is preprogrammed with the 35 Hz modulating range tone, and its data is applied over data path 464 to multiplexer 466.

Counter 462 generates the same clock signals for generating all the FM-modulated range tones, so they all remain phase coherent. This allows the operation to be switched among the three FM-modulated carriers at will, without occasioning a phase jump or error at the time of the switch. This allows continuous 27 KHz range tone to be generated for high resolution range measurement, while at the same time switching among the 3968 Hz, 283 Hz, and 35 Hz ambiguity resolution range tones.

Multiplexers 422 and 466 of FIG. 4 are responsive to the range tone selection signals applied over data path 100 from a front panel or from the computer (FIG. 1), to couple to their outputs one of the signals applied to their inputs. Thus, multiplexer 422 may select one of four signals, namely the 27 KHz unmodulated pilot tone from PROM 418, the 27 KHz pilot tone modulated by 3968 Hz pilot tone produced by PROM 438, the 27 KHz pilot tone frequency modulated by the 283 Hz pilot tone produced by PROM 444, or the 27 KHz tone frequency modulated by the 35 Hz range tone produced by PROM 450. The tone selected by multiplexer 422 is applied to a DAC 474 for conversion into an analog signal. The resulting analog signal is filtered in a bandpass filter 476 having a bandwidth of about 8 KHz, centered on 27 KHz. The filtered signal is applied to conductor 42 for application to upconverter 26 of FIG. 1.

The 27 KHz reference signal is generated continuously by DAC 424 of FIG. 4 in conjunction with bandpass filter 426. The filtered 27 KHz reference tone is made available on conductor 428 for application to the range tone processor in accordance with the invention, which is illustrated as 500 in FIG. 5. In addition to the 27 KHz range tone reference signal applied over conductor 428, one of the 3968 Hz, 283 Hz or 35 Hz reference tones produced by PROMS 440, 446 or 452, respectively, is selected by multiplexer 466 in response to range tone selection signals applied over data path 100. The selected reference range tone is applied to a DAC 468 for conversion into quantized analog form, and is filtered by a low pass filter 470 having a cutoff frequency near 6 KHz. The resulting filtered reference range tone is applied over a conductor 472 to the range tone processor 500 of FIG. 5.

FIG. 5 is a simplified block diagram of a range tone processor in accordance with the invention. In FIG. 5, a 104 MHz crystal (XTAL) oscillator 536 produces master clock signals for application to a fine range or time counter 514 and to a further counter 538. Counter 538 divides by thirteen to produce the 8 MHz clock on conductor 460 for application to 462 of FIG. 4, and also divides by 6.5 to produce a 16 MHz clock signal on a conductor 539 for application to a counter 526. Also in FIG. 5, baseband range tones are received over conductor 45 from downconverter 34 of FIG. 1, and are applied in common to an FM demodulator 510 and to a PLL 512 PLL 512 is a narrowband PLL corresponding to PLL 312 of FIG. 3. PLL 512 responds to the unmodulated 27 KHz range tone and also responds to the 27 KHz component of the frequency-modulated 27 KHz range tone. Thus, PLL 512 always receives a 27 KHz range tone component as an input at any time at which range tones are received. PLL 512 produces a filtered 27 KHz tone, which is applied to the STOP input terminal of a counter 514. Counter 514 also receives at its START input terminal the reference 27 KHz range tone from range tone generator 400 of FIG. 4. Counter 514 counts high frequency clock pulses from oscillator 536 beginning at the time of each positive-going zero crossover or crossing of the reference tone until it stops counting upon the occurrence of the next following positive-going zero crossing of the delayed 27 Khz range tone received from PLL 512. The number of clock pulses counted represents the time interval corresponding to the delay of the range tone in the generating and transmitting apparatus, in the receiving apparatus, and in propagation between the spacecraft and the ground station. As described below, time attributable to equipment delays may be calibrated out. The 12-bit high-resolution time or range signal produced by counter 514 is applied to an input of a supplemental processing unit (CPU) 528, which is a part of phase indicating device 48.

When the received range tones includes a frequency-modulated 27 KHz range tone, FM demodulator 510 of FIG. 5 responds by producing one of the 3968 Hz, 283 Hz or 35 Hz range tones. The demodulated range tone is applied by way of a conductor 516 and a buffer 518 to inputs of a PLL 520 and of a low pass filter (LPF) 522. Phase lock loop 520 operates at 3968 Hz with a 5 Hz bandwidth to filter a 3968 Hz tone when it is present, and applies the filtered tone to an input of a multiplexer 524. Low pass filter 522 has a cutoff frequency near 300 Hz, so it can pass both the 283 Hz and the 35 Hz tones to another input of multiplexer 524. Multiplexer 524 selects either the 3968 Hz range tone, or that one of the 283 Hz or 35 Hz range tones which is present, under the control of selection signals applied over data path 100, and applies the selected one of the 3968 Hz, 283 Hz and 35 Hz tones to the STOP input of counter 526. A selected reference range tone is applied to the START input of counter 526 over conductor 472 from range tone generator 400 of FIG. 4. Counter 526 counts 16 MHz clock pulses received over conductor 539, from beginning at the first-positive going zero crossing of the reference range tone applied to the START input and ending at the first positive going zero crossing of the delayed range tone applied to the STOP input. The resulting 12-bit signal provides an indication of the time required for transit of the selected range tone through the range tone generator, receiver, and the space between the spacecraft and the ground station. The 12-bit time or range-representative signal produced by counter 526 is applied to a second input of CPU 528. CPU 528 converts the time-representative signals from counters 514 and 526 into phase signals which can be used by host computer 50 (FIG. 1) in the same manner in the prior art.

CPU 528 receives the 12-bit time-representative signals from counters 514 and 526, and also receives time code signals over a conductor 532 from a source (not illustrated). Simple algorithms relate measured time to phase, if the frequency is known. The frequencies are known to CPU 528 by virtue of the range tone selection signal applied over data path 100. CPU 528 converts the two time measurements to phase, and time-tags each phase-representative signal with a Universal Coordinated Time (UTC) code, so that time consumed in later processing does not result in an error in the time to which the calculated range is ascribed.

FIG. 6 is a more detailed diagram of counter 14. FIG. 6 is a simplified block diagram illustrating some details of counter 514 of FIG. 5, together with portions of FIG. 5 for reference. Elements of FIG. 6 corresponding to those of FIG. 5 are designated by the same reference numerals. In FIG. 6, 104 MHz oscillator 536, counter/divider 538 and certain other portions are implemented using high-speed technology. At the current state of the art, ECL logic is desired, with transmission-line techniques at appropriate locations, as known in the art.

The 104 MHz clock from oscillator 536 is applied by way of conductor 537 to a start/stop pulse generator 614, a 16-bit ECL counter/shift register 618, count-up control logic 616, shift control logic 624, and sample control logic 622. In general, counter/shift register 618 counts 104 MHz clock pulses when commanded by control logic 616. The count of counter 618 represents a number of 104 MHz clock pulses, thereby indicating range with a resolution near the 9.6 nanosecond period of the 104 MHz clock, corresponding to less than plus or minus 3 meters. Noise and system inaccuracies may exceed this amount. In order to overcome some of these effects, counter/shift register 614 is commanded to count for a selected number of range samples with the 27 KHz range tone, under control of a SAMPLE SELECT input on data path 620, to thereby produce an accumulated count from which an average range can be extracted, averaged over the selected number of samples. The number of samples can be selected to be 1, 2, 4, 8, 16, 32, 64 or 128. When a particular number of samples are taken, as for example 16 samples, the range-representative time count accumulated in counter/shift register 614 is sixteen times greater than it would be if only one range sample were taken. Averaging is accomplished by shifting the count left to accomplish division by 2.sup.N ; for the case of sixteen, 2.sup.N =16, and N=4; as the count is shifted left four times. The sample select signal is applied over data path 620 to sample control logic represented as a block 622, which is essentially a one-of-N converter, which drives one of eight lines of a data path 623. Data path 623 is coupled to shift control logic illustrated as a block 624. Shift control logic 624 responds to the selected conductor of data path 623, and when the accumulated count is completed, causes counter/shift register 618 to shift "left" by the appropriate amount.

The reference 27 KHz tone is presented to start/stop pulse generator 614 of FIG. 6 by way of conductor 428, and the delayed-27 KHz tone is applied over conductor 612. Each of the tones is applied to a high-gain comparator (not illustrated) in generator 614 to produce sharp transitions at the zero crossing, and reference and delayed pulses are produced in response to the positive-going transitions of each tone. The pulses are coupled to count-up control logic 616, which toggles upon the occurrence of each pulse to produce a count-enabling logic level at the count (CNT) input of counter/shift register 618 during the period between the reference and delayed pulses. Thus, during each interval between reference and delayed pulses, counter/shift register 618 counts the 104 MHz clock pulses, to produce an accumulated count on a 16-bit data path 619. The four least significant bits (LSB) of data path 619 are not used, so only the twelve most significant bits (MSB) are coupled to a 12-bit ECL latch 626. Latch 626 responds to the completion of the shift-left command from shift control logic 624, applied over a conductor 630. Once the accumulated count is latched in latch 626, counter/shift register 618 is free to begin another counting and accumulation cycle. The output of latch 626 is converted from ECL to TTL logic levels by ECL/TTL level converter 628, and the count is made available on data path 612 to CPU 528 (FIG. 5). It should be noted that counter/shift register 618 does not necessarily count consecutive 27 KHz pulses when accumulating, but only needs any N samples.

Counter 526 of FIG. 5 operates at a lower clock frequency and need not incorporate ECL logic.

As so far described, the invention simultaneously produces signals representative of the relative phase of two range tones. Consequently, two separate computers such as computer 50 of FIG. 1 can be addressed simultaneously with information allowing continuous high range resolution together with ambiguity resolution. Alternatively, one computer may alternately read the high and low resolution phase information tagged with the time code, and provide unambiguous range.

Other embodiments of the invention will be apparent to those skilled in the art. For example, more or fewer range tones may be used than four, and their frequencies may be selected within the general range from 15 Hz to 50 KHz or more, depending upon the particular satellite or spacecraft. The counters may count at frequencies higher than 104 KHz, as available technology may permit, to thereby provide improved range resolution.