Clamping Circuit for Data Transfer Bus

The present invention generally relates to computer data transfer systems, and more particularly to means for increasing the data transfer speed of data buses suitable for use in microprocessor chips.

Prior art data transfer systems, such as the system 100 in FIG. 1, often contain a pre-charging transistor 102 coupled to the data bus 104 for precharging the bus 104 to a logic high level (e.g., 5 volts). This approach normally assumes that it is faster to pull the bus voltage down to a logic low level (e.g., 0 volts) from the logic high level, than the reverse. The pull-down transistors 106, 110 and 114 with their respective bus logic 108, 112 and 116 are operated to pull the bus voltage down to the logic low level by creating conduction paths to ground when activated.

The bus 104 is maintained at a logic high voltage, which voltage is nearly instantaneously available at an input of an inverter 118. The bus 104 is pulled down when a logic low voltage is to be provided to the inverter 118. Pre-charging can thus increase the operating speed of data transfer systems.

However, repeated pre-charging cycles without the intervention of a pull-down operation can raise the pre-charge voltage to such a high level that the overall advantage of pre-charging is lost since the time for going from the logic high voltage to the logic low voltage is directly proportional to the precharge voltage.

U.S. patent application Ser. No. 284,644 entitled "High Speed Computer Data Transfer System" and assigned to the assignee of the present invention teaches the use of a clamping circuit to solve the above problems. That application is hereby expressly incorporated by reference. The present invention is directed to producing a more reliable data transfer system wherein body effect upon the pre-charging regulation components is reduced (thus for example, threshold voltages are more stable). Body effect is the effect upon semiconductor components caused by built-in voltages in the substrate layer.

It is an object of the present invention to provide a data transfer system with high data transfer speed.

It is also an object of the present invention to decrease bus transition times for changing from the pre-charge voltage level to the pull-down voltage level.

It is a further object of the present invention to reduce body effect in the pre-charging regulation components.

It is another object of the present invention to implement such a data transfer system using complementary metal-oxide-semiconductor (CMOS) technology.

It is yet another object of the present invention to implement a data transfer system meeting the above objects in a microprocessor chip.

There is provided in accordance with the present invention a high speed computer data transfer system for transferring digital data. The system has a data transfer bus, a pre-charger connected to the data transfer bus for pre-charging the bus to a voltage representative of a first logic level, and a pulling circuit connected to the data transfer bus for pulling the bus from the first logic level to a voltage representative of a second logic level. Additionally, the system has a diode-type clamping circuit connected to the data transfer bus for preventing the bus from exceeding a threshold voltage during pre-charging, whereby the time for transition from the first logic level to the second logic level is decreased.

The details of the present invention will be revealed in the following description with reference to the aforementioned drawings.

FIG. 1 is a generalized schematic diagram of a prior art data transfer system.

FIG. 2 is a detailed schematic diagram of the present inventive data transfer system.

FIG. 2 shows the preferred embodiment for a high speed computer data transfer system 200 implemented using CMOS technology and having a data transfer bus 202 that transfers data in the form of logic high and logic low voltages. All transistors are of the junction field-effect type (JFET), with a bubble at the gate indicating a p-channel device, and the absence of a bubble at the gate indicating an n-channel device.

A pre-charge transistor or pre-charger 204 is connected at its drain to a 5 volt power source V.sub.DD at 206, which power source is controllably transferred to pre-charge the bus 202. The source of the transistor 204 is connected to the bus 202 at node 208 while its gate is connected at 210 to a combination pre-charge control and delay circuit 249, to be detailed infra, and to the gate of a transistor 212.

The transistor 212 in combination with transistors 216 and 220 serve as a bias voltage setter in a clamping circuit 209. Transistors 216 and 220 are joined at their drains via node 218, and the drain of transistor 212 is also connected to node 218. The transistor 216 is connected at its source to the 5 volt power source V.sub.DD at 217, while the source of the transistor 220 is connected to ground at 222. In the preferred embodiment the bias voltage (at node 218 and hence 224) is set at approximately 2.5 volts by adjusting the ratio of transistor 216 to transistor 220 while transistor 212 is conducting.

A clamping transistor 226 has both its gate and drain connected to node 224 from whence its bias voltage is supplied. The clamping transistor 226 is also connected by its source to the bus 202 at node 231. The transistor 220 conducts to allow charges from the clamping transistor 226 to clamp the bus voltage only when an enabling signal (signifying the beginning of a pre-charging cycle) is received at its gate from node 214. The enabling voltage at 214 appears when a logic high signal received at the gates of transistors 212 and 204 indicates the beginning of a pre-charging interval. During the pre-charging interval the transistor 212 connects the input node 214 to the output node 218 of an inverter formed by transistors 216 and 220, setting node 218 at 2.5 volts and enabling transistor 220. Transistor 216 is always prepared to conduct, and will conduct when a conduction path to ground is created by transistor 220 in the pre-charging interval. Whenever the bus voltage exceeds the bias (or threshold) voltage during a pre-charge cycle, both transistors 220 an 226 conduct to remove excess charges, thereby clamping the bus voltage.

The transistor 226 thus functions as a diode which unidirectionally conducts to remove excess charges from the bus 202 when the bus voltage exceeds the diode bias voltage (or clamping voltage). Empirical evidence has shown that the body effect experienced by the diode clamping circuit 209 is lower than that for the clamping circuit in the previously incorporated U.S. patent application Ser. No. 284,644. The remaining components of the system 200 will now be described.

A pull-down circuit 229 pulls the bus voltage down to a logic low level when desired, and operates as follows. A latch 230 temporarily stores data to be transferred onto the data bus 202. A transistor 232 connected at its source to ground at 234 is capable of pulling the bus voltage down from the logic high voltage level to the logic low voltage level when the latched data (connected to the gate of the transistor 232) are logic high values. However, transistor 236, connected to the bus 202 at node at 238, only allows pulling-down during positive clock cycles of a clock signal CLKN when a control signal CONT B indicates that pulling-down is to occur.

The pull-down control signal CONT B and the clock signal CLKN form inputs 240 and 242 of a NAND gate 244. The output signal of the NAND gate 244 is inverted by an inverter 246, and is then transferred to the gate 248 of the transistor 236 to control the transfer of data.

The clock signal CLKN is also applied via input 250 to a series of NAND gates 252-258, which form part of the pre-charge control and delay circuit 249. As shown, the second input of the NAND gate 252 is connected to the power source V.sub.DD at 260. Both the clock signal and the output signal of the NAND gate 258 are applied to a NOR gate 262. Similarly, the clock signal and the output of NAND gate 258 are also applied to the inputs of a second NOR gate 264. The NOR gates 262 and 264 are connected at their outputs to node 210, and serve as drivers for the pre-charge transistor 204.

The series of NAND gates 252-258 are included in the circuit so that data selected can be completely transferred prior to the onset of the pre-charging cycles. In other words, the pre-charging cycles do not begin until after the end of the falling edge of the clock signal. This prevents the disturbance of data transfers by the pre-charger 204.

Data at input 268 are inverted by an inverter 270 which serves as a bus driver, and are selectively transferred by a CMOS driver circuit 267 having a CMOS switch made of transistors 272 and 274. The operation of the CMOS driver circuit 267 is controlled by the combination of a control signal CONT A at 276 and the clock signal CLKN at 278, both of which are inputs to a NAND gate 280. The output of the NAND gate 280 is connected to the gate of the transistor 272 and to an inverter 284. The output of the inverter 284 is applied to the gate 286 of the transistor 274. A logic high control signal at 276 causes the CMOS switch to conduct when the clock signal has a logic high value. Likewise, a logic low control signal halts conduction of the CMOS switch.

The CMOS driver circuit 267 illustrates how the bus 202 can be driven by input driver circuits other than pull-down circuits, such as the pull-down circuit 229. The CMOS driver circuit 267 has the ability to drive the voltage level of the bus 202 either high or low. In those cases where the high voltage introduced by the CMOS switch exceeds the bus threshold voltage (2.5 volts) the clamping circuit 209 is activated to clamp the bus voltage in the same manner as when the pre-charge voltage alone exceeds the threshold voltage. Although only one CMOS driver circuit 267 and one pull-down circuit 229 are shown in FIG. 2, it will be appreciated by those skilled in the art that additional driver and pull-down circuits may be connected to the data transfer bus 202.

Data transferred by the data transfer system 200 are inverted by an inverter 288 prior to being output at the data transfer system output 290.

Variations and modifications to the present invention are possible given the above disclosure. However, such variations and modifications are intended to be within the scope of the invention claimed by this letters patent.