Tone and Announcement Message Code Generator for a Telephonic Switching System and Method

This invention relates to an apparatus and a method of selectively providing tone and announcement message PCM codes to different channels of a telephonic network and, more particularly, to such a tone and announcement generating apparatus and method in which different preselected sequences of tones and announcement codes are selectivley provided to, and selectively received from, a plurality of time division multiplexed channels associated with the generating apparatus.

In telephonic switching networks, there is a need for automatic communication between the network control and the individual telephonic transceiving units. This communication takes two different forms of messages: tones and announcements. Tones are single, multiple, or alternating frequencies, and are continuous or intermittent. Familiar examples of such tones include the busy tone, ring back tone, dial tone, and touch tones. The announcements are voice communications such as "Your call cannot be completed," and "Calls are now being taken at . . . ". These tone and announcement messages have been stored in memory in the form of binary, pulse code modulated, or PCM, signals which may be referred to generically as message codes. The message codes comprise a series of binary words representing the amplitudes of a corresponding series of samples or segments of the tone or announcement. When these message codes are converted to analog form, they produce an audio signal convertible to sound by means of an electromagnetic speaker.

In a time division multiplexing system, it is necessary to selectively provide these message codes to a plurality of different telephonic transceiving units respectively associated with a plurality of time slots or channels which compose a multi-channel time division multiplexing frame. In the past, a separate ROM (Read Only Memory) has been provided for each multifrequency tone code, and the sample words have been read out simultaneously from all the ROM's, one word per frame per tone being read out and available during essentially the entire frame. To switch a tone to a desired destination in a switching network, the output of the tone of that ROM was sent into the switching network in the network time slot, or channel, associated with the desired destination requiring such a tone.

In U.S. Pat. No. 4,205,203 of Mehta et al., issued May 27, 1980, to the predecessor in title of the assignee of this application, instead of the tone codes being made available during essentially the entire time interval, each multi-channel cycle, or frame, and switching each tone code sample into a channel time slot, or channel, the individual tone codes samples are made available only during the relatively short time slot, or channel, of each frame when the tone code is needed. Command signals received asynchronously from a central control unit results in the outputing of any desired one of many tones in any desired one of the several time slots within the recurring cycles, or frames. In addition, a predetermined selection of certain "fixed tones" is provided. These are always outputed in preassigned time slots of every frame, while other tones are selectively switched into the remainder of the time slots or channels. Operational sound samples held in a main memory at successive address locations are selected by applying, during one time slot of one cycle, address signals read out of a certain location of a next-sample read/write memory and, thereafter, inserting into that certain location, new signals which are incremented or decremented by one in relation to those previously existing, and writing out the new address signals during the same time slot of the ensuing cycle.

While this tone generator operated satisfactorily, there were some disadvantages. No provision was made for handling any message codes other than tone codes. There was no capability of providing announcement message codes for voice communications. Flexibility was limited because all message codes of a given sequence had to be stored in consecutive address locations because only identification codes were stored. The remaining addresses had to be derived from the address for the first sample of the tone sequence.

Limitations were also present. Since the tone codes were preferably stored in read only memories, there was no ability of reprogramming the tone code memory via the telephonic network, and of course, there was no message recording capability. Moreover, the tone codes could not be down loaded into the tone code memory from a central tone code memory, and thus, a change of tones required a change read only memories. In addition, periodic tone signals were generated by storing only the tone portion and then periodically gating the PCM codes of the tone in accordance with a preselected duty cycle memory. Accordingly, the stored PCM signals had to be given special treatment as compared to the PCM codes of other tones which also reduced system flexibility.

It is therefore the principal objective of the present invention to provide an apparatus for generating tone and announcement message codes for a telephone switching network and method which overcomes the aforementioned disadvantages and limitations of known tone and announcement generators and generating methods.

This objective is achieved in part through provision of an apparatus and method of selectively providing tone and announcement message PCM codes to the different channels of a multichannel telephonic switching network in which a large repertoire of preselected tones and announcements is stored and available upon request for playback to any one of the transceiving units of the network, such as handsets, facsimile machines and computer interface modems. Selectively, in accordance with asynchronous control signals from a controller, the controller is responsive to the status or condition of the multiple channels to automatically select the appropriate tones and announcements to be provided to each of the channels. Advantageously, in order to obtain maximum storage efficiency, the various tones and announcements are stored in the same memory, and in any selective order, and each tone or announcement can be of any selected duration within limits and can be combined in any selected combination for playback. The same tone or announcement may be provided simultaneously to any combination of channels or even all channels on a time division multiplexing basis without limitation, so maximum utility is achieved. Periodic tone signals are stored in their entirety along with duty cycle information to eliminate separate storing of duty cycle information and special treatment of periodic tone signals as compared to other tones and announcements to increase flexibility.

Another advantageous aspect of the invention is provision of means and a method for enabling a tone and announcement message code memory to receive and record PCM code formatted audio signals from selected ones of the plurality of channels for later playback.

In addition, provision is also made to enable down loading of PCM message codes from a central memory unit of the telephone switching network. Likewise, means and a method are provided for up loading messages stored in the tone and announcement message code generating apparatus to the central memory unit.

These advantageous features are achieved in the tone and message announcement message code generating apparatus of the present invention by providing it with means for storing the message codes in a message memory at addressable memory locations therein, means for temporarily storing a sequence of addresses of selected ones of the addressable memory locations for each channel of said multichanneled telephonic switching network and means for selectively, sequentially writing out the message codes at the addressable locations of said sequence of addresses of each of said channels to the telephonic network during a succession of time slots of said channels, respectively, and a method of utilizing these elements of the apparatus to generate andy combination of tone and message codes on any or all of the plurality of time division multiplexing channels.

In a preferred embodiment of the invention, the tone and announcement message code generating apparatus comprises a message memory, a multichanneled interface circuit, a share memory, a controller and a sequencer, or state machine. The message memory stores a repertoire of PCM encoded tone and announcement messages, respectively, at a plurality of addressable message memory locations. The multichanneled interface circuit interconnects the message memory with the telephonic switching system, and a share memory stores identification codes for selected ones of said plurality of message memory locations for each of a plurality of time slot channels. The controller issues command signals with respect to each of the time slot channels in response to a central computer of the telephonic network. The sequencer is responsive to the controller for selectively causing the message memory to successively read out through the multichanneled interface circuit the plurality of messages at said selected ones of the plurality of addressable memory locations for each of said time slot channels in accordance with a command signal directing it to do so.

One of the objects of the invention is also achieved through provision of a tone and announcement message code generating apparatus comprising a message memory, a multichanneled interface circuit and means for controlling the message memory for storing messages form a selected channel of the telephonic switching network. The message memory stores a plurality of PCM encoded announcement messages at a plurality of addressable memory locations, and the multichanneled interface circuit interconnects the message memory with a plurality of channels of the telephonic network. The controlling means controls the message memory to store a selected PCM encoded announcement received through the telephonic interface circuit from a selected channel of the telephonic network at selected ones of the plurality of memory locations.

A further object of the invention is achieved through provision of an apparatus for generating tone message codes for a telephonic switching network comprising a local tone message memory, a multichanneled interface circuit and means for controlling the tone message memory for down loading PCM encoded messages from a central memory of the telephonic switching network. The local tone message memory stores a plurality of PCM encoded tone messages at a plurality of addressable memory locations, and the multichanneled interface circuit interconnects the message memory with a central tone memory of the telephonic switching network. The controlling means controls the tone message memory for sown loading PCM encoded tone messages from the central tone memory of the telephonic switching network at selected addressable memory locations of the tone message memory.

The objective is also obtained by provision of a method of selectively providing PCM codes for a plurality of tones and announcements to a plurality of different time division multiplexing channels of a multichannel telephonic switching network having a central control computer. The steps of the method first include the step of storing the message memory to plurality of tones and announcements in a message memory to addressable memory locations therein. A representation of a sequence of addresses of selected ones of the addressable memory locations for each channel of said multichannel telephonic switching network is temporarily stored in a reprogrammable memory in response to asynchronous command signals form said central control computer. Different command signals cause temporary storage of representations of different tones and announcements. The message codes at the addressable memory locations of said sequence of addresses are then selectively seqentially written out to each of the channels of the telephonic network during a succession of time slots of said channels, respectively.

The objective of the invention is also achieved in part through provision of a method of generating a periodic tone signal for a telephonic switching network in which both the tone portion and the silent, or nontone, portion of the periodic signal are stored at the same addressable memory location to facilitate flexibility. This method includes the steps of storing in PCM code a plural number of cycles of the tone corresponding to a preselected time period of periodic tone generation of the periodic tone signal at a preselected periodic tone memory location of a memory, storing a plural number of PCM codes representative of substantially zero amplitude corresponding to a preselected time period of periodic silence of the periodic tone signal adjacent to the PCM codes of the plural number of cycles of tone at the preselected periodic tone memory location, said PCM codes of plural cycles of tone together with the PCM codes of substantially zero amplitude forming at least one complete period of the periodic tone signal, and selectively reading the PCM codes of the periodic tone signal in response to a command signal from the telephonic switching network for producing an audible period tone signal.

The foregoing objects, features and advantages will be described in greater detail and other advantageous features of the invention will be made apparent from the following detailed description of the preferred embodiment which is given with reference to the several figures of the drawing, in which:

FIG. 1 is a general functional block diagram of the preferred embodiment of the tone and announcement message code generating apparatus, or message code generator, of the present invention shown as connected with a telephonic switching network;

FIG. 2 is a partially schematic diagram of a digital auto source, or DAS, circuit which is a preferred implementation of the message code generator shown in functional block form in FIG. 1;

FIG. 3 is a block diagram, showing the positional interface between the DAS circuit or message code generator circuit of FIG. 2, and a subsystem of a telephonic switching network in which it is preferably employed;

FIG. 4 is a logic flow diagram of the memory sequence of FIG. 2;

FIG. 5 is a block diagram of a software interface programming model for the microprocessor of the controller in which blocks of relatively small size communicate in eight bit word format while the relative larger functional boxes communicate in a sixteen bit word format;

FIG. 6 shows the bitwise control information of each byte of control information prescribed for each channel in the message control-report register of FIG. 5;

FIG. 7 is a table showing the order of down loading of message address data into the share memory from which messages of different length are assembled;

FIG. 8 is a simplified flow chart of the main computer program routines required in the microprocessor of FIG. 5;

FIG. 9A illustrates the form of each command signal from the Controller of FIG. 1;

FIG. 9B is a table showing the different type of control commands from the Controller of FIG. 1;

FIG. 9C is a table showing a minimum set of recording commands from the Controller of FIG. 1;

FIG. 10A shows the form of the status report signals sent by the message code generating apparatus to the central controller of the network;

FIG. 10B is a table showing the different kinds of status reports which are provided;

FIG. 11A is a functional block diagram of the sequencer block of FIG. 2;

FIG. 11B is a timing chart for the operation of the sequencer kernel of FIG. 11A;

FIG. 11C is a functional block diagram of the control kernel block of FIG. 11A;

FIG. 11D is a functional block diagram of the message pointer block of FIG. 11A;

FIG. 11E is a functional block diagram of the Address Pointer block of FIG. 11A;

FIG. 11F is a functional block diagram of the DRAM sequencer block of FIG. 11A;

FIG. 11G is a comparative timing chart for access to the DRAM SEC of FIG. 11F;

FIG. 12 is a functional block diagram of the DAS 10';

FIG. 13 is a functional memory map of the 68000 microprocessor of FIG. 2;

FIG. 14 is a memory map for the EPROM's SRAM's and control register of the DAS of FIG. 2;

FIG. 15 is a memory map for the address pointer dual port RAM of FIG. 2;

FIG. 16 is a memory map for the control dual port RAM, or command share memory, of FIG. 2;

FIG. 17 is a memory table for the write protection memory;

FIG. 18 is a memory map for the NLI and control register memory;

FIG. 19 is a map of the DRAM memory;

FIG. 20 shows the timing for the NLI interface of FIG. 2;

FIG. 21 shows the interlace timing for the NLI of FIG. 2;

FIG. 22 is a table showing the timing specifications and limits for various elements of the message code generating apparatus of FIG. 2;

FIG. 23 is a table listing initialization procedures for the NLI of FIG. 2;

FIG. 24 is a table of the initialization procedures of an 82C55 peripheral device;

FIG. 25 is a table of the addreses of the various PROMS of the sequencer of FIG. 2;

FIG. 26 shows the specification for the timing of the NLI of FIG. 2;

FIG. 27 is a list of the sequencer PROM control signals of the message DPRAM sequencer of FIG. 2;

FIG. 28 is a list of the sequencer PROM control signals of the address DPRAM sequencer;

FIG. 29 is a listing of the control signals of the DRAM Controller of FIG. 2; and

FIG. 30 is a listing of the control signals of the NLI of FIG. 2.

Referring now to the drawing, particularly FIG. 1, the preferred embodiment of the tone and announcement message code generating apparatus, or message code generator 10 is seen as connected with multiple channels of a telephonic switching system 12 through means of asynchronous, time division multiplexing, serial, two-way link 14. The message code generator 10 has a message memory 16 which contains a repertoire of PCM encoded tone and PCM encoded announcement messages located at a plurality of addressable message memory locations. The repertoire preferably provides all the tones and announcement needs for an automatic call distribution by the telephonic switching network 12 and includes all multifrequency, or MF, tones; all dual tone, multiplexing, or DTMF, tones; call progress and signaling tones and all origin, delay and intercept announcements. In addition, in keeping with one of the objectives of the invention, customer created messages can be directly recorded into the message memory for use by the telephonic switching system 12.

In keeping with another important aspect of the invention, all the tones, customer messages and announcements can be stored in any of the addressable memory locations of the message memory 16 in any order desired to optimize flexilibity. Although certain tones or announcements can be assigned to preselected memory locations, dedication of particular locations for certain tones or announcements is not required. Advantageously, stored tones, customer messages and announcements are processed using a uniform process for both inputting and outputting.

Accordingly, the PCM codes whether causing tone, customer message or announcements are generally referred to herein simply as message codes. As an extension of this general approach, this flexiblity is enhanced and one of the objectives of the invention is achieved by storing both the tone generation period and the silent period together at a single memory location to form the full period of a periodic tone signal.

Generally, the message memory can store and operate up to a preselected number of messages (i.e. tones, customer messages or announcements) onto another plural number of time division multiplexing channels. Each of the message units can be concatenated in any order at any multiple time length on any channel and can be transmitted to any one or all channels at once, as desired, under program control. In the other direction, customers voice messages can be recorded by the message memory 16 for later use or for up loading to a central memory 12B associated with a higher order, central controller 12A of the telephonic switching system 12. On the other hand, the entire repertoire can be down loaded from the central memory 12B.

The remaining elements of the message code generator 10 includes a unique combination of a controller 18, share memory 20 and sequencer, or state machine 22 for controlling communication between the message memory 16 and the telephonic switching system 12 through a serial interface 24 in response to command signals from the central controller 12A.

The controller 18 includes a microprocessor and its associated memories for on board self diagnostics and communications with the higher level controller 12A of the system 12. This controller interfaces directly with the dual port, or share memory 20 for setting up a message pointer table with each address representing a message ID. These message pointers control the actual address of each digital tone in PCM form stored in the message memory 16. A command share memory 20B of share memory block 20 is also accessed by the controller 18 issuing commands and reading back the processing status from the state machine 22. The controller 18 also down loads PCM tones data to the message memory 16 section using the commands from, and reports all message status to, the central controller 12A through the interface 24.

The state machine, or sequencer, 22 is a dedicated hardware logic circuit including a ROM, an address comparitor, an address incrementing and interface circuits and circuits ancillary thereto. It generates the appropriate control signals to the message memory 16 to process a message. The state machine 22 interfaces directly with the share memory 20, with which also interfaces the controller 18, and executes the commands sent by the controller through the share memory 20. During each cycle of the state machine, the state machine increments the channel counts, monitors the message ending point and reports any success or failure during a message processing to the controller 18. If a message is within a specified range of locations, a PCM tone associated with that pointer location is transmitted to a selected channel in the serial interface 24. In addition to interfacing with the message pointer table, the state machine 22 also periodically monitors requests from the controller 18 in the command portion of share memory block 20, immediately updates the tone requests and reports the message processing status to the controller 18.

The dual port, or share, memory block 20 includes two dual port memories that can be asynchronously assessed by both the controller 18 and the state machine 22: a message share memory 20A and a command share memory 20B. An arbitration logic is preferably built into these devices to resolve contention if it should occur. The message share memory 20A contains the addresses of the PCM message data, while the addresses of share memory 20A preferably comprise the message IDs, themselves. The command share memory 20B contains the status from each channel and the commands issued by the controller 18 and the addresses of the command memory 20B correspond to the channels to which the commands for each channel are directed.

Referring now to FIG. 2, the functional block diagram of message code generator 10 of FIG. 1 is implemented as digital audio source circuit, or DAS, 10'. The DAS 10' is preferably located in a network termination subsystem 26 of a network subsystem 28 which, in turn, is connected with an SBX bus 30 of a control subsystem, shown in FIG. 3. Communication of the DAS 10' with the central controller 12A and central memory 12B (not shown) of the telephonic switching system 12 is through means of the SBX bus 30. Still referring to FIG. 3, the control subsystem of bus 30 is preferably a 68020/68030 microprocessor based multiprocessor, distributed processing system which is capable of either simplex or duplex operation. The network subsystem 28 consists of a system clock, or CLK, 32 and four interactive switching/control modes, each comprising a single stage, nonblocking, 772 channel time slot interchanger, or TSI, 34. 768 of these channels are broken down into 32 groups of 24 channels for interface over high speed serial interfaces known as network links to circuits including the DAS 10' of the network termination subsystem 26. A network shelf controller, or NSC, circuit 36 connected to the TSI 34 has a 6800 microprocessor with two Mbytes of DRAM to provide processing capability of signaling activity on the 768 channels of each switch mode. Within the NSC circuit 36, the 768 channel parallel time division multiplexing, or TDM, bus to and from the TSI circuit (not shown) is multiplexed into the thirty-two 24 channel 3.088 MHz serial links, or network links, to and from the network termination subsystem 26. The TSI circuit provides access to higher level processing for itself and the NSC circuit via an SBX interface 30 to an SBX circuit residing on a control subsystem secondry bus. The control memory 12B and central controller 12A are loaded via this secondary bus.

The other circuits which form the network termination subsystem 26 in addition to the DAS circuit 10' include a basic rate line, or BRL, circuit 38; a primary rate interface, or PRI, 40; one or more DSl port circuits 42; and a digital signal processing, or DSP, circuit 44. The BRL circuit provides system access to agent and supervisor consoles which the PRI circuit 40 provides termination of the twenty-fourth 64 Kbit channel of the TI digital trunk and also has all the fetures of a DS1 Port Circuit 42. The DSa Port circuit 42 provides digital T1 trunk access into the system. PCM channels are appropriately formatted and delivered to a DS1 transmit line 46. Incoming information from the DS1 link 46 are recovered, buffered and delivered to network links for access to the network. The digital signal processing circuit 44 provides three separate TMS 320C25 digital signal processor based circuits for each accessing eight of the twenty-four system channels that the DSP circuit 44 accesses over its link into the network. The DSP 44 processor receives functions for MF and DTMF and can also be used for tone metering functions in system diagnostics.

Referring now particularly to FIG. 2, the DAS circuit embodiment of the message code generator of FIGS. 1 and 2 includes as the controller 18 a 68000 microprocessor 18' operating from a 10 MHz clock 46 and provides the overall controlling functions of the DAS circuit 10'. The microprocessor communicates with higher level call processors over one of two, links or, optionally, from network links interface circuits 48 which perform the function of serial interface 24 of FIG. 1. The microprocessor 45 interprets commands for message number, channel assignment, single message or repeat, concatenation with other messages, etc. and provides corresponding control information to a memory sequencer 50 through a dual port RAM, or DPRAM, 52 interface to accomplish the command. The DPRAM 52 performs the functions of the share memory 20 of FIG. 1.

An EPROM 54 of 64 Kbytes provides basic start up diagnostic capability and a boot loader. Functional code for the DAS 10' is down loaded into a static RAM 56 for execution having 64 Kbytes of memory expandable to 128 Kbytes to allow flexible function upgrades. Memory protection logic is preferably provided for write protection of the RAM code space and allows diagnostic software to monitor for unwarranted writes to protected memory. A single network link interface 48 provides 24 PCM channels, a 768 Kbit communication link, and a system clock and sync signals to the DAS circuit 10' from the NSC circuit 36 of FIG. 2.

The message memory 16 of FIG. 1 is implemented with a two or eight Mbyte message DRAM 58 representing four or sixteen minutes of memory. Preferably, the message DRAM 58 is preferably comprised of a plurality of single 1 Mbit DRAM devices for maximum density and employs conventional DRAM control and refresh logic from DRAM controller 59. The message DRAM 58 is controlled by the memory sequencer 50 in order to provide its information over parallel TDM buses 60 into the network link interface circuits 48. In keeping with an important aspect of the invention, the contents of the message DRAM 58 can be loaded by the microprocessor 45 from down loaded files or input directly from the network link interface PCM channels for user defined messages.

As noted above, the message memory sequencer 50 receives its asynchronous command inputs from the microprocessor 45 through the buffered interface provided by DPRAM 52. The memory sequencer 50 accesses the DPRAM for control information that tells it logically what to do next. Information for each sequenced channel, such as "beginning address", and "ending address", is written by the microprocessor 45 into the DPRAM 52, and the memory sequencer 50 maintains its own "active address" pointer in the DPRAM 52. "Current" and "next" message pointers are given to the sequencer 50 as well as control information for repeat functions and read/write for recording. The memory sequencer 50 preferably operates in accordance with the logic flow diagram of FIG. 4. The microprocessor 45, FIG. 2, operates in accordance with primatives, pseudocodes and program listing of Appendix A.

Referring now to the remaining drawings, the operation of DAS circuit 10' of FIG. 2 in its various modes of operation will be described in detail.

Preferably, DAS 10' is designed to source up to 256 messages of random length to up to 96 time slot channels. The messages can be repetitive or not, but the total message storage time is 240 seconds. Optional additional memory will allow up to approximately another twelve minutes of recording time to be accessed.

The command from the central controller, or control complex, 12A as it arrives at the 68000 microprocessor 45 contains a channel number and a sequence of announcement numbers. The DAS 10' will automatically begin each digit when the preceding one is through. The microprocessor 45 can respond to a request to automatically repeat an announcement until a computer command is received or to a request to switch from one announcement to another. Since all messages are treated the same, origin, delay, and intercept announcements are handled identically. Software in the central controller 12A is free to set up a special configuration for each separate application and installation environment, but a few examples will be provided. For illustration however, typical scenarios are described below for the three types of announcements.

In a typical automatic call distribution (ACD) application the DAS 10' will output up to thirty simultaneous city origin announcements into 30 dedicated time slots. The origin announcements can be any length, but might be exactly one second long. A particular call can then be connected to the origin announcement asynchronously for two seconds. As an alternative, each origin announcement can be provided on a demand basis with connection of the announcement to an outbound time slot only when needed.

The announcement repertoire is down loaded into the message DRAM 58 during initialization, subject only to the size of the DRAM 58 and a limit of 256 announcements. A typical ACD system might have five, simultaneous, double phase, delay announcements output on ten different channels. In such a case, each call is connected by the microprocessor 45 to the correct announcement during successive cycles. Alternatively, certain announcements to certain channels are provided on demand.

In a typical PBX application (even for an ACD), the DAS 10' would store thirty 5-second intercept announcements or fragments. Advantageously, the microprocessor 45 can cause these to be concatenated with other fragments or tones in any order. For example, a tritone, then a series of fragments and then a postscript called, to produce a very personal and specific intercept announcement. Some fragments that could be stored would include the voice reciting of digits 1 through 0, and a pause. For example, the following intercept announcement could be assembled by the central controller 12A and output by the DAS 10': tri-tone, "The number you have dialed", "960", pause, "8653", "is not in service." pause, "Calls are being taken by", "8686". Alternatively, while a caller is waiting, he could be presented with a choice of information announcements by dialing or punching in the correct digit on his phone and thereby define his own intercept announcement.

The DAS 10' is able to be programmed to provide voice recording and editing for message composition. If the source is a telephone, an editing session could be as follows: The user dials a certain phone number which tells the central controller 12A that a request for editing is being made. The user must then key in a password on the phone keypad or from a control console terminal. The central controller 12A then directs the time slot interchanger 34 to route the message from the phone to the a DAS 10' which has been appropriately programmed and will also attach a DTMF detector to the phone line and monitor it for control information. Software in the central controller 12A will interpret the received digits as functions; such as record, stop, rewind, playback, and end session. The central controller 12A will convert these functions into commands and send them to the DAS 10' to perform these functions. The DAS 10' will respond to these commands such as record, stop, rewind, playback. The user can re-record all or part of the message several times and thereby edit the message until the user is satisfied.

A recording session is concluded when the user signals the central controller, or control complex 12A, that the message is complete and should be remembered. The control complex 12A then sends a control code to the DAS 10' to begin up loading the new message to the control memory 12B. The DAS 10' begins up loading the complete message via the serial bus 14. The user then tells the control complex 12A an assigned message number and the complex asks the user if the current message should overwrite a previous message stored under that message number, if one exists. The messages could also be identified and stored by names for the users in the hard disk of the control complex 12A. Thus, a much larger repertoire could be stored on the hard disk at any given time than would be down loaded to the DAS 10'. As a user came to the system, the various segments or messages could be listened to before deciding which one she really wants to update.

Once a user finally decides to install a certain message, an instruction is provided to the control complex 12A to install the selected message number into the system. The central controller 12A then prompts the user for various necessary information. The central controller then rearranges a new repertoire and header information such as location and length. This new file is then down loaded to a selected DAS 10'.

If a second, or backup, DAS 10' was chosen for the new repertoire, it can be gradually turned on as the DAS 10' with the old repertoire is deactivated. Since any individual channel can be trisated, the switchover can proceed without interruption to the customer. Once the switch over is complete, the central controller 12A can either treat the original as the backup DAS 10' or also down load the repertoire to the original DAS 10' and then switch in as the main unit.

Thus, the DAS 10' has functional features, as follows: (1) Continuous tone plant generation, (2) switched tone generation, (3) delay announcements, (4) origin announcements, (5) easy recording of new announcements, (6) concatenation of message segments, (7) entire function and message repertoire is system down loadable, (8) up to four minutes of message time on the main DAS 10' with up to sixteen minutes with optional add on memory, and (9) connectable to 48 or 96 channels. These will be described in greater detail below.

The entire repertorire is down loaded during initialization along with a logical/tone conversion table. The tones are treated exactly like messages to the DAS 10'. Each tone segment contains the entire period of the wave, including quiet time, if any. If a tone has no quiet time associated with it, it is is at least sixteen milliseconds long, which is the minimum time to describe the tone. The entire repertoire can be changed, increased, or decreased by down loading from the control complex 12A. The down loading process fills the entire card with tones and/or messages in any combination up to a maximum of 256 messages.

The DAS 10' communicates with the network shelf controller (NSC) 36 through a maximum of four serial links interface circuits 48. PCM samples are sourced by the DAS card, transmitted on the serial links 48 at the network shelf controller 36 and distributed via the time slot interchanger 34, where they may be sent to a single channel or broadcast to many. The software interface referred to herein refers to the interface that the 68000 microprocessor 45 sees when it looks at the hardware on the card. Where appropriate, some of the actual algorithms are illustrated.

The 68000 microprocessor 45 is connected to all the resources of the DAS 10' as shown in the software interface programming model of FIG. 5 which shows by relative size which are the eight bit wide locations and which are sixteen bit wide locations, so that the appropriate read/write access can be coded.

Upon initialization, the NLI circuits 48 will clear all of their registers and the 68000 microprocessor 45 will reset its peripherals and begin executing from its reset vector address. The 68000 microprocessor 45 must then program the desired channel numbers into the position registers of the NLI circuits 48 and reports to the NSC circuit 36 via the serial links. The NSC circuit 36 constantly polls the serial links, receives the message from the DAS 10; and starts establishing communication.

A quiet tone function code should be loaded into both the next message pointer table 62 and the current message pointer table 64 for each of the 96 channels. The sequential-read status should be set up in the message control-report register table 66 for all 96 channels. A loop is begun which assures that all 96 channels of the message control report register 66 will be looked at at least once every twelve milliseconds. The select registers of the NLI circuits 48 should initially be set to tri-state all the channels for now.

The 68000 microprocessor 45 then performs self diagnostic tests and when completed, sets the LED status indication (not shown) by writing to the appropriate LED port via the LED'ed control register 68. The 68000 microprocessor 45 then tells the control complex 12A that it is available and awaits instructions.

The message control report register table 66 is made up of 96 bytes of control information corresponding to the 96 channels. Each byte contains bit wise control information of the form shown in FIG. 6.

The abort request bit D6 causes the sequencer 50 to advance the next message pointer 62 to the current message pointer table 64 the next time that it services that particular channel. This is necessary at the beginning to initialize all channels with desired messages. If this is not set, then the next message pointer 62 will be advanced when the next end of message is detected by the address comparator. The abort request signal will then be cleared by the sequencer.

The end of message report bit reports to the 68000 microprocessor 45 when the end of message is detected by the address comparator. EOM report, when set high, indicates that the end of a current message has been reached and the message in the queue or next message pointer 62 has been transferred to the current message pointer 64 and is being processed by the sequencer 50. Since the hardware will have advanced the next message pointer 62 to the current message pointer table 64, it means that the hardward is working on the last message. The 68000 microprocessor 45 must then supply the next message pointer 62 with the next message from its queue or put a quiet tone to end the message. Since the shortest message is about thirteen milliseconds, the 68000 microprocessor 45 has about thirteen milliseconds to update that next pointer in the message DRAM 58.

The play/read NOT bit D5 tells the sequencer 50 whether the channel is set for reading from the NLI 48 to the message DRAM 58 or writing from the message DRAM 58 to the NLI 48. For almost all channels this bit 70 will be set for writing to the NLI 48, except for the channel (or channels) selected for recording.

The error report bit D1 is set high when an address comparator detects that the active address is greater than the end address of this particular channel which could be due to an error in the message number, the address pointer or the end address for that message number. The sequencer 50 will take no other action and will continue possibly outputing incorrect PCM message data out on this channel. It is up to the 68000 microprocessor to check the message pointer ram and address pointer ram to pinpoint the problem and turn off that channel's output, if necessary.

Bit D2 to D7 are always at high logic when read back from the message control-report register 66.

An LED port of the control register 66 contains latches and drivers which remain in the state that was last written to them. This port is readable to check the current register status. The LED bits, red, green, yellow, when set low will turn a corresponding LED (not shown) on. Upon power up, all three LEDs should be lit. A test bit of the LED port is reserved for factory frame tests, and a bus error disable bit, when set low, will override write protection bus error circuitry, so means that the processor can write to protected memory areas without causing bus error. However, a bus error timer is still activated for incomplete memory cycles. Upon power up, this bit is cleared. A TL23EN bit is used to enable the two optional network link circuits 48, FIG. 2. This bit when set will allow a full 96 channels capability. Upon power up this bit is cleared and defaulted to only two primary link 0 and 1. A sequencer on bit when set high, will allow the sequencer 50 to access the message DRAMs 58 interleaving with the processor. Upon power up, this bit is cleared. A DRAM lock bit, when set high, will disable the microprocessor 45 to access all message DRAMs 58. An access violation would result in incomplete memory cycle and a bus error cycle will be asserted. Upon power up, this bit is cleared.

The front panel has three LEDs 70, FIG. 2, which indicate status of the DAS 10' for diagnostic purposes. A greeN in service light indicates that the card has established contact with the NSC 36, FIG. 2, on the serial link and that at least one channel time slot is being written to or read from on the serial interface chip. A red LED indicates an error occurred that affects the card function and the 68000 microprocessor 45 is unable to recover from the error. A yellow light indicates a fault of the DAS 10' has been detected and the 68000 microprocessor 45 is in the process of recovering from the fault.

The software program ROMs 72, FIG. 5, of the DAS 10' performs overall control and communications and maintenance functions. The software section referred to herein is the section that the 68000 microprocessor 45 must operate, and is viewed from the perspective of the microprocessor 45. It communicates with the central controller 12A through the network link and sets registers inside the NLI 48 to select which time slots will be connected. The software also performs the queuing function of each channel by adding to it from the central control and popping from it to the hadware section of the card. It monitors the status reports from the hardward and either pops from the queue and/or reports the information up to the central controller 12A. The software also interprets commands from the central controller 12A and sets the correct codes to the sequencer 50. It is also used during message recording to keep track of available space and pointer locations. During all up loads and down loads, the software also interprets the data and correctly parcels it out to the sequencer 50. The sequencer 50 accepts down loaded data from the 68000 microprocessor 45 and stores it in a data RAM and the address pointer RAM 74, FIG. 5. The sequencer 50 also accepts commands and message numbers. The preferred form of the software is shown in the program listing and list of primatives and pseudocode of the preferred program attached hereto as Appendix A and hereby made a part of this application.

The sequencer 50 automatically sequences through all 96 channels and fetches the message pointer number, points to the correct message, points to the correct data ram location and then outputs it to the corresponding NLI 48 within its channel timeslot. Since each NLI 48 only supports 24 channels, the sequence 50 has to provide data sequentially to each NLI 48 until all 96 channels of data transfer is complete.

The software scheduler is provided in EPROM 54 (32K words) to handle communication between the microprocessor 45 and the NLI circuits 48. In addition to this EPROM scheduler, application software, message data and PCM data must be down-line loaded at initialization time from the control complex into various on-board RAMs 56. The tables below identify different types of memory contents:

1) The DAS software is loaded into the 64K words of static RAMs (organized in two banks of 32K words). This software involves executing a loop for task for assigning messages to all 96 channels and report the status of each channel to the processor.

2) The PCM samples will be downloaded to the message DRAM 58. Up to eight megabytes of memory, or sixteen minutes of messages, can be stored on this card. These PCM data include samples of the followings:

The PCM samples for each of the call progression tones.

The PCM samples for each of the DTMF/MF tone digits.

The PCM samples for each of the voice messages.

3) A file containing a concatenated form of all the messages destined for a particular DAS 10' will contain a header that contains the address of each message beginning and ending. This is the file that will actually be down loaded during initialization to two sets of the dual port static RAM 52, FIG. 2. The first set corresponding to the message share memory 20A contains the address table for each message which include three sections of 256 locations each for storing a start address, an end address and an active address of each message in DRAM 58. This memory section is organized as 24 bit wide data. The second set of dual port memory corresponding to the command share memory 20B contains four sections of 96 memory locations. These four sections are used for 1) storing message to be processed, 2) processing type requested, 3) channel status report, 4) next message to be concatenated to the on process message.

The preferred down load table for the DAS 10' is shown in FIG. 7. The microprocessor will perform a main function of keeping the sequencer 50 queued up and handling inbound and outbound mail via the network serial link. The flow diagram of FIG. 8 illustrates a simplified flow chart indicating the main routines required. The status of all 96 channels should be checked every thirteen milliseconds, popping a new message number to the ones which are ready. A secondary loop operates on the network serial control data, receiving the distributing mail as well as queueing and transmitting mail.

The software must response to a nonmaskable interupt generated by the NLI 48 as a form of watchdog timer to prevent a reset of the microprocessor 45. In addition, the interrupt from the NLI 48 to the microprocessor 45 is used to alert the microprocessor 45 of an incoming command message from the control complex 12A, and finally a ten msec interrupt provides a real time clock for the processor to process message and stay in synchronization with the rest of the system.

The single byte codes of FIG. 9B are examples of instructions required to control the DAS 10'. They are sent to the DAS 10' from the shelf controller 36 on the serial line and are received and interpreted by the microprocessor 45. The microprocessor 45 translates these functions into the proper subroutines necessary to control the sequencer 50 in the desired fashion.

In addition, there are controls that help the card record announcements. FIG. 9C shows a minimum set of recording commands. They assume that the pointer controls are all being maintained on the central controller 12A. Alternatively, more intelligent commands are given with the interpretation being performed on the DAS 10', itself. These higher level commands are play recording, rewind recording, stop, fast forward and record.

The codes of FIG. 10A that the DAS 10' sends up the line to report certain status events. The status report will contain an echo of the function being reported as well as the channel number reporting. A status code of successful or unsuccessful would follow, or if there is an up load, a number of bytes of PCM data would be contained. Some other function codes that are sent are different than just echoing the function are shown in FIG. 10B.

Referring to FIG. 12, the DAS 10' is divided into four main subsections plus the power supply: the Seq.sub.-- kernel 76, 68k.sub.-- kernel 78, NLI.sub.-- kernel 80, and the power and clock section 82. The microprocessor 45 performs intelligent queuing of messages and communicating with the control system via the serial link. It controls the input to the sequencer section.

Referring to FIG. 11A, the sequencer kernel 76 is designed to process the 96 channel messages and efficiently interface with the microprocessor 45 and the NLI 48. The sequencer 50 receives a control message from the message dual port RAM 52 as a control code. The control code pertaining to each message channel is then processed by a control section 81 in the sequencer 50. The 32 bit PROM-based state machine in the control section 81 generates a sequence of control signals to various hardware nodes for message processing.

For each channel, the process involves updating the message pointer 82, checking for the message ending and conducting appropriate action for message concatenation. In parallel with this process, the message pointer addresses 82 the message memory DRAM 58 and depending on the request, PCM data from the NLI 48 is written into memory (message recording) or transferred from memory to the NLI 48 (message sourcing).

Referring to FIG. 11B, the operational functions of the sequencer 50 and its relative time reference of different tasks is illustrated. As seen, the first operation is an access to the message pointer RAM which points to the address pointer RAM. This, in turn, points to the on going message loction of the DRAM section 84, FIG. 11A. The PCM data retrieved from this location is then written into the corresponding NLI 48. Because of this parallelism, all 96 channels can be accessed within 125 milliseconds.

Referring to FIG. 11C, the control section 81 consists of a set of PROMS 84 whose addresses are selected by a state counter 86. There is also an output consisting of the channel number for a counter 88. These two sigals each go to latches to be broadcast throughout the sequencer kernel 76.

The messge pointer section 82 is a connection RAM for the sequencer kernel 76. It contains a list of what message numbers should be put out onto each of the 96 channels. It also contains other handshaking registers for each channel that are used during normal operation.

The dual port RAM 52 is used as the message pointer and is partitioned in four sections associated with latches 90, 92, 94 and 96 as shown in FIG. 11D. The first 96 locations in each section store the corresponding information for each channel. The processor 45 communicates with the sequencer 50 through this dual port memory 52. During normal operation, the processor 45 periodically checks status of all 96 channels by reading and interpreting the data in the channel status section. If a new message is requested for a particular channel, the processor 45 writes that message number into the corresponding channel in the next message section of latch 94. Then, it also requests an appropriate action to that channel by setting up the abort code or sequencing code in the channel status section of latch 96.

The sequencer 50 operates on the other side of the dual port RAM 52, constantly processing all the messages requested by the processor and reports all channel status and message errors to the processor. The next message section of latch 94 is normally accessed by the sequencer 50. But the processor 45 can also monitor the on going message for each channel in this section of the dual port RAM 52.

The current message number is an address that points to the ADDR.sub.-- POINT ram 83, FIG. 11A. The message number tells the address pointer 83 which of the messages has been selected for this channel. The next message latch 94 is used to allow the sequencer 50 control the ability to move the next message number to the current message number when it is time to do so.

The status latch 96 allows the sequencer 50 to store each channel status temporarily after each channel message processing. The request latch 90 allows the sequencer 50 to store the requests made by the microprocessor 45 for each channel processing. The contents of the two latches are combined and are written into the message control-report section of the dual port RAM 52. The definition of the register contents shown in FIG. 6.

The dual port RAM 52 is a 1K.times.8 device but its access is preferably partitioned to make it look like three separate devices to the sequencer 50 side by time multiplexing its access. Although the microprocessor 45 can access any location at any time, it will only be writing new connections to the next message location associated with latch 94, requests and checking status in the channel status location associated with latch 96. The sequencer 50, meanwhile, checks requests, obtains the current message and, if an abort request or an end of message is detected, move the next message to the current message location. Also, it will report end of message to the microprocessor 45 in the status location, if there is a request from the microprocessor 45.

Referring also to FIG. 11E, the address pointer section associated with latch 92 contains the 24 bit address for the location of the message stored in the message DRAM 58. There are three dual port RAMs which are made to look like one 24 bit wide RAM to the sequencer 50 side, whereas the microprocessor 45 accesses these dual port RAMs in two cycles (either 2 words, or 1 word and 1 byte).

The dual ported RAMs are partitioned to contain three sections as viewed from the sequencer 50; one is the beginning address section 98 for the given message. This is stored in locations 0 through 256 and corresponds to that message number. An end address section 100 similarly contains the ending address for the given message. Slightly different, the third segment 102 contains the current address that a certain channel is pointing to. Thus, there are only 96 locations in this memory segment 102, and they are referenced by the channel counter rather than the message number like the first two.

The dual port RAM 52 is accessed by the sequencer 50 via time multiplexing to address all the segments it contains. First, the active address is moved to the A section of a comparator 104, the N+1 counter 106, and output to the DRAM section 52 for use. Next the end address section 100 is loaded into the comparator 104 B side and they are compared. If they are equal a signal is given to the control side as well as telling the N+1 counter 106 to load the begin address section 98. If they are not equal then the N+1 counter 106 is told instead to increment. Finally, the address in the N+1 counter 106 is loaded back into the active address section 102. Thus, the active location will either be given an increment or reset to the beginning of the correct message.

Referring to FIG. 11F, the DRAM 58 is accessed at most two times per 1.3 microsecond cycle and is completely controlled by the sequencer 50. Arbitration is handled by the fact that the sequencer maintains control of the DRAM 58 and allocates a certain time for the microprocessor 45 to access the DRAM 58.

Normal operation, every 1.3 microsecond, the sequencer 50 accesses the DRAM 58 using the current address from the address pointer section 83, FIG. 11A, and the control signals from the control section 110, FIG. 11F. The sequencer 50 only accesses the DRAM 58 in the first half of the 1.3 usec interval. The last half of the period is allocated for memory refreshing or microprocessor memory access. Every ten sequencer periods (.sup..about. 13 microseconds), the refresh request will be asserted from the refresh timer circuitry. The memory refresh will be given higher priority than the microprocessor access if both of them happen to request for memory access at the same. The arbitration circuitry will resolve this priority during the sequencer access period and allow the refresh cycle to start immediately after the access cycle of the sequencer 50. The microprocessor 45 can then be delayed two and a half sequencer cycles or 3.4 usec at most (worst case) before it can access the memory.

The sequencer control section 81 is run on a twelve Mhz clock, and uses sixteen phases per 1.3 microsecond cycle. The 80.1 nanosecond clock is referred to simply as the clock. The sequencer controller section 81 first allows the sequencer 50 to access the DRAM 58. Then it releases the DRAM port to either the microprocessor or a refresh cycle, if it happens to occur. Since the refresh request only occurs at the end of every tenth channel frame (1.3 uSec per channel frame), the sequencer control section 108, FIG. 11F, will always sample for this refresh signal at the end of each frame as part of the sequencing routine. In normal operation, the microprocessor 45 is granted the DRAM access immediately after the sequencer access. But if a refresh request signal is activated and recognized by the sequencer controller 110, FIG. 11F, it will be allowed to refresh the DRAM and put the microprocessor on hold. In this case, the microprocessor will be held on wait states until the refresh cycle completes, follows by another sequencer access before it can complete its pending cycle.

The sequencer controller is always active and transfers data to the NLI 48, even when the data it is producing is nonsensical simply to provide a complete sequencer routine to all 96 channels. Even the nonsensical data does go to the NLI 48 but the netowrk shelf controller 36, FIG. 3, only requests data on the assigned active channels on the NLI 48 and ignores the rest of the channels.

The sequencer control provides the address strobe signal, and decodes the upper or lower bytes control signals to the DRAM controller 108, FIG. 11F. The address strobe is brought low one clock cycle after the address is available to the DRAM controller 108, initiating the read or write cycle. The DRAM controller 108 automatically generates the row and column strobes to multiplex the addresses and present them to the DRAMs along with CAS signals. Three clock cycles after the address strobe is asserted, the data is assumed to be valid on the data bus, the sequencer 50 then generates a write clock signal to clock the data into the appropriate NLI 48. One clock cycle after the write clock is activated, the address strobe is de-asserted which signals the dram controller to terminate the bus cycle.

The sequencer access begins by enabling the output of the DRAM address latch 112, FIG. 11F. This contains the next address to access, and was loaded up one clock cycle previously. One clock cycle later, which allows the address to set up in the DRAM controller 108, the typical read/write cycle is performed. The read/write signal itself is supplied by read/write registers which tells the DRAM whether this is a write to the NLI 48 or a read from the NLI 48.

The read/write function is set by the microprocessor 45 as part of the instruction in the status RAM associated with the latch 96, FIG. 11D to program the sequencer per channel basis whether reading PCM data into memory or writing PCM data out from memory to the PCM bus.

Because the microprocessor 45 writes the beginning and ending locations into the address RAM, a buffer is reserved for each message, whether reading or writing. Since the microprocessor 45 also specifies whether or not the hardware reprots when it is at the end of the buffer, during reading, the buffer can either be circular, and overwrite itself, or a one shot, after which the microprocessor 45 warns the user that his recording is truncated. The DRAM controller 108 used in the DAS 10' is preferably designed with discrete MSI devices to control up to eight megabytes of memory. The front end of this controller 108 preferably has a 3-way arbitration circuit of multiplexing the access cycle between the sequencer, the microprocessor 45 and the memory refresh cycles. This controller circuit is designed to operate in two different modes: the microprocessor control mode and the sequencer mode.

In the microprocessor control mode, the processor 45 first has to disable the sequencer 50 from the memory port completely by setting a logic "0" to the sequencer control bit (SQCON bit) of the control register. In this mode, the arbitration circuit is set to become a two way automatic arbitration between the microprocessor 45 and the memory refresh circuitry.

In the sequencer mode, the processor 45 has to enable the sequencer operation by setting a logic "1" to the sequencer control bit (SQCON bit) of the control register. This operation would activate the three way arbitration circuitry to accommodate the sequencer, the microprocessor and the memory refresh access cycles to the DRAMs.

A refresh control signal is generated by the sequencer controller and occurs every ten channels frames (.sup..about. 10 microseconds). This refresh signal is generated at the end of a channel frame from the carry output of the state machine counter. At the beginning of the next cycle, the refresh is generated at the end of a channel frame from the carry output of the machine counter of the sequencer 50. At the beginning of the next cycle, the refresh request signal is recognized by the arbitration circuit and is allowed to take over the DRAM bus immediately after the sequencer access.

The refresh cycle is initiated by the sequencer controller by asserting the RFSH.sup..about. line, FIG. 11G. The DRAM controller uses a staggering CAS (Column Address Strobe) before RAS (Row Address Strobe) refresh scheme to accommodate for all four banks of memory within the last half of the 1.3 microsecond period, as illustrated in FIG. 11G.

Still referring to FIG. 11G, after the RFSH.sup..about. line is held low, the next synchronous clock edge of the controller will generate RAS refresh cycle and the refresh counter addresses appear on the addresses of the DRAMs. The .about.RAS0 goes low first and one clock cycle later the .sup..about. RAS1 goes low. At the next clock cycle, as RAS0 goes back high, RAS2 starts to go low and so on. In other words, each RAS signal goes low sequentially, each one stays low for two clock cycles and throughout the refresh period results in only two strobes lines being asserted low at most. This refresh scheme is chosen to prevent high power surge if all eight megabytes of memory are refreshed simultaneously.

The microprocessor access segment begins, normally right after a sequencer access if refresh request signal is not activated. At the beginning of an access cycle, the microprocessor address and control signals like AS.sup..about., UDS.sup..about., LDS.sup..about. are selected through a multiplexer. The upper three address lines of the processor are used to decode the four blocks of two megabytes of DRAMs.

The AS.sup..about. is gated with the sequencer control signal to initiate the access cycle, and the data strobes are used to decode which byte of DRAMs is being accessed. As soon as the sequencer allows the microprocessor to access, the dram controller starts generating the appropriate control signals (such RAS and CAS), and in addition, a DTACK.sup..about. from the controller is generated. This DTACK.sup..about. signal is currently generated at one clock cycle after RAS goes low and goes high immediately with the AS.sup..about. at the end of the cycle. Right after the microprocessor access cycle ends, the sequencer controller disables the microprocessor address and controls latches, the arbitration circuitry then sets the priority for the next access to the sequencer.

The microprocessor access control signals generated by the sequencer:

a) Latch in the address to the 68000-Dram address latch

b) Disable the Sequencer-DRAM address latch

c) Enable the 68000-DRAM address latch

d) Enable the 68000-DRAM control latch

e) Enable the output of the 68000-DRAM data transceiver

f) Enable the DTACK signal to the 68000

The read/write signal also sets the direction of the microprocessor DRAM data receiver.

During a PCM down load process in which megabytes of data are to be transferred to DRAMs, the 68000 has the option to terminate the sequencer access priority in order to fully access the DRAM. This option takes the sequencer access priority out of the arbitrabtion circuit; therefore, the processor and the refresh timer arbitrate between themselves. Even though the sequencer access to the drams is blocked, the sequencer controller logic still functions and cycles through its sequence. This DRAM lock feature is part of the control register and is under processor control.

The microprocessor kernel consists of a communication interface with the four NLI circuits 48 on board, program memories, data memories, write protect memory and a control register for general control and maintenance.

The functional memory map allocating different memories and interface devices with the microprocessor is shown in FIG. 13. This map also shows the device sizes and memory space allocated for each device. The physical device memory map as illustrated in FIG. 14, shows the actual limit of the microprocessor address decoder for EPROM 54, static rams and control register in the microprocessor address space. These total of eight devices occupy the first megabyte of the microprocessor address space at 128k bytes each. All memories and IO port address decode are contained in two address decoder PALs in this section.

The microprocessor's program memory space consists of permanent EPROM 54, and a static RAM 56, FIG. 2. The EPROM section contains the scheduler software which the microprocessor requires for establishing an intelligent down loading link with the central controller 12A via the Serial link. The RAM 56 contains the actual application software for the card which is down loaded from the control.

The EPROM memory is designated for supervisor exception vector table, program booting, mail transfer, handler with the NLI 48 and the scheduler software. This portion of memory will reside in two 32k.times.8 EPROM's and occupy the first page on the 128K boundaries map as shown in FIG. 14.

The microprocessor program RAM 56 is assigned to the next 128K bytes on the memory map. This particular memory contains the application program for the microprocessor to communicate with the NLI 48 and the sequencer for message processing. This RAM 56 is write-protectable in each 4K word boundary, so that software can be partitioned in either program or data memory in sixteen distinct blocks. If a write protect violations occurs, a bus error input signal to the microprocessor will be asserted to initiate a bus error cycle routine.

All of these four static rams are fully decoded and organized in word size but can be accessed in either byte or word mode. The primary 32K words of static RAM 56 ranges from 020000H to 02FFFFH in the memory map whereas the upper 32K words are optional for future expansion and located from 030000H to 03FFFFH.

The dual port address table RAMS allow the processor to write new message addresses to replace unused message addresses on-line without interfering with the sequencer operation on the other port. This portion of memory is partitioned as three different dual port RAM's to contain the starting, ending and current message addresses.

These three memories are organized as 1K.times.24 bits wide. This organization allows the sequencer to bring out the whole 24 data lines with one read cycle. The processor has to perform two write cycles at two different memory locations. The first write cycle is a word write at one memory location to the first two RAMS and the second one is a byte write to the third RAM at even locations and offset by +020000H from the first word write. These three dual port RAMs occupy two pages of 128K of memory right above the program RAM and are labelled address dual port RAM low word (ADPL) and address dual port ram high byte (ASPH), respectively. The ADPL rams are organized in word size and can be accessed in both word and byte boundary whereas the ADPH rams is mapped into the odd byte of the memory map but can also be accessed in either word or byte mode but only the lower byte contains valid data.

The memory map of these three dual port RAMs for the address pointer tables are shown in FIG. 15.

The microprocessor 45 communicates with the sequencer 50 through a set of four dual port RAMs 52. The microprocessor 45 has access from one side while the sequencer operates on the other side of these dual prot RAMs.

Since the sequencer 50 only reads data out of the three address dual port RAMs 52, it should not present any contention with the processor access on the other port. If new message addresses need to be written into these RAMs 52, the processor 45 will first abort all channels from using that message and proceed with new message down load. When the new message is installed, the processor will then assign channels to that message if it is requested.

The dual port control circuitry generates the appropriate control signals to the message pointer section and the address pointer section in the sequencer kernel 76. The microprocessor hardward interfaces to the dual port RAMs 52 using lower order byte format for the message pointer section and long word format for the address pointer section. The preferred memory map for the dual port RAM 52 is shown in FIG. 16.

Port B and C of an 82C55 peripheral interface device are preferably used for setting protection to the 64K words static RAMs 56. At power up reset, all outputs of the two ports B and C are pulled down which disables access to the entire static RAM memories. The eight output bits of port B provides write protection to the first set of 32K words static ram address ranging from 020000H to 02FFFFH, as seen in FIG. 17. Each bit protects a block of 4K words of memory.

The upper 32K words of static RAM expansion is write protected in the same manner using port C for address ranging from 030000H to 03FFFFH. Since the stack pointer and the main program will reside in RAM, the power up routine should include setting memory write protection through ports B and C of the 82C55 before any attempt to access static ram memory.

All these protection bits are combined with the processor addresses in a PAL device (Write Protection PAL) to enable or disable the Ram selection during a RAM access cycle. When a write cycle attempts to access a protected memory location, the chip select to the RAM is not asserted. This will cause the bus cycle timer to time out, generate a bus error to inform the processor of the violation.

Writing a "0" to port B or C will set the write protection for the corresponding memory locations and writing a "1" will disable it. FIG. 17 shows the address protection for each bit of port B and C of the 82C55.

The four NLI's 48 of the DAS 10' are fully decoded and memory mapped into the 68000 address range as shown in FIG. 19. Each NLI 48 contains thirty two registers and can be acessed in either word or byte mode. The eight bit data of the NLI 48 are connected to the lower byte of the processor data bus.

As seen in FIG. 14, the PCM data for voice and tone messages are stored in DRAMs which start from address 800000h thru FFFFFFh. To be compatible with the sequencer access, all DRAMs can only be accessed in bytye mode in continuous memory spectrum. Its memory map is shown in FIG. 19. All eight megabytes of DRAMs are organized in four banks of two megabytes.

The basic DAS will have two megabytes or eight megabytes of DRAM memory for PCM storage which provide up to four minutes of voice message and tones. An additional six megabytes of memory can be added in to the DAS 10' for a total of eight megabytes or sixteen minutes of tones/message storage.

The processor 45 is reset by the power-on-reset (POR.sup..about.) circuitry. The power-on-reset delay from the power supply will provide an active low reset signal of at least 100 ms after VCC reaches 5 V. This signal will drive both a reset and a halt inputs of the processor 45 to assure proper start up mode.

In normal operation, the serial links from the DAS 10' are periodically polled by the NSC 36 to determine which link is active. If a link does not respond, the NSC 36 will generate a soft reset on the DAS 10' through a nonmaskable interrupt (interrupt level 7). If again, no response is received by the NSC 36, it will generate a hard reset through POR circuitry to reset the whole card. The microprocessor can also be reset by the NSC if it fails to respond to a 10 millisecond interupt, or the interrupt generated by the NLI 48 itself. Whenever the reset line goes low, the status LED's will all light up to provide a visual diagnostic of card failure. The healthy circuit should be able to turn off the Red and Yellow LEDs to indicate normal operation during its start up initialization routine.

Interrupt sources for the DAs 10' are identified as follows: 10 millisecond interrupt, NLI or communication interrupt and a non-maskable interrupt (or watchdog software reset). These interrupt signals are generated by the NLI 48 to provide communication handshaking or diagnostic check on the processor status by the central controller 12A. Autovector interrupts are preferably used in the DAS 10' to accommodate all of the above interrupt signals. The interrupt priority levels are preferably assigned as followed:

an interrupt level 7 (NMI) is assigned to soft reset (watchdog timer), generated from the network link through the NLI 48.

an interrupt level 5 is assigned to all four NLI 48 on the DAS 10'. Upon interrupted by this level, the processor will poll all four status registers inside the four NLI 48 to determine the interrupt source. All four interrupt lines from the NLI 48 are stored together to provide one single interrupt signal to the processor.

an interrupt level two to four are unused.

interrupt level one is assigned for the ten millisecond timer. As this timer runs out, an interrupt is generated. This interrupt is used for keeping track of real time on the DAS 10' and remaining in synchronization with the rest of the system.

All seven sources are input to a priority encoder whose outputs are connected to an interrupt priority level inputs of the microprocessor 45. The function control outputs of the processor are decoded for the interrupt aknowledge signal and inputs it to a VAP pin of the processor 45 to initiate the exception process.

The bus error is used to detect an attempt to access a write protected areas like the program RAM, EPROM or unused memory spaces. When this sitution occurs, the bus error signal is generated and input to a BERR pin of the processor. This BERR signal is also used to complete the on going bus cycle and initiate a bus error exception routine.

The bus error signal can be disabled by asserting the BERR.sub.-- disable bit in the control register. This would allow the processor to write to the protected memory without causing a bus error. However, the memory access timer is always active and could cause a bus error if an invalid memory cycle is detected even with the BERR.sub.-- disable bit asserted.

Each external memory or I/O access of the processor requires an asynchronous DTACK signal to complete a cycle. The processor has to support four different types of device speeds: 200 ns for EPROMs, 120 ns for RAMs, up to 1.3 us for DRAMs, and about 80 ns for I/O devices.

The address strobe and address decode signals for all devices are combined in a PAL (DTACK generator PAL) to generate a DTACK signal to the processor. At the beginning of each processor cycle, a 6.4 microsecond timer is cleared and counting up during the processor cycle. This 6.4 microseconds takes into account the worst case waiting period for the processor to access the DRAMs memory. If a DTACK signal is not available when the timer runs out, a bus is generated to indicate a faulty cycle.

As a means of checking for faulty PCM in the DRAM 58, the processor 45 will provide background diagnostics by auditing messages in the DRAM 58. If errors occur, the software will require repeat of down load of that particular message or select the standby card to become the main card.

The DAS 10' can support up to 96 channels of voice and tone, therefore requires a maximum of four NLIs. These four are memory mapped into the I/O space of the microprocessor 45 memory. The NLIs 48 communicate with the microprocessor at an interrupt level 5.

Data is transferred between the processor and the NLIs 48 through their internal FIFO's. It is possible for all four to interrupt the processor simultaneously. Upon receiving an interrupt from the NLI 45, the microprocessor 45 will read the status registers of these NLI circuits to determine which one is the interrupt source and reads data from its FIFO (currently 16 bytes deep). The status register of the interrupting device will be cleared and leave the other interrupts pending. Upon emptying the incoming data from the FIFO, the microprocessor 45 then writes its outbound data to the transmit FIFO for transmission to the network link.

There are thirty-two internal registers inside the chip that can be accessed by the processor 45. The NLIs 48 of the DAS 10' are hard wired in the DAS mode so that there is no need to initialize its operation mode during initialization process. However, the transmit and receive channels of the DAS should be stored in the EPROM 54 and should be used to set the four NLIs 48 during initialization. The optimized set of channels group should be assigned to these four NLIs are: channel two for NLI #0, channel ten for NLI #1, channel eighteen for NLI #2 and channel twenty-six for NLI #3.

There are two versions of the DAS 10' contemplated. This standard DAS 10' is designed to interface the entire card with the network serial link. The time channels inside the EPROM are written into the chip during initialization. With the above channel assignment, each time slot is 1.3 microseconds apart. Each channel data can be written into the chip asynchronously as long as all twenty-four channels are written during one time frame. Since the DAS 10' is designed for ninety-six channels, four NLIs 48 are needed and have to be time multiplexed with each other. The optimum time interval between 96 channels is approximately 1.3 microseconds. The detail timing for this mode is shown in FIG. 20.

The NLI 48 requires a 12 MHZ input clock to function. Three 12 MHZ PLL's are preferably used to generate this required clock from the 3.308 MHZ clock coming out from this chip. This clock is buffered and also used for the processor clock and sequencer clocking requirement. The NLIs interlace timing is shown in FIG. 21.

Read/write timing from AS.sup..about. active to each device (min/nom/max), timer and clock specifications are shown in the FIG. 22.

The four NLIs 48 require initialization in order to communicate with the companion ICs on the NSC cards. The basic initialization procedure consists of writing five bytes of data to each NLI according to FIG. 23. Each NLI has a unique data pattern for this particular address location i.e. the first data pattern goes to NLI-IC0, the second pattern goes to NLI-IC1, and so on.

The above procedure allows all NLI-ICs to be initialized and synchronized with the NSC links if they are available within 3 msec maximum.

The 82C55 peripheral device should be initialized immediately at power up reset. At power up, this device are reset to inputs and all outputs are cleared. Address 0E107 H of the 82C55 device is then initialized with data bytes 080 H to configure the 82C55 to a three eight-bit output control ports. FIG. 24 illustrates a sample initialization of the 82C55 peripheral device.

Four PAL's are preferably used in the DEX cards. Two of them are for address decoders, two others for DTACK generator and memory write protection generator.

The data at each PMOM location is shown in FIG. 25.

The connectors pins PA 96 (TESTOUT) and PA 32 (TESTIN or PBHALT) are reserved for system test. These signals are static logic signals. The duty cycle varies with the test clock. Pin JA33 to pin JA64 are transmit and receive serial links to and from the NLIs 48. These back plane signals are pulse width modulated (PWM) signals from the NSC to the network termination cards and are in NRZ form from the network card to the NSC card direction. FIG. 26 shows the waveforms for these signals at positive differential drive outputs.

The message DPRAM sequencer control signals, the address DPRAM sequencer control signals and the DRAM controller and NLI control signals are respectively shown in FIGS. 27, 28, 29 and 30.

While a detailed description has been provided, it should be appreciated that many variations may be made thereto without departing from the scope of the invention as defined in the appended claims. ##SPC1##