Bi-Cmos Circuit With High-Speed Active Pull-Down Output Currents

The present invention relates to a logic circuit, and more particularly to a logic circuit of Bi-CMOS construction used for driving capacitive load.

In the Bi-CMOS process that adds a part of a MOS process to a normal bipolar process and that forms bipolar elements and MOS elements at the same time, a logic circuit of high performance can be made by building a bipolar circuit having advantages of high accuracy analog processing and large power drive and a CMOS circuit having advantages of high integration and low power consumption, together on the same IC chip.

FIG. 7 schematically shows a conventional logic circuit which forms an inverter with the Bi-CMOS process. In the figure, M.sub.n1 is an input transistor made from an N-channel MOS transistor, Q.sub.1 and Q.sub.2 are off-buffer transistors made from bipolar transistors, and Q.sub.3 is an output transistor made from a bipolar transistor. R.sub.1 through R.sub.4 are resistors, and D.sub.1, D.sub.2 schottky barrier diodes. C is capacitive load, V.sub.IN an input signal, and V.sub.OUT an output signal. In a construction such as this, in order to obtain a high drive capability, Q.sub.1 and Q.sub.3 normally comprise transistors with schottky barriers, and alternatively, the areas of Q.sub.2 and Q.sub.3 are increased.

In the conventional logic circuit described above, particularly when the area of the transistor Q.sub.3 is increased to obtain a high drive capability, it is necessary to increase current that is supplied to the base of the output transistor Q.sub.3. However, since the MOS transistor (M.sub.n1) is used as a source of the base current, a sufficient amount of the base current cannot be supplied to the output transistor Q.sub.3. Consequently, there is the drawback that the output transistor Q.sub.3 is turned on very slowly, that is, the propagation delay time t.sub.PHL of the output signal V.sub.OUT increases.

Accordingly, it is an object of the present invention to make the turn-on speed of the output transistor Q.sub.3 faster and shorten the propagation delay time t.sub.PHL of the output signal V.sub.OUT.

In accordance with one important aspect of the present invention, there is provided a Bi-CMOS circuit comprising a first transistor made from an N-channel MOS transistor that is turned on and off in response to the logic state of an input signal and that supplies a first current to the base of an output transistor when the first transistor is turned on, and an active pull-down current supplying means connected to the gate electrode of the first transistor and for supplying a second current, which is active pull-down current, to the base of the output transistor so that the first and second currents can be supplied to the base of the output transistor.

The active pull-down current supplying means may comprise a second transistor made from a P-channel MOS transistor and having its gate electrode connected to the gate electrode of the first transistor, a third transistor made from an N-channel MOS transistor and having its gate electrode connected to the gate electrode of the second transistor, the third transistor being connected in series with the second transistor, and a fourth transistor made from a bipolar transistor and having its base connected to the third transistor and its emitter connected to the base of the output transistor.

The second transistor may be substantially identical in area with the third transistor. The second transistor may also be greater in area than the third transistor.

The active pull-down current supplying means may also be comprise a second transistor made from a P-channel MOS transistor and having its gate electrode connected to the gate electrode of the first transistor, a third transistor made from an N-channel MOS transistor and having its gate electrode connected to the gate electrode of the second transistor, the third transistor being connected in series with the second transistor, a fourth transistor made from a P-channel MOS transistor, a fifth transistor made from an N-channel MOS transistor and having its gate electrode connected to the gate electrode of the fourth transistor, the fifth transistor being connected in series with the fourth transistor, a line between the second and third transistors being connected to a line between the fourth and fifth transistors, and a sixth transistor made from a bipolar transistor and having its base connected to the fifth transistor and its emitter connected to the base of the output transistor.

In the present invention, during the turn-on transition period of the first transistor (corresponding to the conventional input transistor M.sub.n1), the second and third transistors are turned on, and the fourth transistor made from a bipolar transistor is turned on by the current that flows through the second and third transistors. Consequently, the current that flows through both first transistor and the fourth transistor is supplied to the base of the output transistor (corresponding to the transistor Q.sub.3), and the turn-on speed of the output transistor is thus made faster.

In accordance with another important aspect of the present invention, there is provided a Bi-CMOS circuit comprising first and second transistors respectively made from a P-channel MOS transistor and an N-channel MOS transistor that are turned on and off in response to the logic state of an input signal and that supplies a first current to the base of an output transistor when the first and second transistors are turned on, and an active pull-down current supplying means connected to the gate electrodes of the first and second transistors and for supplying a second current, which is active pull-down current, to the base of the output transistor so that the first and second currents can be supplied to the base of the output transistor.

In accordance with yet another important aspect of the present invention, there is provided a Bi-CMOS circuit comprising a first transistor made from an N-channel MOS transistor that is turned on and off in response to the logic state of an input signal and that supplies a first current to the base of a first output transistor when the first transistor is turned on, second and third transistors respectively made from a P-channel MOS transistor and an N-channel MOS transistor that are turned on and off in response to the logic state of the input signal and that supplies a second current to the base of a second output transistor when the second and third transistors are turned on, a first active pull-down current supplying means connected to the gate electrode of the first transistor and for supplying a third current, which is an active pull-down current, to the base of the first output transistor so that the first and third currents can be supplied to the base of the first output transistor, and a second active pull-down current supplying means connected to the gate electrodes of the second and third transistors and for supplying a fourth current, which is an active pull-down current, to the base of the second output transistor so that the second and fourth currents can be supplied to the base of the second output transistor. The third current supplied through the first active pull-down current supplying means is an supplied to the base of the first output transistor when the input signal makes a transition from a low to a high, while the fourth current supplied through the second active pull-down current supplying means is supplied to the base of the second output transistor when the input signal makes a transition from a high to a low.

The above and other objects and advantages will become apparent from the following detailed description when read in conjunction with the accompanying drawings wherein:

FIG. 1 is a schematic view illustrating an embodiment of a Bi-CMOS circuit in accordance with the present invention;

FIG. 2 is a timing diagram of the FIG. 1 embodiment;

FIG. 3 is a schematic view illustrating another embodiment of the Bi-CMOS circuit in accordance with the present invention;

FIG. 4 is a waveform diagram of the output signals from the FIG. 1 embodiment;

FIG. 5 is a schematic view illustrating a third embodiment of the Bi-CMOS circuit in accordance with the present invention;

FIG. 6 is a schematic view illustrating a fourth embodiment of the Bi-CMOS circuit in accordance with the present invention; and

FIG. 7 is a schematic diagram of a conventional logic circuit.

Referring now in greater detail to the drawings and initially to FIGS. 1 through 4, there is shown a preferred embodiment of a Bi-CMOS circuit constructed in accordance with the present invention. The same reference characters and numbers will be applied to the same parts as FIG. 5. Reference numeral 1 denotes a gate part that functions as an inverter. The gate part 1 comprises off-buffer transistors Q.sub.1 and Q.sub.2 each made from a bipolar transistor, an output transistor Q.sub.3 made from a bipolar transistor, and an input transistor (first transistor M.sub.n1 made from an N-channel MOS transistor. The logic state of an output signal V.sub.OUT of the inverter is determined by turning on either the off-buffer transistors Q.sub.1 and Q.sub.2 of high level side or the output transistor Q.sub.3 of low level side with an ON/OFF operation of the input transistor M.sub.n1.

That is, if the input signal V.sub.IN is in a logic low state, the input transistor M.sub.n1 is turned off and the off-buffer transistors Q.sub.1 and Q.sub.2 are turned on. Consequently, the output signal V.sub.OUT goes to a logic high state. If, on the other hand, the input signal V.sub.IN is in a logic high state, then the input transistor M.sub.n1 is turned on, a base current I.sub.B is supplied to the output transistor Q.sub.3, and therefore the output transistor Q.sub.3 is turned on. Consequently, the output signal V.sub.OUT goes to a logic low state.

Reference numeral 2 is an auxiliary drive circuit which is the gist of the present invention. Between a high level power supply V.sub.cc and a low level ground V.sub.ss, the auxiliary drive circuit 2 comprises a P-channel MOS transistor (second transistor) M.sub.p1, an N-channel MOS transistor (third transistor) M.sub.n2, and a resistor R.sub.5 which are connected in series. The auxiliary drive circuit 2 further comprises a bipolar transistor Q.sub.4 (fourth transistor) having its base connected to the line between M.sub.n2 and R.sub.5 and its emitter connected to the base of the output transistor Q.sub.3.

Assume now that the area of M.sub.p1 is substantially the same as that of M.sub.n2. This makes the turn-on speed of M.sub.n2 faster than that of M.sub.p1 by the difference of carrier mobility (the mobility of electrons .mu.n is about two or three times greater than the mobility of holes .mu.p) between the two transistors (P-channel and N-channel MOS transistors). Consequently, when the input signal V.sub.IN makes a transition from a low state to a high state, the transistors M.sub.p1 and M.sub.n2 can be both turned on instantaneously. When this occurs, current I.sub.D flows through the transistors M.sub.p1 and M.sub.n2, and causes voltage V.sub.1 to generate across the resistor R.sub.5. If V.sub.1 is greater than the total value of the base-emitter voltage V.sub.BE4 of Q.sub.4 and the base-emitter voltage V.sub.BE3 of Q.sub.3 (2 V.sub.BE =V.sub.BE3 +V.sub.BE4), then Q.sub.4 is turned on by V.sub.1 and the emitter current I.sub.B, can be added to the base current I.sub.B of Q.sub.3. That is, the total current of the current I.sub.B" supplied through M.sub.n1 and the current I.sub.B' supplied through Q.sub.4 can be employed as the base current I.sub.B (I.sub.B =I.sub.B' +I.sub.B") of Q.sub.3, so the base current I.sub.B of Q.sub.3 can be increased instantaneously during the low-to-high transition period of V.sub.IN. Consequently, the turn-on speed of Q.sub.3 can be made faster, and the high-to-low transition speed of the output signal V.sub.OUT is made faster and the propagation delay time t.sub.PHL of the output signal V.sub.OUT is thus shortened. The current I.sub.B.sub.40 functions as active pull-down current, makes the turn-on of Q.sub.3 deep, and can rapidly pull out a wiring load capacity connected to V.sub.OUT. As a result, high-speed operation can be performed.

The shortening of t.sub.PHL will hereinafter be described in accordance with the timing diagram of FIG. 2. If both M.sub.p1 and M.sub.n2 and are concurrently turned on as the input signal V.sub.IN makes a low-to-high transition, then the current I.sub.D flows through the transistors M.sub.p1 and M.sub.n2. The current I.sub.D causes the base voltage V.sub.1 of Q.sub.4 to increase. If the voltage V.sub.1 exceeds 2 V.sub.BE, Q.sub.4 is turned on and I.sub.B' flows. The current I.sub.B' is added to the current I.sub.B" that flows through M.sub.n1. As a result, since the base current I.sub.B of Q.sub.3 is increased by the amount of I.sub.B', the turn-on speed of Q.sub.3 can be made faster.

As described above, in the embodiment of the present invention, when the input signal V.sub.IN makes a transition from a low to a high, the base current of the output transistor Q.sub.3 is increased by supplying the current from Q.sub.4 of the auxiliary drive circuit 2. Consequently, the turn-on speed of Q.sub.3 can be made faster and therefore t.sub.PHL can be shortened.

Although the above described embodiment is applied to an inverter, it is noted that it may also be applied to a logic circuit in which input and output signals V.sub.IN and V.sub.OUT change in the same logic state. In that case, the area of M.sub.n2 is made smaller than that of M.sub.p1 so that the turn-on speed of M.sub.n2 can be made slower when V.sub.IN makes a transition from a high to a low. Consequently, the base current of Q.sub.3 can be increased in the same way.

FIG. 3 schematically shows another embodiment of the auxiliary drive circuit 2 of FIG. 1. In this embodiment, an auxiliary drive circuit 2' is provided at its input side with an inverter stage 3 comprising a P-channel MOS transistor M.sub.p2 and an N-channel MOS transistor M.sub.n3. When the input signal V.sub.IN makes a transition from a high to a low, the turn-on speed of M.sub.n2 can be made slower. In the same way, the base current of Q.sub.3 can be increased.

FIG. 4 illustrates the waveform of the output signal V.sub.OUT. V.sub.cc was set to 5.5 V, 5.0 V and 4.5 V, and each t.sub.PHL according to the present invention was compared with that of the conventional logic circuit. It will be understood from FIG. 4 that, with the rapid turn-on speed of Q.sub.3, the high-to-low transition according to the present invention is faster than that of the conventional logic circuit.

While the present invention has been applied in order to improve t.sub.PHL, it is noted that it is also applicable to improve t.sub.PLH. FIG. 5 schematically illustrates a Bi-CMOS circuit to which the present invention is applied to improve t.sub.PLH. The same reference characters will be applied to the same parts as FIG. 1 and therefore a detailed description will not be given. In the embodiment of FIG. 5, the base current I.sub.B' of Q.sub.4 is added to the base current I.sub.B" of Q.sub.1, so that the turn-on speed of Q.sub.2 is made faster and the propagation delay time t.sub.PLH of the output signal V.sub.OUT is shortened. In addition, the present invention is applicable to improve both t.sub.PHL and t.sub.PLH. FIG. 6 schematically illustrates a Bi-CMOS circuit in which both t.sub.PHL and t.sub.PLH are shortened in accordance with the present invention. As shown in FIG. 6, the base currents of Q.sub.2 and Q.sub.3 are increased in the same manner as those of the embodiments of FIGS. 1 and 5, so both t.sub.PHL and t.sub.PLH can be shortened.

While certain representative embodiments and details have been shown for the purpose of illustrating the invention, it will be apparent to those skilled in this art that various changes and modifications may be made therein without departing from the scope of the invention.