Color Liquid Crystal Display Apparatus

1. Field of the Invention

The present invention relates to a liquid crystal display panel driving apparatus for driving a color liquid crystal panel having color filters provided between scan electrodes and signal electrodes.

2. Description of the Related Art

A color liquid crystal panel for use in liquid crystal color televisions, etc. displays an image in full color by a combination of red (R), green (G) and blue (B) pixels. In displaying a color image by a combination of red, green and blue pixels, display of a full color image with high reproducibility requires that the luminances of these three types of pixels be balanced. Due to the wavelength dependency of a liquid crystal element, however, this property influences the color reproducibility of display pixels. This short-coming is more prominent for a color liquid crystal display element having its view angle characteristic improved by reducing the cell gap (the thickness of a liquid crystal layer).

In other words, to improve the view angle characteristic of a liquid crystal display element, the value of the liquid crystal element, .DELTA.n.multidot.d (.DELTA.n: birefringence and d: cell gap) should be set small. This is because a liquid crystal element having a large .DELTA.n.multidot.d has a large change in this value depending on the view angle (viewing direction). Since the value of .DELTA.n.multidot.d greatly changes depending on the view angle means that a large change in contrast occurs depending on the view angle. Therefore, the change in contrast which is depended on the view angle can be reduced by setting the cell gap of the liquid crystal element small to thereby make .DELTA.n.multidot.d small. According to the color liquid crystal element, however, reduction in .DELTA.n.multidot.d increases the wavelength dependency of transmitted light, as shown in FIG. 1. FIG. 1 illustrates the relation between .DELTA.n.multidot.d (.mu.m) and an amount of transmitted light (%), where "R" is a characteristic of 650-nm (red) wavelength light, "G" is a characteristic of 550-nm (green) wavelength light, and "B" is a characteristic of a 450-nm (blue) wavelength light. The presence of the aforesaid "wavelength dependency" means that the light transmittivity varies from one wavelength to another and that, in view of three-color (R, G and B) lights, the lights with different wavelengths which pass the respective filters have different intensities. This is because that the characteristic showing a change in transmittivity with respect to .DELTA.n.multidot.d differs from one light having a specific wavelength to one of the three colors to another; the greater the wavelength dependency of transmitted light, the lower the color reproducibility of a displayed image.

As a conventional solution to the above short-coming, the thicknesses of the individual color filters FR, FG and FB are set different from one another to adjust the cell gaps dR, dG and dB for pixel display sections for these colors, as shown in FIG. 2, whereby the transmittivities of the individual color lights are balanced by changing the values of .DELTA.n.multidot.d of the individual pixel display sections. FIG. 2 illustrates the cross section of the configuration of a color liquid crystal display element. Referring to this diagram, reference numerals 1 and 2 denote a pair of upper and lower transparent substrates (glass plates) facing each other with a liquid crystal layer 3 in between, and these substrates are adhered through a frame-shaped seal member (not shown). A number of parallel transparent scan electrodes 4 are arranged in stripe form on the inner wall of the upper substrate 1 (which faces the lower substrate 2) in the horizontal direction in the diagram. A number of parallel transparent R, G and B signal electrodes 5a, 5b and 5c are arranged on the inner wall of the lower substrate 1 (which faces the upper substrate 1) in such a direction as to cross the scan electrodes 4. These signal electrodes 5a-5c are respectively provided on the striped color filters FR, FG and FB, which are provided on the surface of the lower substrate 2 in such a way as to cross and face the individual scan electrodes on the upper substrate 1. FR is a red filter, FG a green filter, and FB a blue filter, and these color filters FR, FG and FB are alternately arranged, as illustrated in FIG. 2. The color filters FR, FG and FB have their surfaces covered with a transparent insulative film 6 on which the signal electrodes 5a, 5b and 5c are formed. The end portions of the scan electrodes 4 and signal electrodes 5a, 5b and 5c are extracted as driver connection terminals to side edge portions of the substrates, as shown in FIG. 3. The scan electrodes 4 are supplied with scan signals X1, X2, . . . , and the signal electrodes 5a, 5b and 5c are supplied with R, G and B image signals in association with the respective color filters FR, FG and FB. Referring to FIG. 2, reference numerals 7a and 7b are orientation process films provided on the electrode-forming surfaces of the substrates 1 and 2, and 8a and 8b are deflection plates.

With the above arrangement, a full color image with a high reproducibility can be displayed with balanced luminances of the red, green and blue pixels by changing the thicknesses of the individual filters FR, FG and FB to balance their transmittivities. In this case, with the same .DELTA.n.multidot.d for the individual pixel display sections, the red light has the highest transmittivity among the three color lights, and the green light has the second highest transmittivity, with the blue light having the lowest one. To balance the transmittivities of the individual color lights, therefore, the red filter FR for passing red light having the highest transmittivity is made thinnest, the green filter FG thicker and the blue filter FB thickest, as shown in FIG. 2. In general, therefore, there is a height difference of about 1 .mu.m between the red filter FR and green filter FG and about 2 .mu.m between the red filter FR and blue filter FB.

As described above, the conventional liquid crystal display element has a large height difference between the red filter FR and blue filter FB, so that the orientation process films 7a and 7b and transparent insulative film 6 may not be formed evenly or the insulative film 6 is more likely to be cut by the etching process for forming the transparent electrodes 4.

Accordingly, it is an object of this invention to provide a liquid crystal panel driver which can surely drive a color liquid crystal panel for image display without deteriorating the balanced light transmittivities even when a height difference between the color filters is made small, and can reduce the number of occurrence of defects.

To achieve the object, there is provide a color liquid crystal display apparatus comprising:

color liquid crystal display means, having a plurality of common electrodes, a plurality of segment electrodes crossing said plurality of common electrodes and filters of three primary colors, for display a color image by means of a plurality of pixels through said filters; and

drive means for driving said segment electrodes in a gradation according to an image signal, driving said common electrodes by a scan signal, and driving said segment electrodes in such a way as to provide a no-bias (zero-bias) period in which a voltage of said common electrodes is set equal to that of said segment electrodes to provide no-bias and which is for setting effective drive voltages of at least two of three types of pixels through said primary color filters different from each other during a non-display period of said image signal.

According to this invention, the height difference between the individual color filters can be made smaller without deteriorating the light transmittivity and the number of occurrence of defects can be significantly reduced.

FIG. 1 is a characteristic diagram illustrating the relation between .DELTA.n.multidot.d of a liquid crystal element and the amount of transmitted light;

FIG. 2 is a cross-sectional view illustrating the configuration of a conventional liquid crystal display element;

FIG. 3 is a diagram illustrating the arrangement of signal electrodes and scan electrodes of the liquid crystal display element;

FIGS. 4 through 9 illustrate the first embodiment of this invention in which

FIG. 4 is a block diagram illustrating the general circuit configuration;

FIG. 5 is a detailed circuit diagram of a data controller;

FIG. 6 is a detailed block diagram of a segment driver;

FIG. 7 is a detailed circuit diagram of segment drive voltage generator of a liquid crystal drive voltage generator;

FIGS. 8A to 8H and 9A to 9G are timing charts for explaining the operation of the first embodiment;

FIG. 10 is a diagram illustrating the structure of a data controller according to the second embodiment;

FIGS. 11A to 11E and 12A to 12G are timing charts for explaining the operation of the second embodiment; and

FIGS. 13 through 18G illustrate the third embodiment of this invention in which

FIG. 13 is a block diagram illustrating the general circuit configuration;

FIG. 14 is a detailed circuit diagram of a data controller;

FIG. 15 is a detailed block diagram of a segment driver;

FIG. 16(a) is a detailed circuit diagram of segment drive voltage generator of a liquid crystal drive voltage generator;

FIG. 16(b) is a diagram for explaining a voltage generating operation; and

FIGS. 17A to 17K and 18A to 18G are timing charts for explaining the operation of the third embodiment.

Preferred embodiments of this invention will now be described referring to the accompanying drawings. In FIG. 2, the thicknesses of the color filters FR, FG and FB are adjusted to set the maximum height difference within 1 .mu.m, for example. For instance, with the thickness of the red filter FR being kept held at the optimum value, the height difference between the red filter FR and green filter FG is set to 0.5 .mu.m and the height difference between the green filter FG and blue filter FB is also set to 0.5 .mu.m, thus setting the maximum height difference between the filters within 1 .mu.m. And the liquid crystal display panel having the individual filters set to have the above thicknesses is driven by the driver as shown in FIG. 4.

FIG. 4 schematically illustrates the general configuration of a liquid crystal panel driver. Referring to the diagram, reference numeral 11 is a data controller which is supplied with R, G and B color signals as well as no-bias (zero-bias) control data RD, GD and BD from a display controller 13. The data controller 11 also receives a data output control signal VDO, sampling signal .phi.s, gate control signals AN (AN1, AN2, . . . ), etc. As will be described in a later section, the data controller 11 selectively outputs the input signals in accordance with the data output control signal VDO. More specifically, the data controller 11 selects the color signals R, G and B during an image display period and selects the no-bias control data RD, GD and BD during a non-display period, and it outputs the selected signals as 3-bit data D1 to D3. In this case, the no-bias control data RD, GD and BD specify effective voltage values in the no-bias interval for each of the R, G and B signals, by the amount of the height difference reduced between the color filters FR, FG and FB. Specifying the effective voltage values provide the optimum value for .DELTA.n.multidot.d. The data D1 to D3 are 8-gradation specifying data, with D1 on the LSB side and D3 on the MSB side, for example.

The data D1-D3 from the data controller 11 are sent to a segment driver 12 which is supplied with a sampling pulse .phi.sm, latch pulse .phi.L, intensity (luminance) modulation pulses P1-P3 and a frame signal .phi.f from the controller 13 as well as liquid crystal drive voltages V1c and V3c from a liquid crystal drive voltage generator 14.

The segment driver 12 (which will be described in detail in a later section) operates in accordance with various timing signals from the display controller 13, and receives the video data D1-D3 from the data controller 11 to prepare, for example, 8-gradation segment drive signals Y1 to Ym for driving segment electrodes (signal electrodes) of a liquid crystal panel 15. This liquid crystal display panel 15 is designed in the manner described earlier so that the thicknesses of the color filters FR, FG and FB are adjusted to provide the maximum height difference within 1 .mu.m.

As will be described in detail later, in accordance with the no-bias timing signal EC and frame signal .phi.f as shown in the timing chart of FIG. 5, the liquid crystal drive voltage generator 14 prepares the drive voltage V1c from the liquid crystal drive voltages V1 and V2 and prepares the drive voltage V3c from the liquid crystal drive voltages V2 and V3, and outputs these voltages to the segment driver 12. The voltage generator 14 sends the liquid crystal drive voltages V0, V2 and V4 to a common driver 16. This driver 16, which operates in accordance with the timing signal from the display controller 13, selects the liquid crystal drive voltages V0, V2 and V4 from the voltage generator 14 to prepare common drive signals X1-Xn and sequentially drive the common electrodes of the liquid crystal panel 15.

A detailed description will be given below of the data controller 11, segment driver 12 and liquid crystal voltage generator 14.

FIG. 5 gives a detailed illustration of the data controller 11. Referring to this diagram, reference numeral 21 is an A/D converter which receives the color signals R, G and B from the display controller 13 through gate circuits 22a to 22c. The ON/OFF operation of the gate circuits 22a-22c is controlled by the gate control signals AN1-AN3 from the display controller 13. The A/D converter 21 performs sequential sampling of an input signal in accordance with the sampling signal .phi.s and converts it into 3-bit data D1', D2' and D3', which are output to the AND circuits 23a-23c. The AND circuits 23a-23c are supplied with the data output control signal VDO from the display controller 13. The no-bias control data RD, GD and BD from the display controller 13 are input to AND circuits 24a to 24c through 3-state buffers 25a to 25c. The ON/OFF operation of the 3-state buffers 25a-25c is controlled by gate control signals AN4-AN6 from the display controller 13. The AND circuits 24a-24c are supplied with the data output control signal VDO through an inverter 26. The output signals of the AND circuits 23a-23c and 24a-24c are output as the data D1-D3 respectively through NOR circuits 27a-27c and inverters 28a-28c, and are sent to the segment driver 12.

FIG. 6 illustrates the structure of one stage of the segment driver 12, in which the data D1-D3 from the data controller 11 are input in a 3-bit register 31. The register 31 latches the input data D1-D3 in synchronization with the sampling pulse .phi.sm and outputs it to a latch circuit 32. The latch circuit 32 latches the data held in the register 31 in accordance with the latch pulse .phi.L outputs it to a pulse width modulation circuit 33. The circuit 33 latches the latched data by means of the latch pulse .phi.L prepares an 8-gradation signal from the intensity modulation pulses P1-P3. The pulse width modulation circuit 33 also inverts and outputs the gradation signal, prepared according to the data D1-D3, in accordance with the frame signal .phi.f. The output signal of the circuit 33 has its level shifted by a level shifter 34 and is output as the segment drive signal Ym through an inverter 35. The inverter 35 is supplied with the liquid crystal drive voltages V1c and V3c from the liquid crystal drive voltage generator 14.

FIG. 7 illustrates in detail the segment drive voltage generating section in the liquid crystal drive voltage generator 14. In the diagram, reference numerals 41a, 41b, 42a and 42b are gate circuits, the first two gate circuits 41a and 41b being supplied with the liquid crystal drive voltages V1 and V2 and the latter two gate circuits 42a and 42b being supplied with the liquid crystal drive voltages V3 and V2. The no-bias timing signal EC from the display controller 13 is input to OR circuits 43 and 44, and the frame signal .phi.f is input directly to the OR circuit 43 and to the OR circuit 44 through an inverter 45. The output signal of the OR circuit 43 is supplied to the gate terminal of the gate circuit 41a through a level shifter 46 and is further supplied therefrom to the gate terminal of the gate circuit 41b through an inverter 47. The output signal of the OR circuit 44 is supplied to the gate terminal of the gate circuit 42a through a level shifter 48 and is further supplied therefrom to the gate terminal of the gate circuit 42b through an inverter 49. The output signals of the gate circuits 41a and 41b serve as the liquid crystal drive voltage V1c, while the output signals of the gate circuits 42a and 42b serve as the liquid crystal drive voltage V3c.

The operation of the above embodiment will now be described. The segment drive voltage generating section in the drive voltage generator 14 shown in FIG. 7 is controlled by the no-bias timing signal EC and frame signal .phi.f shown in the timing charts of FIGS. 8B and 9B. The signal EC (FIGS. 8A and 9A) is kept at a high level during a video signal display period T1 and at a low level during a non-display period T2, such as a vertical blanking period, in each field in which the frame signal .phi.f is at a high level or low level. When both of the timing signal EC and frame signal .phi.f are at a low level, the gate circuit 41b is turned ON and the voltage V2 is taken as the segment drive voltage V1c (FIG. 8H), and when either signal EC or .phi.f becomes a high level, the gate circuit 41a is turned ON and the voltage V1 is taken as V1c (FIG. 8G). With regard to the segment drive voltage V3c output through the gate circuits 42a and 42b, the gate circuit 42b is turned on and the voltage V2 is taken as V3c only when the timing signal EC is at a low level and the frame signal .phi.f is at a high level, and the gate circuit 42a is turned on otherwise and the voltage V3 is taken as V3c.

Accordingly, the data controller 11 (see FIG. 5 for its detailed illustration) selectively outputs the color signals R, G and B or the no-bias control data RD, GD and BD (FIGS. 8D to 8F), by means of the data output control signal VDO (FIG. 8C). This control signal VDO has the same signal waveform as the no-bias timing signal EC and has a high-level duration ta and a low-level duration tb. In consideration of the delay time in the segment driver 12, however, the signal VDO is given at a timing slightly earlier than the signal EC. During the high-level duration ta of the control signal VDO, the gate control signals AN1-AN3 from the display controller 13 are supplied to the gate circuits 22a-22c to open them, and the color signals R, G and B are input to the A/D converter 21. The A/D converter 21 converts the received signals R, G and B into 3-bit video data D1'-D3' in synchronization with the sampling signal .phi.sm and sends the data to the AND circuits 23a-23c. Since the gates of the AND circuits 23a-23c are opened during the high-level duration ta of the control signal VDO, the video data D1'-D3' from the A/D converter 21 are taken as data D1-D3 and sent to the segment driver 12 through the AND circuits 23a-23c, NOR circuits 27a-27c and inverters 28a-28c.

Thereafter, when the control signal VDO becomes a low level, the gates of the AND circuits 23a-23c are closed and the gates of the AND circuits 24a-24c are opened during the low-level duration tb. During the low-level duration tb of the control signal VDO, the gate control signals AN4-AN6 as well as the no-bias control data RD, GD and BD, set to specific values, are supplied to the 3-state buffers 25a-25c from the display controller 13. In accordance with the control data RD, GD and BD, a signal with all "1" (high level) or all "0" (low level) is output as the data D1-D3. In this case, the control data RD, GD and BD may be set as shown in FIGS. 8D to 8F. More specifically, the data RD is preset so that D1-D3 are all "0" over the entire low-level duration tb of the control signal VDO, the data GD is pre-set so that D1-D3 are all "1" for a given period t1 and are all "0" for the remaining period, and the data BD is pre-set so that D1-D3 are all "1" for a period t2 longer than t1 and are all "0" for the remaining period. The no-bias interval of the liquid crystal display panel 15 is determined by the data D1-D3 in the non-bias period.

Consequently, the data D1-D3 from the data controller 11 are read by the segment driver 12 which in turn prepares the segment drive signals Y1-Ym. That is, the segment driver 12 (see FIG. 6 for its detailed illustration) reads the data D1-D3 from the data controller 11 into the register 31 in synchronization with the sampling pulse .phi.sm. The sampling pulse .phi.sm (.phi.s1, .phi.s2, . . . , .phi.sm), which is prepared by the sampling start signal .phi.ST (see FIG. 9D) in association with the individual segment terminals, is output one pulse between the generation of the latch pulses .phi.L (FIG. 9C) after the data D1-D3 are supplied. This sampling pulse .phi.sm permits the data D1-D3 to be sequentially transferred to those regions of the register 31 which are associated with the individual segment terminals. When the data D1-D3 are read into the register 31 at the all stages, the latch pulse .phi.L is supplied to the latch circuit 32 so that the data held in the register 31 is latched in the circuit 32 and is then transferred to the pulse width modulation circuit 33.

This pulse width modulation circuit 33 performs intensity modulation using the intensity modulation pulses P1-P3 in accordance with the latched data and prepares an 8-gradation signal. This gradation signal is inverted in synchronization with the frame signal .phi.f and is output as the segment drive signal Ym through the level shifter 34 and inverter 35. In this case, the segment drive signals Y.sub.R, Y.sub.G and Y.sub.B are prepared for the respective color signals R, G and B and drive the associated segment electrodes of the liquid crystal panel 15. The common electrodes of the liquid crystal panel 15 are driven by the common driver 16. X-Y.sub.R, X-Y.sub.G and X-Y.sub.B in FIGS. 9E to 9G are the waveforms of the synthesized drive voltages between the common electrodes and segment electrodes (R, G and B) of the liquid crystal panel 15 in a case where reference voltage V.sub.2 is set at O V. The no-bias timing signal EC is set at a high level, that is, the segment drive signal based on the video data D1'-D3' is given during the video signal display period and the voltage level is .vertline.V1.vertline. and -.vertline.V3.vertline.. With the common electrodes being selected, therefore, the synthesized drive voltages X-Y.sub.R , X-Y.sub.G and X-Y.sub.B between the common and segment electrodes become .vertline.V0-V3.vertline. and .vertline.V0-V1.vertline. when the frame signal .phi.f is at a high level and become -.vertline.V4-V1.vertline. and -.vertline.V4-V3.vertline. when the frame signal .phi.f is at a low level. These synthesized drive voltages X-Y.sub.R, X-Y.sub.G and X-Y.sub.B drive the liquid crystal panel 15.

During the no-bias period T2 in which the no-bias timing signal EC is at a low level, the segment signal Ym based on the no-bias control data RD, GD and BD is output from the segment driver 12. When the frame signal .phi.f is at a high level, therefore, the synthesized drive voltage X-Y.sub.R between the common and segment electrodes is kept at the .vertline.V1.vertline. (.vertline.V1-V2.vertline.) level over the period T2. The synthesized drive voltage X-Y.sub.G is kept at the .vertline.V1.vertline. (.vertline.V1-V2.vertline.) level for time t1 in the period T2 and is kept at the .vertline.V2-V2.vertline., i.e., O V level for the remaining period. The synthesized drive voltage X-Y.sub.B is kept at the .vertline.V1.vertline. (.vertline.V1-V2.vertline.); level for time t2 in the period T2 and is kept at the .vertline.V2-V2.vertline. level for the remaining period. When the frame signal .phi.f is at a low level, the drive voltages with their levels being inverted from those in the above case are applied between the common and segment electrodes.

In the manner described above, the drive voltages for the R, G and B segment electrodes can be independently set and the birefringence .DELTA.n of the liquid crystal element can be set at the optimum to provide the optimum value for .DELTA.n.multidot.d even if the thicknesses of the color filters differ from the optimum values.

Although a DC voltage is applied during periods t1 and t2 in FIGS. 9F and 9G, an AC voltage may be applied instead.

The second embodiment of this invention will now be described referring to FIGS. 10 to 12G. According to this embodiment, the data controller 11 shown in FIGS. 4 and 5 is constituted as shown in FIG. 10. More specifically, the data controller according to the embodiment shown in FIG. 10 employs three sets of 3-state buffers 51a-51c, 52a-52c and 53a-53c in place of the 3-state buffers 25a-25c of the data controller 11 shown in FIG. 5. The first set of buffers 51a-51c are supplied with no-bias control data RD1, GD1 and BD1 from the display controller 13 shown in FIG. 4. The second set of buffers 52a-52c are supplied with no-bias control data RD2, GD2 and BD2 from the controller 13, and the third et of buffers 53a-53c are supplied with no-bias control data RD3, GD3 and BD3 from the controller 13. The buffers 51a, 52a and 53a are supplied with the gate control signal AN4, the buffers 51b, 52b and 53b with the gate control signal AN5, and the buffers 51c, 52c and 53c with the gate control signal AN6. The output signals of the buffers 51 a-51c are supplied to the AND circuit 24a, the output signals of the buffers 52a-52c to the AND circuit 24c, and the output signals of the buffers 53a-53c to the AND circuit 24c. The other section of the data controller of the second embodiment has the same structure as that of the data controller 11 shown in FIG. 5.

The display controller 13 stops the generation of the sampling start signal .phi.ST inhibit the supply of the sampling pulse .phi.sm to the register 31 of the segment driver 12, during the non-display period T2 in which the no-bias timing signal EC is at a low level (see the timing chart shown in FIG. 12A). In other words, during the no-bias period T2, the no-bias control data RD1-RD3, RG1-RG3 and RB1-RB3 given as the data D1-D3 from the data controller 11 are held intact in the register 31.

With the above arrangement, the no-bias control data RD1-RD3, GD1-GD3 and BD1-BD3, which serve to set the gradation levels in no-bias period, are set as follows:

RD1 to RD3: "0 0 0" (gradation 0),

GD1 to GD3: "0 1 0" (gradation 2), and

BD1 to BD3: "0 0 1" (gradation 4).

During the period in which the data output control signal VDO is at a low level (see the timing chart shown in FIG. 11C), thus set control data RD1-RD3, GD1-GD3 and BD1-BD3 are taken out through the AND circuits 24a-24c and are further sent as the data D1-D3 to the segment driver 12 through the NOR circuits 27a-27c and inverters 28a-28c. The segment driver 12 transfers the control data RD1-RD3, GD1-GD3 and BD1-BD3 (given as D1-D3) into the register 31 in synchronization with the sampling pulse .phi.sm. Then, the input of the sampling pulse .phi.sm to the register 31 is inhibited, so that the data transferred to this register is held as it is during the no-bias period T2. The segment driver 12 reads out the data held in the register 31 in synchronization with the latch pulse .phi.L (FIG. 12C), repeatedly prepares a gradation signal according to the data and outputs the segment drive signal Ym.

The liquid crystal panel 15 is driven by the segment drive signal Ym from the segment driver 12 and the common drive signal Xn from the common driver 16. X-Y.sub.R, X-Y.sub.G and X-Y.sub.B shown in FIGS. 12E to 12G are the waveforms of the synthesized drive voltages between the common and segment electrodes of the liquid crystal panel 15 at that time in a case where reference voltage V2 is set at O V. The synthesized drive voltages will have the gradation waveforms set by the aforementioned no-bias control data RD1-RD3, GD1-GD3 and BD1-BD3 during the no-bias period T2 in which the no-bias timing signal EC is at a low level. In other words, since "0 0 0" is specified by the control data RD1-RD3 in the no-bias period T2, the drive voltages X-Y.sub.R is selected to be the no-bias voltage .vertline.V2.vertline., i.e., 0 V over the entire period T2. Since "0 1 0" is specified by the control data GD1-GD3 in the no-bias period T2, the drive voltages X-Y.sub.G is selected to be .vertline.V1.vertline. or .vertline.V3.vertline. corresponding to the gradation 2 every time the latch pulse .phi.L is applied, and is selected to be no-bias voltage .vertline.V2.vertline. otherwise. Since "0 0 1" is specified by the control data BD1-BD3 in the no-bias period T2, the drive voltages X-Y.sub.B is selected to be .vertline.V1.vertline. or .vertline.V3.vertline. corresponding to the gradation 4 every time the latch pulse .phi.L is applied, and is selected to be no-bias voltage .vertline.V2.vertline. otherwise. Although a DC voltage is applied as a waveform corresponding to the gradation 2 or 4, an AC voltage may be applied instead.

In the above manner, with regard to the individual drive voltages X-Y.sub.R, X-Y.sub.G and X-Y.sub.B, the time durations of the selected voltages are set different from one another during the no-bias period T2, thereby providing different effective voltage values. The effective voltage values can be arbitrarily set by the control data RD1-RD3, GD1-GD3 and BD1-BD3, and the double refraction factor .DELTA.n can be set to such a value as to provide the optimum value for .DELTA.n.multidot.d even if the thicknesses of the individual color filters differ from the optimum values.

Although the effective voltage value of an image signal is changed for each color by varying the voltage-applying time during the non-display period according to the first and second embodiments, the effective voltage value may be changed by varying the value of the voltage applied.

Although, according to these embodiments, the no-bias driving is executed with effective voltage values that are mutually different for the individual colors, red, green and blue, the no-bias driving needs only to be effected with the effective voltage values at least two of which differ from each other.

FIG. 13 schematically illustrates the general configuration of a liquid crystal panel driver. Referring to the diagram, reference numeral 111 is a data controller which is supplied with R, G and B color signals as well as bias control data RD, GD and BD from a display controller 113. The data controller 111 also receives a data output control signal VDO, sampling signal .phi.s, gate control signals AN (AN1, AN2, . . . ), clock pulse .phi.ck, etc. As will be described in a later section, the data controller 111 selectively outputs the input signals in accordance with the data output control signal VDO. More specifically, the data controller 111 selects the color signals R, G and B during an image display period and selects the bias control data RD, GD and BD during a non-display period, and it outputs the selected signals as 3-bit data D1 to D3. In this case, the bias control data RD, GD and BD specify effective voltage values in the non-display interval for each of the R, G and B signals, by the amount of the height difference reduced between the color filters FR, FG and FB. Specifying the effective voltage values provide the optimum value for .DELTA.n.multidot.d. The data D1 to D3 are 8-gradation specifying data, with D1 on the LSB side and D3 on the MSB side, for example.

The data D1-D3 from the data controller 111 are sent to a segment driver 112 which is supplied with a sampling pulse .phi.sm, latch pulse .phi.L, intensity modulation pulses P1-P3 and a frame signal .phi.f from the controller 113 as well as liquid crystal drive voltages V1 and V3 from a liquid crystal drive voltage generator 114.

The segment driver 112 operates in accordance with various timing signals from the display controller 113, and receives the video data D1-D3 from the data controller 111 to prepare, for example, 8-gradation segment drive signals Y1 to Ym for driving segment electrodes (signal electrodes) of a liquid crystal panel 115. This liquid crystal display panel 115 is designed in the manner described earlier so that the thicknesses of the color filters FR, FG and FB are adjusted to provide the maximum height difference within 1 .mu.m.

The liquid crystal drive voltage generator 114 generates crystal drive voltages V1 and V3 and supplies them to the segment driver 112. The voltages V1 and V3 are held at constant bias voltages vb and -vb, respectively. As will be describe in a later section, the liquid crystal drive voltage generator 114 prepares the bias voltages vb and -vb in accordance with the non-display period signal EC and frame signal .phi.f (see the timing chart of FIGS. 17A and 17B) and prepares the liquid crystal drive voltage V2 from the ground potential GND. The voltage generator 114 further sends liquid crystal drive voltages V0 and V4 of a constant level to a common driver 116. This driver 116, which operates in accordance with the timing signal from the display controller 113, selects the liquid crystal drive voltages V0, V2 and V4 from the voltage generator 114 to prepare common drive signals X1-Xn and sequentially drive the common electrodes of the liquid crystal panel 115.

A detailed description will be given below of the data controller 111, segment driver 112 and liquid crystal voltage generator 114.

FIG. 14 gives a detailed illustration of the data controller 111. Referring to this diagram, reference numeral 121 is an A/D converter which receives the color signals R, G and B from the display controller 113 through gate circuits 122a to 122c. The ON/OFF operation of the AND circuits 122a-122c is controlled by the gate control signals AN1-AN3 from the display controller 113. The A/D converter 121 performs sequential sampling of an input signal in accordance with the sampling signal .phi.s and converts it into 3-bit data D1', D2' and D3', which are output to the AND circuits 123a-123c. The AND circuits 123a-123c are supplied with the data output control signal VDO from the display controller 113. The bias control data RD, GD and BD from the display controller 113 are input to AND circuits 124a to 124c through 3-state buffers 125a to 125c. The ON/OFF operation of the 3-state buffers 125a-125c is controlled by gate control signals AN4-AN6 from the display controller 113. The AND circuits 124a-124c are supplied with the data output control signal VDO through an inverter 126. The output signals of the AND circuits 123a-123c and 124a-124c are output as the data D1-D3 respectively through NOR circuits 127a-127c and inverters 128a-128c, and are sent to the segment driver 112.

FIG. 15 illustrates the structure of one stage of the segment driver 112, in which the data D1-D3 from the data controller 111 are input in a 3-bit register 131. The register 131 latches the input data D1-D3 in synchronization with the sampling pulse .phi.sm and outputs it to a latch circuit 132. The latch circuit 132 latches the data held in the register 131 in accordance with the latch pulse .phi.L and outputs it to a pulse width modulation circuit 133. The circuit 133 latches the latched data by means of the latch pulse .phi.L and prepares an 8-gradation signal from the intensity modulation pulses P1-P3. The pulse width modulation circuit 133 also inverts and outputs the gradation signal, prepared according to the data D1-D3, in accordance with the frame signal .phi.f. The output signal of the circuit 133 has its level shifted by a level shifter 134 and is output as the segment drive signal Ym through an inverter 135. The inverter 135 is supplied with the liquid crystal drive voltages V1 and V3 from the liquid crystal drive voltage generator 114.

FIG. 16(a) illustrates in detail the section in the liquid crystal drive voltage generator 114, which generates the common drive voltage V2. In FIG. 6(a), reference numerals 141a, 141b, and 141c are gate circuits, which are respectively supplied with the bias voltages vb, ground potential GND and bias voltage -vb. The non-display period signal EC from the display controller 113 is input to the gate terminal of the gate circuit 141b and is input through an inverter 142 to AND circuits 143 and 144. The frame signal .phi.f is input to the AND circuit 143 and is input through an inverter 145 to an AND circuit 144. The output signal of the AND circuit 143 is input to the gate terminal of the gate circuit 141c, and the output signal of the AND circuit 144 is input to the gate terminal of the gate circuit 141a. The output signals of the gate circuits 141a, 141b and 141c are extracted as the liquid crystal drive voltage V2.

The operation of the above embodiment will now be described. The common drive voltage generating section in the drive voltage generator 114 shown in FIG. 16(a) is controlled by the non-display period signal EC and frame signal .phi.f shown in the timing chart of FIGS. 17A and 17B, and the liquid crystal drive voltage V2 from the gate circuits 141a to 141c varies as shown in FIG. 16(b). The former signal EC is kept at a high level during the video signal display period T1 and at a low level during the non-display period T2, such as a vertical blanking period, in the individual odd- and even-numbered fields in which the frame signal .phi.f is at a high level or low level. When the signal EC is at an "L" (low) level, it is inverted to be an "H" (high) level before being input to the AND circuits 143 and 144, the one of the outputs of the AND circuits 143 and 144 becomes the "H" level in accordance with the level of the frame signal .phi.f. This controls the gate circuits 141a and 141c to determine the level of the liquid crystal drive voltage V2. In other words, if the frame signal .phi.f is at the "L" level, the output of the AND circuit 144 has the "H" level and the gate of the gate circuit 141a is opened. As a result, the bias voltage vb is output as the liquid crystal drive voltage V2. If the frame signal .phi.f is at the "H" level, however, the output of the AND circuit 143 will have the "H" level and the gate of the gate circuit 141c is opened. As a result, the bias voltage -vb is output as the liquid crystal drive voltage V2. If the non-display period signal EC is at the "H" level, the gate of the gate circuit 141b is opened and the ground potential GND is output as the liquid crystal drive voltage V2. Since the output of the inverter 142 becomes the "L" level at this time, the outputs of the AND circuits 143 and 144 are kept at the "L" level to close the gates of the gate circuits 141a and 141c, thereby inhibiting the output of the bias voltages vb and -vb.

In other words, the liquid crystal drive voltage V2 is kept at the ground potential GND irrespective of the frame signal .phi.f during the display period T1 in which the signal EC is at the high level as shown in FIG. 17A, but during the non-display period T2 during which the signal EC is at the low level, the voltage V2 is kept at "-vb" in the odd-numbered frames in which the frame signal .phi.f is at the high level and is kept at "vb" in the even-numbered frames in which the frame signal .phi.f is at the low level.

The liquid crystal drive voltage V1 and V3 (FIGS. 17G and 17H) which is applied to the segment driver 112 are kept at constant potentials of "vb" and "-vb," respectively. Therefore, the relative voltages between the voltage V2 (FIG. 17I) applied to the common electrode driver 116 and the voltages V1 and V3 applied to the segment driver 112, "V2-V1" and "V2-V3," vary in the video signal display period T1 and non-display period T2, as shown in FIGS. 17J and 17K. More specifically, in the display period T1, "V2-V1" is "GND-vb=-vb" and "V2-V3" is "GND-(-vb)=vb." In the odd-numbered frames wherein the frame signal .phi.f is at the high level, however, "V2-V1" is "-vb-vb=-2vb" and "V2-V3" is "-vb-(-vb)=GND." In the even-numbered frames where the frame signal .phi.f is at the low level, "V2-V1" is "vb-vb=GND" and "V2-V3" is "vb-(-vb)=2vb."

In the above manner, "V2-V1" changes around "-vb" between "GND" and "-2vb", while "V2-V3" changes around "vb" between "GND" and "2vb."

Accordingly, the data controller 111 (see FIG. 14 for its detailed illustration) selectively outputs the color signals R, G and B or the bias control data RD, GD and BD, by means of the data output control signal VDO. This control signal VDO has the same signal waveform as the non-display period signal EC and has a high-level duration ta and a low-level duration tb. In consideration of the delay time in the segment driver 112, however, the signal VDO is given at a timing slightly earlier than the signal EC. During the high-level duration ta of the control signal VDO, the gate control signals AN1-AN3 from the display controller 113 are supplied to the gate circuits 122a-122c to open them, and the color signals R, G and B are input to the A/D converter 121. The A/D converter 121 converts the received signals R, G and B into 3-bit video data D1'-D3' in synchronization with the sampling signal .phi.s and sends the data to the AND circuits 123a-123c. Since the gates of the AND circuits 123a-123c are opened during the high-level duration ta of the control signal VDO, the video data D1'-D3' from the A/D converter 121 are taken as data D1-D3 and sent to the segment driver 112 through the AND circuits 123a-123c, NOR circuits 127a-127c and inverters 128a-128c.

Thereafter, when the control signal VDO becomes the low level, the gates of the AND circuits 123a-123c are closed and the gates of the AND circuits 124a-124c are opened during the low-level duration tb. During the low-level duration tb of the control signal VDO, the

gate control signals AN4-AN6 as well as the bias control data RD, GD and BD, set to specific values, are supplied to the 3-state buffers 125a-125c from the display controller 113. In accordance with the control data RD, GD and BD, a signal with all "1" (high level) or all "0" (low level) is output as the data D1-D3. In this case, the control data RD, GD and BD may be set as shown in FIG. 17. More specifically, the data RD is pre-set so that D1-D3 are all "0" over the entire low-level duration tb of the control signal VDO, the data GD is preset so that D1-D3 are all "1" for a given period t1 and are all "0" for the remaining period, and the data BD is pre-set so that D1-D3 are all "1" for a period t2 longer than t1 and are all "0" for the remaining period. The bias interval of the liquid crystal display panel 115 is determined by the data D1-D3 in the bias period.

Consequently, the data D1-D3 from the data controller 111 are read by the segment driver 112 which in turn prepares the segment drive signals Y1-Ym. That is, the segment driver 12 (see FIG. 15 for its detailed illustration) transfers the data D1-D3 from the data controller 111 into the register 131 in synchronization with the sampling pulse .phi.sm. The sampling pulse .phi.sm (.phi.s1, .phi.s2, . . . , .phi.sm), which is prepared by the sampling start signal .phi.ST (see FIG. 18D) in association with the individual segment terminals, is output one pulse between the generation of the latch pulses .phi.L after the data D1-D3 are transferred to the segment driver 112. This sampling pulse .phi.sm permits the data D1-D3 to be sequentially transferred to those regions of the register 131 which are associated with the individual segment terminals. When the data D1-D3 are transferred to the register 131 at the preceding stage, the latch pulse .phi.L is supplied to the latch circuit 132 so that the data held in the register 131 is latched in the circuit 132 and is then transferred to the pulse width modulation circuit 133.

This pulse width modulation circuit 133 performs intensity modulation using the intensity modulation pulses P1-P3 in accordance with the latched data and prepares an 8-gradation signal. This gradation signal is inverted in synchronization with the frame signal .phi.f and is output as the segment drive signal Ym through the level shifter 134 and inverter 135. In this case, the segment drive signals Y.sub.R, Y.sub.G and Y.sub.B are prepared for the respective color signals R, G and B and drive the associated segment electrodes of the liquid crystal panel 115. The common electrodes of the liquid crystal panel 115 are driven by the common driver 116. X-Y.sub.R, X-Y.sub.G and X-Y.sub.B in FIGS. 18E to 18G are the waveforms of the synthesized drive voltages between the common electrodes and segment electrodes (R, G and B) of the liquid crystal panel 115. The non-display period signal EC is set at a high level, that is, the segment drive signal based on the video data D1'-D3' is given during the video signal display period and the voltage level is V1 (vb) and V3 (-vb). With the common electrodes being selected, therefore, the synthesized drive voltages X-Y.sub.R, X-Y.sub.G and X-Y.sub.B between the common and segment electrodes become "Vop" and "Vop-2vp" when the frame signal .phi.f is at a high level and become "-Vop" and "-Vop+2vb" when the frame signal .phi.f is at a low level. These synthesized drive voltages X-Y.sub.R, X-Y.sub.G and X-Y.sub.B drive the liquid crystal panel 115.

During the non-display period T2 in which the non-display period signal EC is at a low level, the segment signal Ym based on the bias control data RD, GD and BD is output from the segment driver 112. When the frame signal .phi.f is at a high level, therefore, the synthesized drive voltage X-Y.sub.R between the common and segment electrodes is kept at the GND level over the period T2. The synthesized drive voltage X-Y.sub.G is kept at the 2vb level for time t1 in the period T2 and is kept at the GND level for the remaining period. The synthesized drive voltage X-Y.sub.B is kept at the 2vb level for time t2 in the period T2 and is kept at the GND level for the remaining period. When the frame signal .phi.f is at a low level, the drive voltages with their levels being inverted from those in the above case are applied between the common and segment electrodes.

In the manner described above, the bias voltage during the non-display period can be set sufficiently large by controlling the drive voltage for the common electrodes, the drive voltages for the R, G and B segment electrodes can be independently set and the birefringence .DELTA.n of the liquid crystal element can be set at the optimum to provide the optimum value for .DELTA.n.multidot.d even if the thicknesses of the color filters differ from the optimum values.

Although a DC voltage is applied during periods t1 and t2 in FIGS. 18F and 18G, an AC voltage may be applied instead.

Although, according to the foregoing embodiments, a predetermined bias voltage is applied in the blanking period as the non-display period of an image signal, the predetermined bias voltage may be applied in a non-display period of an image signal which is provided in each selected period of the common electrodes.

Further, although bias driving is effected with effective voltage values which are mutually different for the respective colors of red, green and blue in the above embodiments, such bias driving may be effected with the effective voltage values at least two of which differ from each other.