US 5,115,358 AGrant
Configurable Disk Memory Servowriter
Issue Date:1992-05-19
•5 Claims
•22 Drawing Sheets
Abstract
A servo pattern writer which may be programmed to write a selected servo pattern for a magnetic disk drive memory is provided. The servo pattern writer includes logic circuitry of which the logic functions and interconnections may be configured as appropriate in response to the configuration program to generate the desired servo pattern.
Metadata
Assignee
- Data Exchange Corporation
Inventor
- Douglas F. Widney
Application Information
Application Number:US 6185118
Filing Date:1990-11-20
Priority Date:1988-11-01
Art Unit:233
Classifications
IPC:
G11B 3100
Field of Search:
36036536468;75;77.02;77.05;77.08189.08716
Patent Drawings (22 sheets)
Description
Background of the Invention
1. Field of the Invention present invention relates to servo-writers for magnetic disk drive memories.
2. Description of Related Art
Magnetic disk drive memories are well-known devices for storing large quantities of digital data. An example of a typical disk drive is indicated generally at 10 in FIG. 1. As the name suggests, a disk drive has one or more disks 12 coated with a magnetizable medium such as ferrous oxide on which the data may be magnetically stored. The disks, often referred to as platters, may be vertically stacked and caused to rotate about a central spindle 14. Data may be stored or "written" onto each surface of the media platters by read-write data heads 16 which are placed in close physical proximity to the surface of a platter. By passing a current through a read-write head, a small portion of the surface of the associated platter may be magnetized to form a magnetic domain and store a digital 1 or 0 onto the platter.
Typically, the read-write heads 16 are rigidly coupled to each other in a vertical stack, and may be moved together as an assembly 20 in a radial motion by a positioning mechanism 22 either towards or away from the spindle 14 of the platter stack. At each position of a head of the head stack, a unique circular track is defined in the surface of the associated platter as the platter rotates below the head. To read data written on the circular data tracks, currents induced in the read-write data heads by the magnetic domains on the media platter are sensed and amplified for transmission to other parts the computer system.
As data storage densities have increased, the spacing between data tracks has decreased. Many disk drives now have in excess of 2,000 tracks per inch of radial head movement. At such densities, special positioning mechanisms referred to as "servos", have been used to ensure proper positioning of the data heads over the data tracks of the disk drive. The servo mechanism of FIG. 1 includes a servo head 24 which reads position information from a special pattern of servo tracks written onto a surface 26 of one of the platters.
One type of servo system is referred to as the "dedicated servo" and employs a servo pattern written to the entirety of the platter surface 26. The position information read by the servo head is the sole source of positioning information for the head assembly.
Where high densities of data are required, the servo pattern is typically written by a special device referred to as a "servo pattern writer" or simply a "servowriter". To position the servo head for writing the servo pattern, a servowriter typically includes a precision lead screw mechanism which is usually controlled by an extremely accurate position control system such as a laser interferometer or an extremely high resolution optical encoder. The servo pattern to be written is typically generated by high speed, precisely clocked logic circuitry. Each disk drive manufacturer often has its own unique servo pattern which may even vary from model to model of the same manufacturer.
FIG. 2 illustrates a servo pattern for a model 6650 disk drive, manufactured by Priam Corporation. The servo pattern when read, allows the servo system to generate an error position signal relative to the current track being read. Often, the patterns of positioning pulses of the servo pattern are alternated from track to track to define "odd" and "even" servo tracks. The equilibrium position of the servo head is usually halfway between adjacent odd and even servo tracks. Thus, the signal read back from the servo head will be a composite of these adjacent even and odd tracks.
The servo system compares the amplitudes of the pulses of the read back signal at odd and even track positioning pulse time windows to generate a position error signal. When the servo head is centered precisely between the odd and even tracks, the odd and even position read back signals will be equal in amplitude, generating no error signal. However, if the servo head is off center between the even and odd tracks, an error signal is generated which is used to reposition the servo head appropriately. Since the data heads are coupled to the servo head, the data heads will follow the movement of the servo head. In this manner, the circular tracks of the servo pattern defines the data tracks on the other surfaces of the platter stack.
The servo pattern also can provide a timing reference. Typically, special timing reference pulses are included in the pattern in a manner in which the pulses can be detected, allowing a phase-locked loop to lock to the timing reference pulses during operation.
Another function of the servo pattern is to provide special position information to the servo system. For example, data may be encoded into the pattern to provide index and sector mark signals, indicating the angular position of the platter stack. Similarly, servo tracks outside of the range of data tracks may be encoded to form guard band zones.
Two primary types of servowriters are custom servowriters and configurable or universal servowriters. A custom servowriter is generally capable of writing a servo pattern for only one particular model of disk drives. Consequently, these servowriters typically generate only one type of servo pattern at a fixed frequency and are generally capable of positioning the heads at a single fixed track density.
Configurable or universal servowriters, on the other hand, are designed to be able to write a variety of servo patterns at different frequencies and track densities. The configurability or programmablity of a servowriter is highly desirable for several reasons. For example, the development of a particular disk drive must by accompanied by or perhaps even preceded by the availability of a servowriter which is capable of writing the servo pattern for that disk drive. Once a servowriter has been designed and constructed to write the selected servo pattern for a particular disk drive, a dedicated servowriter inhibits any modifications to the servo pattern. Furthermore, servowriters are relatively expensive devices, the cost of which can be ammortized more effectively if the servowriter can be adapted to other, or future disk drive designs. Still further, a servowriter which may be used for many different disk drive types is highly desirable for use in disk drive service and repair.
However, previous configurable servowriters have tended to be much more expensive than custom servowriters. For example, U.S. Pat. No. 4,584,619 to Nay, et al. describes a programmable servo pattern generator for a configurable servowriter which employs a pattern programming hierarchy. Different levels of pattern repetition are included in the hierarchy such as "cell", "frame", "sector", and "track type". The contents, length and repetition count of each level are programmable to an extent. A phase-locked loop of very high frequency (>80 megahertz) enables the user to write the pattern transitions at any arbitrary interval subject to a small quantization error. The clock frequency is programmable. A wide selection of sensor, driver and power options, with elaborate programmable controls, may also be provided as an interface to the disk drive mechanism. One problem with this approach is that in addition to being quite expensive, the resultant servowriter is quite complex and bulky.
Summary of the Invention
It is an object of the present invention to provide an improved servowriter, obviating for practical purposes, the above-mentioned limitations, particularly in a manner requiring a relatively uncomplicated electronic arrangement.
These and other objects and advantages are achieved in a configurable servo pattern writer which includes, in accordance with a preferred embodiment of the present invention, a plurality of logic gates coupled to the output of a clock, and programmable interconnection circuitry for interconnecting the logic gates in response to a logic gate interconnection program so that the output of the logic gates is a selected servo pattern. As will be explained more fully below in connection with the detailed description of the present embodiment, the servo pattern to be written may be readily changed by supplying an appropriate logic gate interconnection program to the plurality of logic gates.
In another aspect of the present invention, the logic gate interconnection program may readily accommodate the particular hardware control requirements of the particular disk drive. Similarly, a variety of clock closure and phase-locked loop requirements may be readily met.
In the illustrated embodiment, the plurality of logic gates are incorporated in a single integrated circuit which includes a gate array. The logic design for the logic gates of the array may be programmed by the contents of an onboard static random access memory. Consequently, a servo pattern writer, in accordance with the present invention, has significant flexiblity and capability and a significant reduction in complexity and cost.
Brief Description of the Drawings
FIG. 1 is a schematic diagram of a typical disk drive;
FIG. 2 illustrates a representative servo pattern and corresponding read back signals;
FIG. 3 is a schematic diagram of a servo pattern writer in accordance with a preferred embodiment of the present invention;
FIG. 4A and 4B are a schematic diagram of a controller circuit for the servowriter of the FIG. 3;
FIG. 5 is a schematic diagram of a gate array circuit for the controller of FIG. 4;
FIG. 6 depicts the command word format for the gate array or FIG. 5;
FIG. 7 is a schematic diagram illustrating the servo data pattern generator logic of the gate array of FIG. 5;
FIGS. 8A and 8B are timing diagrams for various signals produced by the servo data pattern generator logic of FIG. 7;
FIG. 9 is a schematic diagram of the servo pattern verifier logic of the gate array of FIG. 5;
FIG. 10 illustrates timing diagrams for signals produced by the servo pattern verifier logic of FIG. 9;
FIG. 11 is a schematic diagram of the mechanical status and control logic of the gate array of FIG. 5;
FIG. 12 is a schematic diagram of the structure of the gate array of FIG. 5;
FIG. 13 is a schematic diagram of an input/output block of the gate array of FIG. 12;
FIG. 14 is a schematic diagram of a configurable logic block of the gate array of FIG. 12;
FIG. 15A-15C and schematic diagrams of various configurations of the combinational logic of the configurable logic block of FIG. 14;
FIG. 16 is a schematic diagram illustrating the general purpose interconnect of the gate array of FIG. 12;
FIG. 17 is a schematic diagram illustrating an interrconnection switching matrix of the interconnect of FIG. 16;
FIG. 18 is a schematic diagram illustrating the long line interconnect of the gate array of FIG. 12;
FIG. 19 is a schematic diagram illustrating the direct interconnect for the gate array structure of FIG. 12; and
FIG. 20 is a flow chart illustrating the operation of the servo pattern writer of FIG. 3.
Detailed Description of the Drawings
A configurable servo pattern writer in accordance with a preferred embodiment of the present invention is indicated generally at 200. The servo pattern writer (hereinafter "servowriter") 200 includes a chassis base 202 on which a disk drive 204 may be securely mounted by appropriate removable clamps (not shown). The clamps and chassis base 202 are preferably readily adaptable to receive a variety of different disk drives. Also mounted on the chassis base 202 is a carriage arm 206 which radially moves a servo head 208 over the servo surface 210 of the disk drive 204. A clock head 212 is mounted at a fixed radius over the servo surface 210. An actuator (not shown) may be provided to lower the head 212 over the media surface once the disk drive 204 is secured on the chassis base 202 to initiate the servowriting process, and to raise the clock head once the process is complete.
The servo pattern writing process is controlled by a controller station 214 which, in the illustrated enbodiment, includes a microcomputer 216 which may be, for example, an IBM compatible personal computer. The microcomputer 216 has an associated monitor 218, keyboard 220, and floppy disk drive 222. The servo pattern to be written onto the disk drive 204 is generated by a servowriter controller 224 which also controls the spindle motor of the disk drive 204.
In one aspect of the present invention, the servowriter controller 224 comprises gate array logic which may be programmed by the microcomputer 216 to be interconnected in a particular configuration to generate the desired servo pattern. In the illustrated embodiment, the programmable gate array logic and associated peripheral circuits may be mounted on a single printed circuit board which may be received by an expansion slot in the microcomputer 216. As a consequence, the controller station 214 need be no larger than a standard personal computer.
The servowriter controller 224 is coupled to the servowriter chassis base 202 and disk drive 204 by a driver and sensor electronics interface 226 which includes drivers and sensors for the clock head actuator and sensors for the spindle and carriage arm 206. In addition, the spindle motor of the disk drive 204 is driven through a driver amplifier 228 coupled to the interface 226.
In the illustrated embodiment, the servo head 208 attached to the carriage arm 206 is positioned by an actuator 230 which includes a precision lead screw having a pitch of 40 turns per inch. The lead screw is driven by a D.C. permanent magnet motor which is controlled by a type DMC-400 motor control system manufactured by Galil Enterprises. The DMC-400 system includes a carriage motor controller board 234 which, like the servo controller board 224, readily plugs into an expansion slot in the microcomputer 216. The output of the controller 234 drives the carriage motor of the actuator 230 through a carriage motor amplifier 236.
The DMC-400 controller 234 includes a high-speed microprocessor to simulate the action of linear servo system components. Hence, the gain, band width, movement profile and other servo parameters are programmable and may be optimized for various mechanism attachments. The method of programming the DMC-400 is well-known to those skilled in the art and is described in the User's Manual supplied by the manufacturer. An example of a suitable program for the DMC-400 is set forth in Appendix A.
In the illustrated embodiment, a 4,000 count per turn optical encoder supplies position feedback signals to the carriage motor controller 234. As a consequence, the position of the servo head 208 may be controlled to a resolution of 6 micro-inches. Other modules, such as a laser interferometer, may be substituted as appropriate for the optical encoder, simply by reprogramming the carriage controller 234.
The servowriter chassis base 202 includes the power supplies 238 for the motors and electronic circuitry mounted on the chassis base 202. A front panel 240 has power switches for the power supplies 238 and "ready" status indicators.
The servowriter controller board 224 is shown in greater detail in FIG. 4. The central control element of the servowriter controller board 224 is a RAM-based, programmable gate array 250 which has a plurality of internal logic elements. The gate array 250 of the illustrated embodiment is implemented with a type XC 2018 Logic Cell.TM. array integrated circuit, manufactured by Xylinx, Inc. The type and interconnection of the logic elements of the gate array 250 may be configured by a program stored in an onboard read-write memory. This program which defines the logic design appropriate to the particular disk drive being servo written is first created and stored as a disk file in the microcomputer floppy disk drive 222 (FIG. 3). The disk file containing the logic gate interconnection program is transferred ("down loaded") to the gate array 250 prior to initiation of the servo writing operation. Once loaded, the gate array 250 becomes a servowriter controller integrated circuit specialized for the particular disk drive servo type to be written. The gate array 250 will then accept a series of operation commands written to it by the microcomputer 216 to perform the servo writing operation, and can also return status information when read.
To assist in loading the logic design program, the controller board 224 further includes a system supervisor 252 (type 16RS4 PAL integrated circuit, manufactured by Monolithic Memories, Inc.) which accepts commands for program loading, read back, reset and fault monitoring and also returns status information when read. The system supervisor 252 is coupled by a data buffer 254 to the microcomputer data bus 256. The gate array 250, system supervisor 252 and other integrated circuit devices of the servowriter controller board 224 may be accessed by the microcomputer 216 (FIG. 3) at input-output port addresses supplied by the microcomputer 216. An address decoder 258 (which includes a type 20L10 PAL integrated circuit, a buffer and plurality of NOR gates) decodes the addresses provided at the microcomputer address bus 260 and selects devices for read or write operations. The programming for the PAL devices of FIG. 4 is provided in Appendix B.
Included within the devices addressable by the microcomputer 216, is a 4-channel digital to analog converter circuit 262 (type AD7226 integrated circuit, manufactured by Analog Devices, Inc.). The digital to analog converters 262 allow the microcomputer 216 to configure certain analog voltage levels within the controller board 224 for operations described below. In addition, two 3-channel 16-bit counter-timer circuits 264 and 266 (type 82C54 integrated circuits manufactured by Intel Corporation) are written to by the microcomputer 216 to set various operation mode and count moduli. When read, the counter-timer circuits 264 and 266 also return count and status information to the microcomputer. The counter-timer circuits 264 and 266 are also used by the gate array 250 for various purposes described below.
To write servo pattern data onto the disk drive or read servo pattern data from the disk drive, the servowriter controller board 224 has a read-write amplifier 270 which has an input coupled to the gate array 250 and an output coupled to the servo read-write head 208 of the servowriter chassis base 202. Similarly, an amplifier 272 couples the gate array 250 to the clock read-write head 212. The amplifiers 270 and 272 are discussed in greater detail in copending U.S. patent application Ser. No. 07/265,788 filed Nov. 1, 1988, entitled "Disk Drive Clock Writer", assigned to the assignee of the present application and incorporated herein by reference. A write current generator 274 provides controlled current to whichever head is selected by the gate array 250 for a write operation.
The gate array 250 is also coupled to external components 280 for a phase-locked loop which is also described in greater detail in co-pending U.S. application entitled "Disk Drive Clock Writer". The gate array 250 can latch sensor information from the servowriter chassis base 202 (FIG. 3) at a sensor port 282 which includes 2 74LS244 latch integrated circuit chips. A fixed delay line 284, a delay line latch 286, and a programmable delay line 288 are used to verify the patterns written as described in greater detail in connection with FIG. 9 hereinbelow.
FIG. 5 illustrates the major functional logic sections of the gate array 250 which has been configured to write the required clock and servo patterns for a type 6650 disk drive, manufactured by Priam Corporation. The gate array 250 includes a processor status and command port interface 300 which latches commands from the microcomputer 216 and returns status information over the microcomputer bus. An operation decoder circuit 302 decodes the commands from the microcomputer and activates control lines to the other functional sections of the gate array 250.
The format of the command words from the microcomputer is depicted in FIG. 6. In the illustrated embodiment, there are four possible classes of operations as defined by bits 5 and 6 of the command byte. The two operation classes of primary interest here are mechanical operations (e.g., loading or unloading the heads) and servo track operations. The remaining two operation classes (i.e., clock operations and index operations) are described in the copending application entitled "Disk Drive Clock Writer".
In response to a gate array command to read or write a servo track, an operation sequencer 304 of the gate array 250 controls the cycle of the read or write operation. A frequency and time base generator 306 receives an 18 megahertz clock signal as a reference from a crystal oscillator 308 and also receives a variable frequency clock signal from a voltage controlled oscillator external to the gate array 250. The frequency and time base generator uses these signals to generate a variety of lower frequency clock signals for use by other sections of the gate array. The generator 306 further includes a phase-locked loop phase detector.
The clock signal to be written onto the servo surface of the disk drive 204 is generated by a clock signal generator and verifier circuit 310. The operation sequencer 304, frequency and time base generator and phase detector 306 and clock signal generator and verifier 310 are discussed in greater detail in the co-pending application entitled "Disk Drive Clock Writer". A mechanical status and control block 312 controls the motors and actuators of the servowriter chassis base 202 in response to gate array commands from the microcomputer. The mechanical status and control block 312 is described in greater detail in connection with FIG. 11 hereinbelow.
The gate array 250 also includes a servo pattern generator 314 which generates the servo pattern to be written to the disk drive. A servo pattern verifier 316 may be used to verify each servo track after it is written and thereby check for errors.
The logic for the servo data pattern generator 250 is shown in greater detail in FIG. 7. As previously mentioned, the logic circuitry of the gate array 250 has been programmed in the illustrated embodiment to generate the servo pattern required by the Priam Model 6650 disk drive, which pattern is illustrated in FIG. 2. As shown therein, the servo pattern for this disk drive comprises a series of cells. At the boundary of each cell, a negative transition of the signal provides a timing reference. A positive transition occurs either one-third or two-thirds of a cell later. Thus, in servo track n, for example, a positive transition 350 occurs two-thirds of a cell after the timing reference at the boundary whereas, in servo track n+1, a positive transition 352 occurs one-third of a cell after the negative transition timing reference at the boundary. These two different types of cell, the "late" cell of track n and the "early" cell of track n+1, provide odd and even position information and are used in combinations as illustrated to provide four types of servo tracks. In the Priam Model 6650 disk drive servo pattern, the four track types are written on the drive in a modulo 4 repetition order.
The servo data pattern generator of FIG. 7 has been configured to generate the modulo 4 servo data pattern illustrated in FIG. 2. A 6 megahertz clock signal from the frequency and time base generator 306 (FIG. 5) is divided by 2 by a frequency divider 360 to generate a 3 megahertz clock signal. The divider circuit 360 also divides the 6 megahertz clock signal by 4 to yield a 1.5 megahertz signal as indicated at 364. One cycle of the 1.5 megahertz clock signal occurs every third of the servo cell illustrated in FIG. 2. Thus, as shown in FIG. 8A, a cell spans 3 cycles (e.g., T.sub.0 -T.sub.2) of the 1.5 megahertz cell division signal.
A divide by three cell division counter 366 is enabled by the 1.5 megahertz cell division signal to count the cell divisions modulo 3. The counter 366 has 2 outputs designated cell division "A" (CDA) and cell division "B" (CDB). The CDA output has a positive transition 368 at the first third division of each cell as depicted in FIG. 8A. The CDB signal has a positive transition 370 at the second third division of each cell.
An additional counter 372 and 384 divides the output of the counter 366 by 6 to count the cells of the pattern modulo 6. The output of the counter 372 is designated cell count "A" (CCA). The outputs of the counter 384 are designated cell count A (CCH) and cell count B (CCH). As shown in FIG. 8A, the CCA signal has a positive transition every other cell.
A cell type generator 378 selects the type of cell appropriate for the servo track being generated. As previously mentioned in the illustrated embodiment, there are 4 types of servo tracks comprised of 2 types of cells, early cells and late cells, as shown in FIG. 2. As indicated in FIG. 6, the servo track type to be written is defined by bits DB0 and DB1 of the gate array command word from the microcomputer. The cell type generator 378 accepts as inputs command word data bits DB0 and DB1 together with cell count signal (CCA) to generate cell type output CT which is a logic zero for late type cells and a logic 1 for early cells. Thus, as shown in FIG. 8A, the cell type generator output CT is a logic zero for command word data bits DB0=0 and DB1=1. Consequently, the servo write data output designated "track data" outputs a series of late type cells. However, once the command word bit DB1 changes to logic zero, the cell type output CT changes to logic 1 and the track data output changes to early type cells. A pattern generator 379 generates the actual late and early cell patterns from the selected cell type signal CT and the cell division signals CDA and CDB as shown in FIG. 7.
Referring back to FIG. 2, a data bit may be encoded in the Priam servo pattern by inserting a negative transition at the midpoint of the cell. An example of such a negative transition to encode a logic one data bit is indicated at 380 for servo track n. In the Priam servo pattern, a 6-bit serial data word is used to indicate index, or 1 of 2 guard band track types. Specifically, a binary 101010 encodes index, and a binary 100100 or 100010 encodes a guard band word.
FIG. 8B illustrates the generation of data words for index and guard bands. The cell count signals CCA, CCB and CCC are decoded for purposes of index and guard band generation. A trigger circuit 386 provides a "begin burst" timing trigger signal BB at the end of every sixth cell.
As previously mentioned, an index is provided at one angular location on each servo track. An index counter channel 388 counts the clock head read back (by counting 1.5 megahertz phase-locked loop clocks) pulses to mark the position of the servo track index. The index counter channel 388 activates an index burst trigger circuit 390 which outputs an index burst signal IDB which is at a logic one state for a duration of 6 cells as shown in FIG. 8B. The beginning and end of the logic one condition of the IDB signal are triggered by the begin burst timing trigger signal BB. While the index burst signal IDB is active, a data multiplexer 392 serially generates the index word 101010 from the index burst signal IDB and cell count A signal CCA as shown in FIGS. 7 and 8B.
As previously mentioned, the servo pattern of the illustrated embodiment has guard bands at the inside and outside borders of the servo pattern to mark the boundaries of the data areas. While a guard band is being written, a guard band counter channel 394 counts the cells of the pattern (by counting phase-locked loop clocks) and activates a guard band burst trigger circuit 396 so that a guard band burst enable signal GBB is output every 255 servo cells of the guard band track at fixed angular offsets from the index.
As shown in FIG. 6, the gate array 250 is caused to write a guard band track when the gate array command word bit (DB30) from the microcomputer is a logic one. The guard band burst trigger circuit 396, like the index burst trigger circuit 390, is triggered by the begin burst trigger signal (BB). Thus, at each 255 cell cycle as indicated by the guard band counter channel 394, the guard band burst enable signal GBB goes active (see cells 6-11) at one begin burst signal and terminates at the next begin burst signal if the command word bit DB3 is active as shown in FIG. 8B.
A guard band data generator 398 serially generates either the guard band data word 100100 or 100010 depending on the state of gate array command word bit DB2 from the microcomputer. The data multiplexer 392 serially outputs at DTM the generated guard band data word GBD if the guard band burst enable signal GBB is active and if the index data burst enable signal IDB is inactive. The data multiplexer 392 give priority to the index word should both the index word and the guard band word occur simultaneously.
The output DTM of the data multiplexer 392 is provided to a pattern mix circuit 400 which encodes the data into the cell pattern PG being generated by the pattern generator 379. Each data pulse is encoded into a cell by forcing a one to zero logic transition at the exact midpoint of a cell when the data multiplexer 392 indicates that an encoded data bit should occur during the present cell. A cell half detector 402 using the 3 megahertz clock signal output by the divider circuit 360 and the cell division signals CDA and CDB from the divider circuit 366 generates the cell half signal CH which has a negative to positive transition at the midpoint of each cell as depicted in FIG. 8A. At cell third T.sub.16, a cell is shown encoded with a logic 1 data bit. Thus, a transition to a logic zero level is inserted at the midpoint of the output pattern cell during cell third T.sub.16. Since an early type cell is normally at logic state one at the midpoint, the pattern mix logic 400 forces the second half of the cell to a logic zero state so that the cell may have logic one to logic zero transition at the midpoint to indicate the encoded data bit.
The output PM of the pattern mix circuit 400 is provided to an output latch 402 which resynchronizes the generated servo pattern using the 6 megahertz and 18 megahertz clock signals. The servowriter data output of the latch 402 is in turn provided to the servo read-write amplifier 270 and head 208 as shown in FIG. 4.
Once the servo pattern has been written onto a servo track, the servo head 208 is used to read the pattern back to verify that the servo pattern has been correctly written. As previously mentioned, the servo pattern verification function is performed by logic block 316 (FIG. 5) of the gate array 250. As shown in greater detail in FIG. 9, the servo pattern verifier logic 316 includes an over-amplitude detector circuit 450 and an under-amplitude detector circuit 452. The over-amplifier detector circuit 450 includes a first comparator 454 which compares the plus read signal from the servo read-write head 208 to a voltage reference V.sub.REF. A second comparator 456 compares the negative read signal to the same voltage reference V.sub.REF. In the illustrated embodiment, the reference voltage V.sub.REF is fixed; however, the comparison level may be controlled by varying the automatic gain (AGC) level of the servo read amplifier 270 as described in greater detail in co-pending application entitled "Disk Drive Clock Writer". If either comparator 454 or 456 indicates that the associated read signal has exceeded the comparison level indicating an over-amplitude condition, the output of an OR gate 458 having inverting inputs coupled to the outputs of the comparators 454 and 456 becomes active, incrementing a counter channel 460 which logs each over-amplitude error condition.
An example of the operation of one of the comparators of the over-amplitute detector circuit 450 is illustrated in FIG. 10. As shown therein, a read signal (either the plus read or minus read signal) is compared to a comparison level 462. During time intervals T0 and T1, the amplitude of the read signal does not exceed the comparison level 462. Consequently, the over-amplitude error signal output of the OR gate 458 remains at a low or logic zero state. However, at the end of time period T2, the amplitude of the read signal exceeds (in the negative direction) the comparison level 462, causing the over-amplitude error signal to rise to a logic one, clocking (that is, incrementing) the error logging counter channel 460.
The existence of an over-amplitude condition in the servo pattern just written to the disk drive is considered to be an error condition. If the number of over-amplitude conditions logged in the counter channel 460 exceeds a predetermined maximum, all servo tracks are discarded and rewritten.
The under-amplitude detector circuit 452 also includes a pair of comparators 470 and 472 which compare a comparison level defined by the analog output DAC 0 of a digital to analog converter channel 262 (FIG. 4) to the plus read and minus read signals, respectively, from the disk drive. The occurrence of an under-amplitude condition, unlike an over-amplitude condition, is not always indicative of an error since in each cell the servo pattern read signal will cross the origin at least two times. Thus, the under-amplitude detector circuit 452 is designed to detect the occurance of under-amplitude conditions at locations where such conditions are not expected and to log them as errors.
The output of the first comparator 470 of the under-amplitude detector circuit 452 is coupled to the "D" input of a "D" type flip-flop 474. Similarly, the output of the second comparator 472 is coupled to a "D" type flip-flop 476. The outputs of the flip-flops 474 and 476 are coupled to the inputs an OR gate 478, the output of which is connected a "D" type flip-flop 480. The output of the flip-flop 480 is coupled to the input of a counter channel 482 which logs the under-amplitude errors.
The under-amplitude detector circuit 452 effectively compares the detected under-amplitude conditions to the generated servo pattern to determine if the under-amplitude conditions occur where expected. If not, the error logging counter channel 482 is incremented to indicate an error condition.
The operation of the under-amplitude detector circuit is illustrated in FIG. 10 in connection with one of the comparators 470 or 472. As shown therein, each comparator of the under-amplitude detector circuit 452 compares a read signal (either plus or minus) to a comparison level 484 set by channel DAC 0 of the digital analog converter 262. The output of the comparator stays high so long as the read signal does not exceed the comparison level 484. As is well known, the read electronics of a disk drive act as a differentiator of the pattern written on the disk such that the read signal pulses at each transition of the pattern. Thus, as shown at a time interval T0, the read signal exceeds the comparison level 484 just before the expected 0 to 1 transition of the servo pattern data. Consequently, the output of the comparator drops to a logic zero when the read signal crosses the comparison level 484 and then returns to a logic 1 when the read signal recrosses the comparison level 484.
To compare the detected under-amplitude condition to the servo pattern, the servo pattern write data output of the servo pattern generator 314 is used to clock the "D" type flip-flops 474 and 476 of the under-amplitude detector circuit 452. The servo pattern write data is delayed by a programmable delay line 486 to match the inherent delay caused in the read signal by the circuitry between the read head and the under-amplitude detector circuit.
As shown in FIG. 10, the rising edge of the servo write data during time interval T.phi. occurs in the midpoint of the logic zero state of the output of the under-amplitude comparator. Consequently, when the associated flip-flop 474 or 476 is clocked by the delayed servo pattern write data, no error signal is stored in the flip-flop, indicating that the under-amplitude condition occured in the proper location. Similarly, the associated flip-flop 474 or 476 is clocked during time interval T1 at the under-amplitude output logic zero state, again indicating that no error has occurred.
However, during time interval T2, the read signal does not exceed the comparison level 484. Consequently, when the servo pattern write data signal clocks the associated flip-flop, that flip-flop is set causing the flip-flop 480 to be set, indicating an error condition. The setting of the flip-flop 480 causes the error logging counter channel 482 to be incremented. The output of the flip-flop 480 is also connected to the reset inputs of the flip-flops 474 and 476, resetting these flip-flops after each detected error condition, which in turns resets the flip-flop 480 on the next cycle of the 18 megahertz signal clocking the flip-flop 480.
It is seen from the above that the servo pattern verifer logic 316 detects both over-amplitude pulses as well as missing pulses of the servo pattern written. In addition, the width or phase of the pulses may be readily measured by varying the delay of the programmable delay line 486 (type TTL DL-14-4, manufactured by Engineered Components, Corp.). The amount of delay of the delay line 486 is set by the microcomputer 216. After each track verify operation, the error logging counter channel counts may be retrieved by the microcomputer.
FIG. 11 shows in greater detail the mechanical status and control block 312 of the gate array 250 of FIG. 6. A decoder circuit 500 decodes the bits of the gate array command word from the microprocessor to initiate various mechanical operations including loading and unloading the read-write heads and starting and stopping the spindle of the disk drive. As shown in FIG. 6, a mechanical operation is initiated by command word bits DB6, DB5=01. The particular type of mechanical operation is defined by a command word bits DB1 and DB0. For command word bits DB1, DB0=11, indicating a load head operation, a JK flip-flop 502 is set, the output of which is coupled to the head load actuator drivers of the driver and sensor electronics interface 226 of the chassis base 202 of FIG. 3. Command word bits DB1, DB0=10, indicating a head unload operation, reset the flip-flop 502. A second JK flip-flop 504 operates in a similar manner to start and stop the spindle of the disk drive in response to the appropriate command word data bits. The gate array contains "D" flip-flops which are connected with other logic elements to form the J-K flip-flops shown.
In the illustrated embodiment, the actuator for loading and unloading the servo head is a simple solenoid. However, the clock head load actuator is a DC motor. A motor drive controller 506 for the clock head DC motor signals a reduced level of motor drive (HOLD) whenever the clock head motor has reached either end of the range of motion of the clock head. The sensor electronics interface 226 of the chassis base 202 of FIG. 3 provides a "CLOCK HEAD UP STOP" signal when the clock head has reached its upper most (retracted) position and a "CLOCK HEAD DOWN STOP" signal when the clock head has reached its lowest (deployed) position. These sensor signals are provided on a sensor bus 508 to the sensor port latches 282 (FIG. 4) for the microcomputer and the gate array 250.
In addition to the clock head fully loaded and fully unloaded position signals, sensors of the interface electronics 226 also provide outer and inner crash stop signals for the carriage arm 206. Two more sensors detect the carriage rezero and unload positions. Finally an additional sensor indicates when the spindle motor has reached operating speed.
The mechanical status and control logic 312 of the gate array 250 further includes a fault detector 510 which detects the occurrance of a status fault and initiates a system reset when the carriage arm activates one of the crash stop sensors. The fault detector circuit 510 further includes a head/spindle fault detector circuit 512 which signals a status fault condition when an illegal clock head load or unload operation is attempted or when a data operation is attempted without the heads being loaded and the spindle being at operating speed.
As previously mentioned, the gate array 250 of the illustrated embodiment is a type XC2018 integrated circuit manufactured by Xylinx, Inc. This integrated circuit allows the logic circuitry of the servowriter controller 224 to be readily configured as appropriate to write the desired servo pattern. Thus, for example, the servo pattern generator logic illustrated in FIG. 7 is, with the exception of the index counter channels 388 and 394, implemented in the illustrated embodiment by configuring the gate array 250 to perform these logic functions. Similarly, a portion 514 of the servo pattern verifier logic of FIG. 9 and the mechanical status and control circuitry 312 of FIG. 11 are also implemented by appropriate configuration of the gate array 250.
The general structure of the gate array 250 is shown in FIG. 12. The elements of the array include three categories of user programmable elements: I/O blocks 520, configurable logic blocks 522 and programmable interconnections 523. The I/O blocks 520 provide an interface between the logic array and the package pins of the device. The configurable logic blocks 522 perform user specified logic functions and the interconnect resources 523 are programmed to form networks that carry logic signals among the blocks.
Configuration of the gate array 250 is established by programming a distributed array of memory cells. A development system provided by the manufacturer assists in the generation of the program used to configure the gate array 250. An example of a program to implement the logic of the illustrated embodiment is provided in the attached Appendix C. Detailed schematic diagrams of the servowriter controller 224 are set forth in Appendix D.
The construction and operation of the gate array 250 is described in greater detail in "The Programmable Gate Array Data Book" by Xylinx. FIG. 13 shows the input/output blocks 520 in greater detail. Each user configurable I/O block 520 provides an interface between the external package pin of the device and the internal logic. Each I/O block 520 includes a programmable input path and a programmable output buffer. An input buffer portion 524 provides threshold detection to translate external signals applied to the package pin to internal logic levels. The input buffer threshold of the I/O blocks 520 can be programmed to be compatable with either TTL of CMOS. The buffered input signal drives both the data input of an edge triggered "D" type flip-flop 526 and one input of a two input multiplexer 528. The output of the flip-flop 526 provides the other input to the multiplexer 528. The user can select either the direct input path or the registered input, based upon the content of the memory cell controlling the multiplexer.
Output buffers in the I/O blocks 520 provide drive for high fan-out CMOS or TTL compatible signal levels. Each I/O block output buffer 530 is controlled by the contents of two configuration memory cells which turn the buffer on or off or select logical three-state buffer control. The user may also select the output buffer three-state control TS.
As shown in FIG. 12, the configurable logic blocks 522 are arranged in a matrix in the center of the device 250. Referring now to FIG. 14, each configurable logic block 522 is shown to include a combinatorial logic section 532, a storage element 534, and an internal routing and control section 536. Each configurable logic block 522 has four general purpose inputs; A, B, C, and D; two outputs, X and Y, and a clock input k. The combinatorial logic section 532 uses a table look-up memory to implement Boolean functions. This technique can generate any logic function of up to four variables with a high-speed 16-bit memory. As shown in FIG. 15(A), each combinatorial logic section 532 can perform any function of four variables or, as shown in FIG. 15(B), any two functions of three variables each. FIG. 15(C) shows still another op ion for configuring the combinatorial logic 532.
Programmable interconnection resources in the gate array 250 provide routing paths to connect inputs and outputs of the input/output blocks 520 and the configurable logic blocks 522 into desired networks. The interconnections of the illustrated embodiment are composed of metal segments, with programmable switching points provided to implement the necessary routing.
Three types of resources accommodate different types of networks: general purpose interconnect, long lines interconnect and direct interconnect. As shown in FIG. 16, the general purpose interconnect in the illustrated embodiment is composed of four horizontal metal segments 540 between the rows of the logic blocks 522, and five vertical segments 542 between the columns of logic blocks 522 and I/O blocks 520. Where these segments would cross at the intersections of rows and columns, switching matrices 544 are provided to allow interconnections of metal segments from the adjoining rows and columns. Switches in the switch matrices and on block outputs are transistors, each controlled by a configuration memory bit. FIG. 16 shows the general interconnect used to route a signal from one logic block 522(a) to three other logic blocks 522(b)-522(d). The possible switching matrix combinations of the illustrated embodiment are illustrated in FIG. 17.
The long line interconnects run both vertically and horizontally the height or width of the interconnect areas as indicated at 550 and 552, respectively, in FIG. 18. Each vertical interconnection column has three long lines; each horizontal row has one, with an additional long line adjacent to each set of input/output blocks 520. The long lines 550 and 552 bypass the switch matrices 544 and are intended primarily for signals that travel a long distance or must have minimum skew among multiple destinations.
As shown in FIG. 19, direct interconnects provide an efficient implementation of networks between adjacent logic or I/O blocks. For each configurable logic block, the X output may be connected directly to the C or D inputs of the configurable logic block above and to the A or B inputs of the configurable logic block below, as indicated at 554. In addition, the Y output can use a direct interconnect 556 to drive the B input of the block immediately to its right. Where configurable logic blocks are adjacent to I/O blocks, direct interconnects are provided to the I/O block inputs I on the left edge of the device, the output 0 on the right edge or both on I/O blocks at the top and bottom of the device.
The overall operation of the servowriter 200 in writing clock and servo patterns for a disk drive is illustrated in FIG. 20. First, the user installs (block 570) the disk drive on which a clock pattern and servo pattern are to be written, onto the servowriter chassis base 202 using the appropriate adapters and clamps for that particular disk drive. The microcomputer 216 then loads (block 572) the appropriate configuration program into the gate array 250 to configure the logic functions and interconnections of the gate array 250 which will allow the gate array 250 to write the desired clock and servo patterns.
A gate array 250 command word is then sent to the gate array 250 by the microcomputer 216 to activate the disk drive spindle and load the clock and servo heads. Once the clock head is in position, the microcomputer 216 sends a command word to cause the servowriter controller 224 to write a clock pattern (block 576) as described more fully in copending application entitled "Disk Drive Clock Writer".
The servowriter is now ready to write the first servo pattern. The carriage arm is activated (block 578) to move the servo head to the first servo track of the servo surface of the disk drive. A servo pattern appropriate for the first track is written (block 580) and is then verified (block 582). Any errors are logged by the microcomputer 216. The blocks 578-582 are then repeated until (decision block 584) the last servo track has been written. Once the last servo track has been written (decision block 584) the spindle is deactivated (block 586) and the heads are unloaded. If the errors logged by the microcomputer 216 are acceptable (decision block 588) the servo writing operation is complete. Otherwise, the servo track is discarded (block 590) and the servo pattern is redone.
Thus, as seen from the above, the present invention provides a configurable servowriter which is readily configured to provide the appropriate servo pattern and hardware control signals for many different types of disk drives. In the illustrated embodiment, the configurable logic elements for generating the servo pattern and control signals are preferably integrated on a single monolithic semiconductor chip.
It will, of course, be understood that modifications of the present invention, in its various aspects, will be apparent to those skilled in the art, some being apparent only after study, and others being merely matters of routine electronic design. For example, the particular logic arrangement will depend upon the target disk drive. In addition, other logic cell array integrated circuit chips may be used.
Other embodiments are also possible, with their specific designs dependent upon the particular application. As such, the scope on the invention should not be limited by the particular embodiments herein described, but should be defined only by the appended claims and equivalents thereof. ##SPC1##
Claims
I claim:
1. A configurable servo pattern writer for writing a selected servo pattern composed of a plurality of servo pattern types which are to be written in a selected order onto a magnetic disc of a magnetic disc drive data storage device, comprising: (a) clock signal producing means for providing a plurality of clock signals which bear a fixed relation to one another and which differ form one another with respect to one of frequency and phase; (b) pattern type control signal generating means for producing control signals representative of a desired servo pattern type; (c) a programmable gate array composed of a plurality of logic gates and programmable interconnection means for interconnecting said logic gates in a logic pattern in response to program signals, said programmable gate array having a plurality of signal inputs connected to receive the plurality of clock signals and the control signals and a single data output for providing an output signal dependent on the clock signals, the control signals and the logic pattern in which said logic gates are interconnected; (d) a servo read-write head having a signal input connected to said data output of said gate array and constructed for writing upon a magnetic disc a servo pattern corresponding in form to the output signal provided at said output of said gate array; and (e) means for storing, and applying to said interconnection means, a logic gate interconnection program which defines an interconnection of said logic gates in a pattern for giving the output signal at said data output of said gate array the form of the selected servo pattern.
2. The configurable servo pattern writer of claim 1 wherein the clock signals provided by said clock signal producing means include three different clock signals all of which have the same frequency, and wherein a first and a second one of said three clock signals differ from one another in phase and the third one of said three clock signals has a pattern different from that of the first and second clock signals.
3. The configurable servo pattern writer of claim 1 wherein the means for storing further stores a logic function program, and said logic gates include programmable logic blocks for implementing selected logic functions in response to the logic function program so that the output of the logic gates is the selected servo pattern.
4. The configurable servo pattern writer of claim 3 wherein the programmable logic blocks are arranged in an array and the programmable interconnection means comprises a first plurality of connecting lines disposed in the array, a second plurality of connecting lines disposed in the array and a plurality of switching matrices for selectively interconnecting connecting lines of the first plurality to connecting lines of the second plurality in response to the logic gate interconnection program.
5. The configurable servo pattern writer of claim 4 wherein the plurality of logic gates and programmable interconnection means comprise a logic cell array integrated circuit chip.