Differential Stage Comprising MESFETS

This invention relates to an integrated circuit comprising a differential-transistor-pair with MESFETs which are coupled to a supply voltage via a respective load, a node between the respective MESFET and its associated load being coupled to a sub-circuit for controlling the same.

The invention is used, for example, in a latch-type comparator which serves to compare an analog input voltage V.sub.IN with an analog reference voltage V.sub.REF and which is formed by field effect transistors.

The invention can also be used, for example, in a synchronized comparator circuit comprising at least two of these circuits connected in parallel.

As an example, the invention may be used for realizing an analog-to-digital converter which is referred to as a parallel converter and in which the analog input signal is applied to the inputs of several parallel comparator circuits in order to obtain a digital output signal. In the comparator circuits the input voltage is compared with a reference voltage which differs for each comparator circuit. The output signals of the comparator circuits are converted into a digital output signal by means of a decoding device. The synchronized comparator used in such parallel analog comparator circuits generally has a construction as described above.

A circuit of this kind is known, inter alia, from European Patent Application No. 85 201742.5, which corresponds to U.S. Pat. No. 4,649,293 (Mar. 10, 1987).

This U.S. Patent, hereby incorporated by reference, discloses a voltage comparator which is realized by means of transistors, each of which comprises a control terminal, a first main terminal and a second main terminal. The comparator comprises:

an acquisition stage which serves to compare an analog input voltage (V.sub.IN) with an analog reference voltage (V.sub.REF) and to output the comparison result in the form of an intermediate signal (V.sub.M) and its complement (V.sub.M). This stage includes two transistors which constitute a first differential pair. The input voltage (V.sub.IN) and the reference voltage (V.sub.REF) are applied to the respective control terminals of these transistors, whose first main terminals form a connection point which serves to receive a control current and whose second main terminals are coupled, via a respective resistive load, to a first d.c. power supply terminal (V.sub.DD) thus to supply the intermediate signal and its complement, respectively;

a sub-circuit formed as a memory stage which is coupled to the acquisition stage and which serves to produce the logic states determined by the signals supplied by the acquisition stages. The memory stage includes two transistors which form a second differential pair connected clocked bistable storage circuit, the signals supplied by each branch of the acquisition stage being applied to the respective control terminals of these transistors whose first main terminals form a connection point and whose second main terminals are cross-wise coupled to the control terminals of the transistors of the second pair, the latter connection points constituting the outputs of said memory stage.

In the known circuit:

the connection point of the first differential pair is coupled to a second d.c. power supply terminal V.sub.SS (e.g. ground) via a current source transistor;

the connection point of the second differential pair is connected directly to the potential of the second d.c. power supply terminal V.sub.SS (e.g. ground);

the second differential pair is coupled to a third differential pair which includes two transistors which are connected parallel to the transistors of the second differential pair and whose control terminals receive a clock signal (C).

Moreover: the second main terminals of the first differential pair are coupled to the sub-circuit, more particularly to the respective control terminals of the second differential pair, each time via a coupling resistance, and the current source transistor of the first differential pair can be controlled by the clock signal in one version or by a third d.c. supply voltage in a second version.

This known circuit has a number of drawbacks.

First of all, the output conductance of each of the transistors of the acquisition stage, which are field effect transistors of the MESFET type, changes as a function of the frequency.

Consequently, the impedance at the drain of these MESFETs can vary by as much as a factor 3. Thus, in the case of high frequencies this impedance becomes three times lower than in the case of low frequencies.

In the case of a transition, the reference voltage V.sub.REF does not change and the input voltage V.sub.IN is subject to an extremely fast variation so that the current derived from the drain of the transistor receiving the input voltage V.sub.IN assumes a high transitory value corresponding to the conductance of this transistor, which has become very high due to said rapid transition.

Subsequently, the current derived from the drain of the transistor receiving this input voltage V.sub.IN drops to a lower value which corresponds to the static value of the output conductance of this transistor.

In the case of fast switching of V.sub.IN about V.sub.REF, at the electrical level this becomes manifest as low frequency decays of the differential output voltage. As a percentage, such decay may reach 10% of the output dynamics. If, for example, before a switching operation in a state where V.sub.IN .noteq.V.sub.REF the voltage difference between the output and the complementary output is 1 V, after fast switching, during which V.sub.IN has become equal to V.sub.REF, the output and the complementary output maintain a level difference in the order of 0.1 V for a non-negligibly short period of time before assuming the same value.

The present invention proposes a circuit in which this decay effect becomes negligibly small.

In accordance with the invention, this object is achieved by means of a circuit as described in the introduction, characterized in that the circuit comprises smoothing means for smoothing fluctuations of an output impedance of said first differential transistor pair during switching.

In one embodiment in accordance with the invention, the circuit is characterized in that the smoothing means comprises, connected between each of said MESFETs and its associated load, a respective cascode transistor which is biased at a predetermined voltage, a node between the respective cascode transistor and the relevant load being coupled to the sub-circuit.

This cascode stage isolates the differential stage from its loads in which a voltage gain occurs. Thus, it is achieved that a voltage gain no longer exists at the level of the outputs of the differential stage, thus minimizing the consequences of the fluctuations of the output conductance of this stage as a function of the frequency.

In an embodiment of the invention, the circuit is further characterized in that the smoothing means comprise a feedback means which controls each of the MESFETs of the differential transistor pair by a signal indicative of a voltage across the other MESFET of the differential pair.

This counter-effect stabilizes the output voltages of the differential stage.

In a preferred embodiment, the circuit is characterized in that each MESFET of the differential transistor pair comprises a first gate electrode and a second gate electrode for receiving input signals and for connection to the other MESFET of the differential pair, respectively.

In this embodiment, the circuit is particularly compact and hence attractive for high-density integration.

Therefore, the circuit formed by the differential stage, the sub-circuit, the loads controlled in accordance with the invention and the smoothing means in accordance with the invention, is particularly suitable for forming the acquisition stage of a synchronized comparator for comparing an analog input voltage V.sub.IN with an analog reference voltage V.sub.REF, which voltages are applied to the inputs of the differential stage. The comparator also comprises a memory stage which is connected to the acquisition stage via the loads.

Thus, not only the effects of the fluctuations of the output conductance of the acquisition stage as a function of the frequency are minimized because the cascode stage isolates the acquisition stage from the loads of the memory stage in which a voltage gain occurs, but the cascode stage also provides an increase of the bandwidth and of the gain of the entire comparator.

The invention will be described in detail hereinafter with reference to the accompanying diagrammatic drawings; in which:

FIG. 1 shows a comparator circuit in accordance with the invention;

FIG. 2a shows a block diagram of a system consisting of two comparator circuits in accordance with the invention;

FIG. 2b is a schematic diagram of the system of FIG. 2a;

FIG. 3 shows an example of the sequencing of the signals in the circuit shown in FIG. 1;

FIG. 4 shows the sequencing of the signals in the system shown in FIG. 2b; and

FIG. 5 shows an analog-to-digital converter realized by means of a circuit in accordance with the invention.

FIG. 1 shows a synchronized comparator which is, for example, attractively realized by means of enhancement-type field effect transistors which are made, for example, of gallium arsenide and whose pinch-off voltage V.sub.T >0 so that they are normally pinched off in the absence of a signal.

This synchronised comparator comprises first of all an acquisition stage which is formed by two source-coupled transistors 10 and 11 whose gates receive the analog input voltage V.sub.IN and the analog reference voltage V.sub.REF, respectively.

The sources of the transistors 10 and 11 are coupled to the connection point 9 and are further connected to the negative supply voltage V.sub.SS via a current source transistor 109 which is controlled by the clock signal C and whose source is connected to V.sub.SS via a resistance R.sub.9.

This synchronized comparator also comprises a sub-circuit which includes a memory stage which is formed by two transistors 32 and 31 which are coupled to the connection point 59 by way of their sources. This connection point is connected directly to ground potential.

The sub-circuit also comprises two transistors 52 and 51 for control of the memory stage and which are connected parallel to the transistors 32 and 31, respectively, and which are controlled by a control or clock signal C. The sub-circuit coupled to nodes 1 and 2 thus comprises a clocked bistable storage circuit.

Thus, when the acquisition stage is activated, the memory stage immediately assumes the state 0. As is known, for suitable operation of such an acquisition stage coupled to a memory stage it is absolutely necessary that the differential pair 31, 32 of the memory stage be de-activated at exactly the instant at which the differential pair of the acquisition stage is activated. The circuit would otherwise exhibit instabilities. This condition is often very difficult to comply with, notably when the acquisition stage and the memory stage are controlled by different clock signals.

This drawback is circumvented because the memory stage and the acquisition stage are controlled by the same control signal, i.e. the clock signal C.

The gates 2 and 1 of the transistors 32 and 31 are cross-wise coupled to the drains of the transistors 31 and 51, and 32 and 52 respectively. The gates of the transistors 32 and 31 also receive, via respective coupling resistances R.sub.2 and R.sub.1, the signals supplied by the acquisition stage.

The connection points 2 and 1 constitute the output of the assembly formed by the acquisition stage and the memory stage.

In the case of a transition as shown in FIG. 3, during which the reference signal V.sub.REF denoted by a non-interrupted line is constant and the input signal V.sub.IN denoted by an interrupted line quickly changes over from the level V.sub.1 to the level V.sub.0 at the instant t.sub.0, the signals Q and Q present at the nodes 1 and 2 should also quickly change over from the states 1 and -1, respectively, to the same state 0.

However, if the transition of V.sub.IN is abrupt, as stated above the output conductance of the transistor 10 which receives V.sub.IN becomes three times higher than the output conductance of the transistor 11 at the instant t.sub.0 of the transition.

Consequently, if the drain voltages of the transistors 10 and 11 are applied directly to the memory stage as in the prior art via the coupling resistances R.sub.1 and R.sub.2, the signals Q and Q at the nodes 1 and 2 will not instantaneously assume the level 0 but only after a period of time t.sub.1, the time difference t.sub.0 -t.sub.1 not being negligibly small.

FIG. 3 shows, by way of dotted lines, that at the instant t.sub.0 of the fast transition the delay could reach a value of 10% of the value of the voltage corresponding to the level difference between Q and Q before the transition.

Therefore, in accordance with the invention this effect is reduced by isolating the differential stage from the loads in which a voltage gain occurs.

Thus, a voltage gain no longer exists at the level of the drains of the transistors 10 and 11. The differential transitions of the drain-source voltage of these transistors are thus limited and the effects of the fluctuations of the output conductance of the transistor 10 as a function of the frequency are minimized.

In accordance with the invention, this object is achieved by smoothing means made up of a cascode stage which is formed by transistors 14 and 15. The drains of the transistors 14 and 15 of the cascode stage are connected to the d.c. supply voltage V.sub.DD via the load resistances R.sub.4 and R.sub.3, respectively. The coupled gates of these transistors are connected to ground. Their sources are connected to the nodes 34 and 35.

The nodes 34 and 35 (see FIG. 1) then exhibit a low differential voltage gain.

This differential stage and the cascode stage which supplements it is to be used in accordance with the invention for realizing the acquisition stage of a comparator.

However, this differential stage comprising the same smoothing means could also be used for other circuits forming loads.

In the comparator circuit which is described herein by way of example, the cascode stage isolates the acquistion stage from the memory stage, increases the bandwidth and also the gain of the entire comparator stage.

If, for example at the instant t.sub.O of a fast transition the level difference between the signals Q and Q at the nodes 2 and 1, respectively, is 1 V, the level difference between the signals present on the nodes 34 and 35 will only be in the order of 0.3 V.

Operation will be further improved by providing, as is shown in FIG. 1, additional smoothing means in the form of a differential acquistion stage which is formed by two dual-gate transistors.

The first transistor 10 of the differential pair includes the gates 10' and 12.

The second transistor 11 of the differential pair includes the gates 11' and 13.

As has already been stated, the gates 10' and 11' perform the differencing operation between the input signal V.sub.IN and the reference signal V.sub.REF.

The gates 12 and 13 constitute a stage which is controlled by the differential pair 10 and 11.

In accordance with the invention, the outputs of the differential pair, formed by the drains 34 and 35, are couteracted via the inputs of this stage, formed by the gates 12 and 13 of the dual-gate transistors 10 and 11.

Thus, the two upper gates 12 and 13, which are cross-coupled to the drains 35 and 34, respectively, of these dual-gate transistors stabilize the intermediate drain voltages at the points 7 and 8 of these dual-gate transistors.

The voltage decay percentages of the signals Q and Q are then reduced from the prior art value of 10% to a value of 0.6% as demonstrated by the non-interrupted curve of FIG. 3.

When the differential stage circuit comprising the means in accordance with the invention is used for realizing an acquisition stage for a comparator circuit, the switching speed at the output of the stage can be increased, and hence also the speed at which the comparison result is produced.

This comparator thus forms a high performance element and can be used for realizing ultrafast and precise analog-to-digital converters.

A third d.c. supply voltage V.sub.B may be applied to the gate of the current source transistor 109, instead of the control signal C, in order to render this transistor continuously conductive (see FIG. 1). The acquisition stage then operates continuously and instability phenomena are also avoided.

This version is of particular interest when the comparator is to be limited to the single acquisition stage coupled to the memory stage.

The performance of the comparator in accordance with the invention can be further improved by means of a system consisting of two comparators as described above which are grouped in accordance with the diagrams shown in the FIGS. 2a and 2b.

To this end, the output nodes 1 and 2 of the first comparator stage are provided with invertor-followers. In particular, at the connection node 2 the inverter stage is formed by a transistor 102 and the resistance R.sub.102 and the follower stage is formed by a transistor 100 and resistance R.sub.100.

In the same manner, for connection node 1, the inverter stage is formed by transistor 103 and resistance R.sub.103, and the follower stage by transistor 101 and resistance R.sub.101.

The inverter stage is provided to increase the high level at the output of the memory stage. The follower stage is provided to decrease the output impedance of the combination of the acquisition stage-memory stage.

The outputs V.sub.M and V.sub.M of these stages are available at the node common to transistor 100 and R.sub.100, and at the node common to transistor 101 and R.sub.101, respectively.

As shown in FIG. 2a, the system of synchronized comparators according to the invention comprises an acquisition stage A.sub.1, coupled to a first memory stage M1 via coupling resistance R.sub.C and an amplifier stage A.sub.2 having a structure similar to that of acquisition stage A.sub.1, coupled to a second memory stage M.sub.2 via coupling resistances R'.sub.C.

The acquisition stage receives at one input the analog signal V.sub.IN and at the other input the analog reference signal V.sub.REF. The outputs of acquisition stage A.sub.1 that are coupled to memory stage M.sub.1 deliver the intermediate signals V.sub.M and V.sub.M (the logic couplement of V.sub.M).

The acquisition stage A.sub.1 and memory stage M.sub.1 are controlled by the same clock signal C.

The amplifier stage A.sub.2 receives the intermediate signal V.sub.M and its complement V.sub.M. Its outputs are coupled to those of the memory stage M.sub.2 to make available a digital output signal that is the difference between the input signal V.sub.IN and the reference signal V.sub.REF.

The amplifying stage A.sub.2 and the memory stage M.sub.2 are each controlled by a signal that is the complement C of the clock signal C.

In another version the acquisition stage and the amplifier stage are controlled by means of a fixed potential V.sub.B.

FIG. 2a shows a system of this kind in the form of functional blocks. The assembly formed by the amplifier stage A.sub.2 and the second memory stage M.sub.2 has exactly the same structure and the same operating principle as the assembly formed by the first acquisition stage A.sub.1 and the first memory stage M.sub.1. Only the transistors and the coupling resistances or load resistances may exhibit slightly different values for better adaptation. The circuit diagram of this assembly is shown in FIG. 2b.

The amplifier stage A.sub.2 is thus formed by two transistors 21 and 20 which are coupled by way of their sources and whose gates receive the intermediate signal V.sub.M and its complement V.sub.M, respectively, which are available at the sources of the transistors 100 and 101 of the follower stages described above. The sources of transistors 20 and 21 are coupled to the connection point 19 and from there are connected to the drain of a current source transistor 119, which is controlled by the complementary clock signal C, and whose source is connected to V.sub.SS via a resistance R.sub.19.

The second memory stage M.sub.2 is formed by two transistors 41 and 42 which are coupled to the connection point 69 by way of their sources. This connection point is directly connected to ground potential.

This memory stage is controlled by two transistors 61 and 62 which are connected parallel to the transistors 41 and 42, respectively, and which are controlled by the complementary clock signal C.

Thus, the memory stage immediately assumes the state O when the amplifier stage is activated.

As before, a d.c. supply voltage V.sub.B may be applied to the gate of the current source transistor 119 in order to render this transistor continuously conductive. The amplifier stage then operates continuously.

The cross-wise coupled gates 72 and 71 of the transistors 41 and 42 receive the signals at the drains of the transistors 42, 62 and 41, 61, respectively. The gates of the transistors 41 and 42 also receive, via respective coupling resistances R.sub.12 and R.sub.11, the signals supplied by the amplifier stage A.sub.2.

The connection points 71 and 72 form the output of the assembly consisting of the amplifier stage and the second memory stage.

In order to isolate the amplifier stage from the memory stage of the second comparator, as before there may be provided a cascode stage which is formed by the transistors 25 and 24 whose coupled gates are connected to ground, whose drains are connected to R.sub.12 and R.sub.11, and whose sources are connected to the drains of the transistors of the differential pair of the amplifier stage.

Moreover, as in the first comparator the transistors of the differential pair of the amplifier stage may be dual-gate transistors whose lower gates 20' and 21' receive the signals V.sub.M and V.sub.M and whose upper gates 22 and 23 are cross-wise connected to the drain of the opposite transistor of this pair.

Moreover, small inverter follower stages may be connected to the nodes 71 and 72. For the connection point 72 the inverter stage is formed by the transistor 112 and the load resistance R.sub.112, the follower stage being formed by the transistor 110 and the resistance R.sub.110.

Similarly, for the connection point 71 the inverter stage is formed by the transistor 113 and the resistance R.sub.113, the follower stage being formed by the transistor 111 and the resistance R.sub.111.

The digital output signal of the comparator is available at the source of the follower transistor 111 and its complement S is available at the source of the follower transistor 110.

As appears from FIG. 4, when the difference between the analog input signal V.sub.IN and the analog reference signal V.sub.REF applied to the acquisition stage is positive and when the negative-going edge of the clock signal C arrives at the instant T.sub.1, the complementary signal V.sub.M, for example, is stored in the high state and the complementary output signal S becomes low.

When at the instant T.sub.2 a positive going edge of the clock signal C arrives, the difference thus becoming negative, the complementary signal V.sub.M becomes low for acquisition and the complementary output signal S is passed to the memory in the low state.

In response to the negative-going edge of the clock signal at the instant T.sub.3, the difference still being negative, the intermediate complementary signal V.sub.M is stored in the low state and the complementary output signal S is high for acquisition.

Finally, at the instant T.sub.4 the difference becomes positive in response to a positive-going edge of the clock signal C and the complementary output signal becomes high for storage.

Thus, the phase of the output signal S follows the sign of the difference between the input signal V.sub.IN and the reference signal V.sub.REF.

The analog-to-digital converter shown in FIG. 5 comprises several comparators (COMP1, . . . COMP N) which are connected in parallel and each of which comprises two inputs. The analog input voltage V.sub.IN to be converted is applied to one input of each comparator. The other input of each comparator receives a reference voltage which is obtained by applying a reference voltage to the terminals of a series connection of several resistances. When all resistances are equal, an arithmetical progression of reference voltages is obtained wherein each pair of successive reference voltages are in the same ratio. In order to produce reference voltages forming a series 1/2, 1/4, 1/8 etc, the associated resistances should be proportional to 2.sup.n, 2.sup.n-1, etc., the latter voltages being used only for indicating an overshoot bit. The outputs of the comparators are connected to the inputs of a logic encoding device (COD) which supplies an n-bit digital signal to the next output in an arbitrary code. This code may be, for example, a Gray code. The construction of the encoding device is subject to the code required, but is not described in detail herein because this encoding device does not actually form a part of the invention. A memory (MEMO) may be coupled to the output of the encoding device in order to save the information of the encoding device during at least one part of the clock period, thus enabling synchronization of the comparators. The clock signal required for the comparators and the memories is supplied by an external circuit. These circuits may be integrated on the same semiconductor substrate.

In the case where the described comparator is realized by means of gallium arsenide transistors having a Schottky gate, the voltages V.sub.IN, V.sub.REF, V.sub.M, V.sub.M, S and S have a value of 0.7 V for the high level and 0.1 V for the low level.

The threshold voltages of the transistors are

V.sub.T =0.1 V.

The d.c. supply voltages are:

for the first: V.sub.DD =2 V

for the second: V.sub.B =-2.5 V, if any

for the third: V.sub.SS =-3 V.

The characteristic values of the gate widths L and the resistances R are stated in the following table:

The use of an identical comparator for realizing an analog-to-digital converter also represents an advantage where the invention is in the form of an integrated circuit.

To those skilled in the art it will be evident that many alternatives are feasible without departing from the scope of the present invention as it is defined in the attached claims.