Digital Cellular TDM System Employing 6:1 Packing of Transcoded Information

The invention relates generally to radio frequency (RF) communication systems and more particularly to RF digital cellular systems incorporating time-division multiplexing (TDM) for data transmission.

RF digital cellular systems employing time-division multiple access (TDMA) carriers offer distinct advantages over analog cellular systems in both system capacity and electrical performance. In a TDMA system, two or more channels of information are transmitted over the same link by allocating a different time interval for the transmission of each channel. For RF digital cellular systems, each time interval (message channel) contains coded speech (or data) for one traffic channel (or voice channel). Such a system using this TDMA format is the United States Digital Cellular System (USDC) defined in EIA/TIA, Project Number 2215 titled "Dual-Mode Mobile Station--Base Station Compatibility Standard" dated December 1989. The system uses the TDMA format for communication between land-based equipment as well as land-based to mobile communication.

Common to all RF digital cellular systems is transcoding which essentially transforms high bit-rate speech data into high quality synthesized speech at low bit-rates. Transcoding in the USDC system is performed on 20 msec blocks of speech and yields an 8:1 compression of speech data. Since the transcoded speech data is transmitted to base-sites in 20 msec blocks, approximately 7/8 of the allotted block is wasted.

One way to more efficiently use this wasted space would be to pack the transcoded data for more than one message channel into a 20 msec block. In packing the 20 msec block, several problems are encountered. First, the packing scheme needs to support the synchronization scheme of the base-sites which uses the eighth bit of every message channel byte in an alternating zero and one pattern. Second, the packing scheme needs to support bit seven (B7) stuffing which leaves the seventh bit of every message channel byte having a zero synchronization bit un-used. This is required by some land-based radiotelephone equipment to retain synchronization in the case where a message channel contains all zeros. A final consideration is that packing six traffic channels into one 20 msec block would lend itself well to the base-sites air-interface transmission scheme.

FIG. 7 depicts the various packing schemes attempted. The first attempt was to use bits one through six (6-bit packing) of each message channel byte (700). This scheme supported B7 stuffing, but only five traffic channels could be packed. Another attempt used bits one through seven (7-bit packing) of each message channel byte (704) and although six traffic channels could be packed, the scheme did not support B7 stuffing.

Accordingly, there exists a need for a RF digital cellular TDMA system that provides efficient packing of traffic channels after transcoding while supporting standard radiotelephone synchronization requirements.

A digital radio time-division multiple access (TDMA) system including a land-line telephone system interface and at least one base-site which generates at least one radio carrier frequency compresses information input from at least two message channels from the land-line telephone system into one information block for transmission in one TDM timeslot. The system inserts synchronization into the information block and conveys at least said one TDM timeslot from the land-line telephone system interface to a base site. The compressed information of said one TDM timeslot is converted to coded information for at least two information timeslots for radio transmission on a radio carrier frequency.

FIG. 1 generally depicts one embodiment implementing 6:1 packing of message channels into one TDM timeslot in accordance with the invention.

FIG. 2 illustrates the framing format of the T1 links used to communicate between land-based equipment.

FIG. 3 illustrates in detail 6:1 packing of message channels into one TDM timeslot in accordance with the invention.

FIG. 4 illustrates a portion of the circuitry located in the land-line telephone system interface used to generate and insert the synchronization pattern described.

FIG. 5 is a flow diagram illustrating the steps the land-line telephone system interface performs to generate and insert the synchronization pattern described. FIGS. 6A and 6B depict the resulting 160 frame information block after packing six 160 bit groups, adding error control, synchronization, header and parity information.

FIG. 7 depicts various packing methods.

FIG. 8 is a flow diagram illustrating the steps a base-site performs to remove synchronization from the 160 frame information block and check each 160 bit group for transmission errors.

FIG. 9 is a flow diagram illustrating the steps a base-site performs to separate 160 bit groups for transmission.

FIG. 1 illustrates 6:1 compression of message channels in accordance with the invention.

A land-line telephone system interface (100) has as input information carried on six separate T1 links (105-110) connected to a land-line telephone system (101). FIG. 2 illustrates the framing format for a T1 link. Each DS1 (200) is comprised of 24 message channels (201-224) and one framing bit (230). Each message channel represents data for one "conversation" and is comprised of 8 bits b1-b8 where bit b1 is the least significant bit and bit b8 is the most significant bit. The bit rate per message channel is 64 Kbit/s.

The land-line telephone system interface (100) of FIG. 1 contains the VSELP speech encoding algorithm (U.S. Pat. No. 4,817,157). Referring to FIG. 3, the VSELP speech encoding algorithm resides in six separate 32K.times.24 static random access memory (SRAM) devices while the algorithm runs on six separate Motorola 56001 digital signal processors (DSP's). The combination of SRAM's and DSP's form six separate processing blocks (301-306). The function of the VSELP speech encoding algorithm is two-fold. First, it obtains 160, 8-bit samples (one 20 msec block) from each message channel in each of the six T1 links, and second, transforms the 160, 8-bit samples into 159 bit groups of compressed data. The 159 bit groups from each processing block (301-306) are serially transferred to a 6:1 compression circuit (310). The 6:1 compression circuit adds a single parity bit to each 159 bit group to form six different 160 bit groups. The 6:1 compression circuit then packs the six different 160 bit groups of data into one information block of 1280 bits. The 1280-bit block of data can be represented by a 20 msec, 160 frame information block. The input Programmable Logic Array (PLA), 6:1 expansion circuitry (312) performs the un-packing of the 160 frame information block of data coming from the base-site.

The 6:1 compression circuit is also responsible for adding error control and synchronization to the 160 frame information block. FIG. 4 depicts the hardware used and FIG. 5 illustrates the steps the 6:1 compression circuit undergoes to insert synchronization into the 160 frame information block. Referring to FIG. 4 and FIG. 5, the 6:1 compression circuit receives a 40 msec framing pulse (interrupt) to initialize counters modulo 40 (405) and modulo 80 (410), internal to the 6:1 compression circuit, to zero (501) and sets the frame synchronization bit to zero (504). The frame synchronization bit, referring to FIG. 2, is the most significant bit in a frame. Turning back to FIG. 4 and FIG. 5, a test is then made to see if a 125 .mu.s pulse has been received (507). If no pulse has been received, the 6:1 compression circuit waits for one. If a pulse is received, internal modulos 40 (405) and 80 (410) are incremented (510). A test is done to determine if internal modulo 80 has reached a count of 80 (513). If modulo 80 has reached a count of 80, internal modulos 40 and 80 are reinitialized to zero. If the count of modulo 80 is less than 80, a test is done to determine if the count of modulo 40 is equal to 40 (519). If the count of modulo 40 is not equal to 40, a J-K flip-flop (415) will toggle the frame synchronization bit (522). If the count of modulo 40 equals 40, the frame synchronization bit will be set to a 1 (516). At this point, whenever a 125 .mu.s pulse is received, the counters increment and toggle the synchronization bit. When modulo 80 counter reaches 80, both modulo 40 (405) and 80 (410) counters are set to zero, the synchronization bit is set to zero and the process is repeated. This means that of the 160 frames that are available, only 80 frames at a time are being used for synchronization.

FIG. 6 depicts the 160 frame information block that results from the 6:1 packing and synchronization. Frames one and 81 of every information block contain header bits which tell the receiving equipment which 160 bit group to look for. Again, the synchronization bit is the most significant bit of each frame. Frame one has as its synchronization bit a `0` and alternates in a `0` and `1` pattern until 40 frames have been counted. At frame 41, the pattern is reverses and a synchronization bit of `1` starts the alternating `1` and `0` pattern until frame 81 is reached. This process is repeated for the next 80 frames, thus two synchronizations occur in one 160 frame information block. Since the sampling rate per message channel on a T1 link is 125 .mu.s, 160 frames of one message channel corresponds to 20 ms, thus, synchronization of the receiving equipment occurs every 80 frames or 10 ms.

Immediately after the header bits are placed in frame one, the 160 bit groups are inserted into the frames. The 160 bits are multiplexed into the 160 frame information block leaving every bit position next to a `0` synchronization bit un-used. This is required in special circumstances for T1 equipment to maintain synchronization. After each 160 bit group has been packed into the desired frames, error control in the form of a cyclic redundant check (CRC) is added. The CRC is an error correction code used to monitor the quality of transmission from the land-line telephone system interface to the base-site. Frames 80 and 160 contain a parity bit pattern to indicate to the receiving equipment when transmission of information for three message channels has been completed. The 160 frame information block shown in FIG. 6 is the block that a base-site will do processing on.

The 160 frame information block enters the base-site as shown in FIG. 3. The TDM interface (314) routes information contained in the TDM timeslot to a dedicated TDM timeslot processor (316). The TDM timeslot processor contains the hardware that decodes the synchronization pattern, checks each of the six 160 bit groups for transmission errors and separates the 160 bit groups. Each group is then coded and sent to the appropriate transmitter (318, 320) for RF transmission.

FIG. 8 illustrates the steps that the base-site goes through to perform synchronization decoding and message channel error detection to the 160 frame information block. 8-bit frames from the transmitted 160 frame information block are clocked into the base-site and the synchronization bit for each frame is stored (802). A test is then done to determine if two consecutive zeros are encountered in the synchronization bit position (804). If two consecutive zeroes (tcz) are encountered, a modulo 80 counter internal to the base-site is reset to zero (806), a tcz counter is incremented (808), the modulo 80 counter is incremented (810), and synchronization begins. If two consecutive zeros are not encountered, a test is done to determine if two consecutive ones (tco) are encountered (812). If two consecutive ones are encountered, a tco counter is incremented (814). After this step and incrementing of modulo 80 (810), modulo 80 is checked to determine if it is greater than or equal to 80 (832). If modulo 80 is equal to 80, tests are performed to determine if tco and tcz are equal to one (836 and 838 respectively). If both are equal to one, a loss of frame alignment flag is set to zero (844) and the internal synchronization bit is set to zero (846). If only one of tco and tcz is equal to zero, the loss of frame alignment is set to one (840), the tco and tcz counters are cleared (842) and the internal synchronization bit is reset to zero (846).

From above, if modulo 80 is not less than 80, a test is done to determine if modulo 80 is equal to 40 (816). If it is, the internal synchronization bit is set to one (818). If it is not, a check of the internal synchronization bit against the input synchronization bit is done (820). Input to this step is also after the internal synchronization bit is reset to zero (846) and the internal synchronization bit is set to one (818). If the input bit is the same as the internal bit, transmission was satisfactory and the entire process ends for that frame (822). If the input bit is not the same as the internal bit, a single bit error detection flag is set (824). After this is set, a test is done to determine if one of the three previous synchronization bits were in error (826). If that test is negative, a two out of four error flag is cleared (828) and the process ends for that frame (822). If the test is positive, the two out of four error flag is set (830) and again the process ends for that frame (822).

Referring back to FIG. 1, the base-site (120) has now received the 160 frame information block of data from one TDM timeslot on a T1 link (115), decoded the synchronization pattern and checked each of the six 160 bit groups for errors. The base-site now separates and codes the six 160 bit groups as coded information for transmission over antennas RF1 (125) and RF2 (130) coupled to the base-site. This separating and coding of the six 160 bit groups disposed in the 160 frame information block is accomplished as follows. Referring to FIG. 9, the first 160 bit group in the 160 frame information block is designated for transmission over antenna RF1 (125 in FIG. 1). The 160 bit group is received from the 160 frame information block (902) and is checked to determine if it resides at the beginning of a 10 msec block (910). If the voice data is at the beginning, the frame count is initialized to zero and the first 10 msec block is distinguished from the second 10 msec block in the 160 frame information block (912). If the data does not reside at the beginning of a 10 msec block, synchronization is removed and error control checked (914). The synchronization bit is then checked for errors (916). If an error is encountered, the previous frame is sent to a transmitter or some other form of error control is employed (918). If an error is not encountered, the voice data is stored in compressed format (920), coded by adding forward error correction and protocol bits (922) and output to a transmitter (924). A test is then performed to determine if the current cycle is for antenna RF1 (926). If it is, data will be received for antenna RF2. If it is not, data will be received for antenna RF1.

Referring back to FIG. 1, after the first 160 bit group has been received from the 160 frame information block, and forward error correction, synchronization and signalling protocol bits added, the information timeslot is transmitted on a first RF carrier out antenna RF1 (125). This first information timeslot corresponds to information timeslot A (135). The process is then repeated for a second 160 bit group in the 160 frame information block. This second 160 bit group gets stored in compressed format, has forward error correction, synchronization and signalling protocol bits added and is transmitted on a second RF carrier out antenna RF2 (130). This second information timeslot corresponds to information timeslot B (138). The process is repeated with a third 160 bit group being output over antenna RF1 (125) in information timeslot C (136). When the process has been completed for all six 160 bit groups, the process is repeated on another 160 frame information block received by the base-site.

Thus, needs have been substantially met through the RF cellular communication system employing at least 2:1 compression summarized below. The invention comprises information input from at least two message channels input into a land-line telephone system interface wherein each message channel is further comprised of one 8-bit timeslot at a transmission rate of 64 Kbit/s. The land-line telephone system interface obtains 160 samples of 8-bit timeslots from each message channel and transforms the 160 samples into at least a first 160 bit group and a second 160 bit group. The at least first 160 bit group and second 160 bit group are then packed into a 1280-bit information block represented by 160 frames of 8-bit TDM timeslots.

Each 160 bit group packed into the 160 frame information block has error control for transmission quality monitoring added while the entire 160 frame information block has a synchronization pattern inserted. The synchronization pattern is an alternating `0` and `1` pattern in the most significant bit of each frame. Frame 1 starts with a `0` and alternates up to frame 41, where a `1` is inserted in the synchronization bit position. The pattern then alternates up to frame 80 and the process is repeated for the next 80 frames. Synchronization occurs when two consecutive 0's are encountered, which is at frames 80/81 and frames 160/1 of the next 160 frame information block.

The 160 frame information block is then conveyed from the land-line telephone system interface to a base-site, one TDM timeslot at a time. The base-site receives the 160 frame information block, synchronizes every 80 frames and checks each 160 bit group for transmission errors. The at least first 160 bit group and the second 160 bit group are then separated and coded to the proper format for transmission. The coded at least first 160 bit group further comprises a first 324 bit group and the coded second 160 bit group further comprises a second 324 bit group. The first 324 bit group is transferred into a first information timeslot for radio transmission on a first radio carrier frequency and the second 324 bit group is transferred into a second information timeslot for radio transmission on a second radio carrier frequency.