US 5,111,417 AGrant
Digital Filter Sampling Rate Conversion Method and Device
Issue Date:1992-05-05
•6 Claims
•2 Drawing Sheets
Abstract
A digital filter providing output samples at a rate B while input samples are being provided at a rate A. The filter impulse response h(t) is sampled at a rate P=a.A=b.B, with P being the lowest common multiple to A and B, to derive Np filter coefficients therefrom. The coefficients are arranged into "a" sets of Np/a coefficients and stored. Output samples are then computed by feeding input samples Sn at incoming rate while permutating the sets of coefficients and generating output samples at the output rate.
Metadata
Assignee
- International Business Machines Corp.
Inventors
- Jacques Belloc
- Claude Galand
- Emmanuel Lancon
- Andre Milewski
- Michel Quintin
Application Information
Application Number:US 5595339
Filing Date:1990-07-19
Priority Date:1988-08-30
Art Unit:231
Classifications
IPC:
G06F 1531
Field of Search:
364724.01;724.1;724.16
Patent Drawings (2 sheets)
Description
Field of Invention
This invention deals with digital signal processing generally; more particularly, it deals with a method and device for digitally converting a signal sampling rate from one given rate to another given rate.
Background of the Invention
Conventional digital signal processing is achieved by sampling a signal, converting said samples into digital values and then performing mathematical operations over said digital values to achieve the desired processing.
In many applications, one has to switch from one sampling rate to another in the course of the process. Assuming the rates are multiples to one another, up sampling may be achieved by interpolating in between consecutive samples, while down sampling would simply require regularly dropping samples. This process does not directly apply to systems wherein sampling rates ratio would not be an integer value or in other words sampling rates relatively prime.
A fairly straightforward solution would be achieved by converting the sampled signal back to analog form and resampling it at proper rate. However, this solution would not only lack efficiency from a processing load standpoint, it might add to the coding error.
An improved method is disclosed in U.S. Pat. No. 4,460,890 wherein direct digital to digital conversion from a first sampling rate to a second sampling rate, not multiple to each other, is achieved using a rate multiplication means feeding an interpolating means.
This solution is still considered rather complex and not cost optimized.
Objects of Invention
One object of this invention is to provide an improved means for converting a sampled signal from one sampling rate to another within one single process.
Another object is to provide a digital filter fed with input samples at a first rate and providing output samples at a second rate, by computing said output samples through permutations of filter coefficient sets in a predetermined order.
Brief Summary of the Invention
A much improved solution to this rate conversion is proposed here, which, instead of focusing on the samples, focuses on the system transfer function. It combines both filtering and interpolation operations into one single operation, i.e. multi rate filtering or interpolating filtering. To that end, the filter impulse response h(t) is sampled at a rate higher than it should normally be; rate multiple of the symbols rate (A=2742.85) and the D/A converter clock rate (B=14,000). The optimal solution is provided by selecting said multiple to be equal to their lowest common multiple, i.e. P=57.6 kHz
Brief Description of the Drawings
Further objects, characteristics and advantages of the present invention will be explained in more detail in the following description with reference to the enclosed drawings which represent a preferred embodiment thereof.
FIGS. 1 and 3 are block diagrams of filters made according to the invention.
FIG. 2 is a flow chart of the filtering process operated with the device of FIG. 1.
Description of Preferred Embodiment
Even though the invention applies to any digital system wherein conversion is to be achieved between input and output sampling rates, the detailed description is given herein with reference to QAM-based digital modems and more particularly to digital filtering used within said modems. For details on said modems, one may refer to:
A. Croisier and J. M. Pierret, "The Digital Echo Modulation", IEEE trans. Communication Technology, COM-18, pp 367-376 (1970).
D. Godard and D. Pilost, "A 2400-Bits/s Microprocessor-Based Modem", IBM journal of Research and Development, Vol. 25, No.1, January 1981, pp 17-24.
More particularly, assume a 19.2 Kbits/s modem is to operate at a symbol rate (baud rate) of 2742.85 symbols/s for transmitting and receiving 7 bits per symbol.
Each symbol is selected within an (X,Y) represented constellation, and therefore is defined by two cartesian components, an and bn. Conventional QAM modulation operations involve carrier modulating (=rotating) the symbol, then convolving (filtering) each selected and modulated symbol by a so called signal element impulse response. Said filter is a complex filter, but one may show that the system is fully defined by the real component r(t).
For a modem operating at the 2472.85 symbols/s rate and assuming the filter impulse response is defined by six samples (coefficients) per baud time, then the filter clock should have a rate of 6.times.2742.85=16457.1 Hz.
According to the conventional modem practice, the filter output is converted into analog form in a D/A converter and then filtered in a low cost, analog, low-pass filter prior to being fed to the transmission line. Naturally, the D/A clock should be rated at 16457.1 Hz.
But assuming one wishes to use a D/A converter clocked at 14400 Hz, the filter output signal S(t) would need resampling properly. Since 14400 and 16457 Hz or 2742.85 Hz are not multiples of each other, the sampling rate conversion operation cannot be achieved in a straightforward manner.
One may interpolate input samples to achieve the rate conversion. But not only does this solution mean additional computing load which might affect the modem signal processor efficiency, it also affects the process precision by adding interpolation noise.
A much improved solution to this rate conversion is proposed here, which, instead of focusing on the samples, focuses on the system transfer function. It combines both filtering and interpolation operations into one single operation, i.e. multi rate filtering or interpolating filtering. To that end, the filter impulse response h(t) is sampled at a rate higher than it should normally be; rate multiple of the symbols rate (A=2742.85) and the D/A converter clock rate (B=14 400). The optimal solution is provided by selecting said multiple to be equal to their lowest common multiple, i.e. P=57.6 kHz since:
when a and b are integer values
(NB=throughout this text, the symbol "." is used to designate a multiplication when no ambiguity may occur with decimals, but where decimals are used, the multiplication symbol will be "x").
For an unchanged filter impulse response length (e.g. 12 symbol intervals long), the total number Np of filter coefficients would be: ##EQU1## Said 252 coefficients are arranged into a 21 sets, herein referenced Set(j) j=0 to 20 of 12 coefficients each. ##STR1##
The multi-rate transmit filter is represented in FIG. 1. It includes a 12 symbol cell long shift register or delay line wherein the symbols S(n) are fed at a rate 1/T=2742.85 Hz. At the current time reference n, the delay line contains the samples Sn, Sn-1, Sn-2, . . . Sn-11. The symbol cells are provided with taps connected to multipliers (not shown), the second inputs of which are assigned a filter coefficient (i.e. filter impulse response sample, according to digital filtering theory). Said coefficients are spaced by T/21 over the impulse response and divided into 21 sets of 12 coefficients. The spacing between the subsequent sets is 4T/21 and corresponds to the output rate.
The coefficient sets are used sequentially. They may be stored in a memory and fetched out when needed. The filter output sample X is computed according to the flow diagram of FIG. 2.
More particularly, when the process is started, i=0 and the first set of coefficients, i.e. Set(0) is fetched out of the storage (not shown). The first filtered sample X(n) is computed:
And a new i value is computed: i=i+4=4. Said i value being less than 21, the filter output sample computation is started again.
i is again incremented to:
i=i+4=24 being larger than 21, i is set to i-21=24-21=3, a new baud time occurred, and a new filter input signal sample Sn+1 is fed into the filter delay line. The new filter output sample X(n+6) is computed:
a new sample Xn+21 is computed.
and so on.
The system keeps going on with switching among the filter sets of coefficients at 14 400 Hz rate (=21/4 T with 1/T=2742.85 Hz while keeping the filter input rate equal to the baud rate of 1/T 2742.85 Hz. In other words, the rate conversion to be achieved, is combined with filtering operation by judiciously rotating the sets of filter coefficients at 14 400 Hz rate to compute a=21 filter output samples every b=4 input samples. As may be seen from above, this implies 6+5+5+5=21 output samples every 4 input samples.
Therefore, the filter sets of coefficients are repetitively permutated in an order defined by:
meaning setting the next i value to (previous i+b) modulo "a" with i being initially set to the index of the first set of coefficients, i.e. i=0. This may be expressed by stating that: ##EQU2## i being the previous coefficient set index, the above operation provides the number of shifts "k" to be applied to the shift register contents and the new set index (inew) for computing the new output sample.
Thanks to this method, the filter input samples are fed into the filter shift register (delay line) at their own incoming rate, while the output samples are computed by switching the filter coefficient sets at the required output rate.
As mentioned, according to digital filtering theory, the filter coefficients are obtained by sampling the desired filter impulse response. The 252 coefficients may be computed accordingly by sampling the original impulse response at the rate of P 57600 Hz. A slightly less precise result may be achieved by performing interpolation operations over the coefficients of a filter originally designed to operate at rate 16457, i.e. coefficients deriving from a filter impulse response sampled at rate 6/T.
The rationale of this invention may be extended to apply to the modem receiver filter. The input samples derived from the received signal are fed into a receive (Hilbert) filter delay line at the rate of 21 samples per 4T which corresponds to a sampling frequency of 14400 Hz. The receive filter issues two complex symbols per time T (or 8 per 4T) which are then fed into a T/2-spaced equalizer delay line. The filter impulse response is sampled at a rate corresponding to the lowest common multiple of twice the symbol rate (2/T) and the A/D sampling frequency.
with K1 and K2 being the lowest integer values verifying the above equation.
Assuming the original impulse response was sampled to provide 54 coefficients over T/6 second, then, the number of coefficients for the multirate receive filter for the same length would be
These coefficients are divided into 8 sets of coefficients corresponding to the 8 symbols generated per 4T. The number of coefficients is reduced to 376 coefficients or 8 sets of 47 coefficients, namely:
A block diagram representation of the receive filter is shown in FIG. 3. The incoming samples are fed into a 47 samples long delay line. After 4T, the sample Sn has been shifted by 21 positions and is stored into Sn-21. The different sets of 47 coefficients each, numbered Set(0) to Set(7), are stored in a memory (not shown). They are used in a specific order such that:
In addition, before each output sample computation, the delay line contents is shifted by a number of samples given by the quotient of the division of the new index by 8.
In other words, assuming the previous set number be i, then i+21=8k+n,then, the new set reference number should equal to n and the number of shifts equals to k.
For instance, lets assume the process starts with feeding the Sn input sample into the filter delay line. The output samples are computed and provided as follows:
Number of shifts=2. Therefore, no output sample is computed when Sn+1 is fed into the filter delay line. Next sample computation X occurs with Sn+2 arrival.
The process starts rescanning the coefficients sets, i.e. Set(0), Set(5), Set(2), Set(7), Set(4), Set(1), Set(6), Set (4), etc. . .
In summary, the algorithm may be expressed by: ##EQU3##
For twenty one input samples, the filter provides eight output samples using the eight sets of coefficients Set(0) through Set(7) in a fixed order defined by the above equation.
Claims
What is claimed is:
1. A digital filter having a predefined impulse response h(t) for filtering an input signal sampled at a rate A into a filtered output signal sampled at a rate B, said filter including a shift register provided with taps, a set of multipliers, each multiplier having one input connected to one of said taps, adding means connected to said multipliers, and storage means for storing filter coefficients to be added to said multiplier inputs, said filter being characterized in that it includes: means for sampling said filter having a predefined impulse response h(t), said sampling being conducted at a rate substantially equal to the lowest common multiple P of A and B, and deriving therefrom Np filter coefficients; means for arranging a number N'p of said coefficients, N'p being substantially equal to Np, into sets of coefficients, Set(i); means for feeding said input signal samples into said shift register at said input rate; and means for fetching sets of filter coefficients in a predetermined order and applying said coefficients to said multipliers at a rate B; whereby the output samples are being generated at said B rate.
2. A variable rate filtering process for filtering a digital signal S(n) representative of an analog input signal, which has been sampled at an input rate A, into an output signal X(x) representative of the filtered analog output said output signal being sampled at a rate B, said filtering being conducted in accordance with the filter impulse response characteristic h(t) defining the considered filtering function, said process including steps of: deriving Np filter coefficients C(i), where i is an integer in the range i=0 to Np-1 corresponding to said impulse response function h(t) of said given filter sampled at a rate P where P is a common multiple of A and B equal to "a" times A and to "b" times B, where "a" and "b" are integers, splitting said Np filter coefficients C(i) into "a" sets S(i) where i is an integer value in the range of 0 to 1-; storing said S(i) coefficient sets; providing a buffer register means; buffering in said buffer register means said input digital samples S(n) of said analog signal sampled at rate A; generating "a" output signal samples while "b" input samples are being fed into the filter, each output sample generation including convoluting said input digital samples, buffered in said buffering step, with a selected coefficient set S(i), i being repetitively permuted in a predefined order while generating consecutive output samples; and, providing said processed output signal samples X(n) as representative of filtered input signal samples S(n) through said filter of given impulse response h(t).
3. A process according to claim 2 wherein A and B are relatively prime.
4. A process according to claim 2 or 3, wherein "a" and "b" are computed for P being the lowest multiple to both A and B.
5. A process according to claim 4 wherein said filter input rate A is higher than output rate B, whereby each output sample computation involves shifting the input samples k positions into a filter having filter impulse response h(t), with k being the quotient of the division of "a" plus previous coefficient set index, by "b".
6. A process according to claim 4, wherein said coefficient set S(i) permutation is obtained by deriving the new set order "i new" from the current set index "i old" using the following relationship: i new=(i old+b) modulo a.
Patent Citations (7)
Non-Patent Literature (2)
- Croisier et al, "The digital Echo Modulation", IEEE Trans. Communication Technology, COM-18, pp. 367-376 (1970).
- Goddard et al, "A 2400-Bits/s Microprocessor-Based Modem", IBM Journal of Research and Development, vol. 25, No. 1, Jan. 1981, pp. 17-24.