Digitally Controlled Delay Circuit

The present invention relates to a circuit for selectively delaying an input trigger signal and more particularly to a delay circuit wherein precise increments of delay are selected in response to a control signal.

A delay circuit is a circuit having an output which is delayed by a prescribed time interval from an applied input. In a variable delay circuit, the time delay between the input signal and the output signal is adjustable, within limits, by the variation of one or more circuit parameters. In general, the variation in time delay is accomplished by the variation in the magnitude of a resistance, a capacitance, or a voltage.

In accordance with the present invention a first inverter circuit is connected between a source of power and a reference potential by a cascade of parallel connected transistors each having a unique resistance when turned on. Each transistor is individually selectable by applying a control signal to its gate. An output circuit, comprised in part, of a second inverter circuit receives and inverts the output from the first inverter circuit to provide the delayed output. The amount of delay is a function of the resistance of the transistor that is turned "on".

From the foregoing it can be seen that a primary object of the present invention is to provide an improved delay circuit.

It is another object of the present invention to provide a delay circuit wherein the amount of delay is a function of the resistance of the transistor that is turned on.

It is yet another object of the present invention to provide a variable delay circuit which is easily cascaded to provide longer delays.

These and other objects of the present invention will become more apparent when taken in conjunction with the following description and drawing in which like characters indicate like parts and which drawing forms are a part of the present disclosure.

FIGS. 1A and 1B are a schematic diagram of the preferred embodiment of the invention.

Referring to FIGS. 1A and 1B, the delay circuit 10 is comprised of a first inverter circuit 20 having an input labeled IN and an output labeled DLY, a source of power V.sub.CC, a reference potential (ground), a cascade 30 of parallel connected transistors and an output circuit 40. The output circuit 40 is connected to the output DLY of the first inverter 20 and provides two outputs, one a buffered delay, DBUF, and the other a delay out, DOUT. One or more of the delay circuits 10 may be cascaded by connecting the DOUT terminal of the first delay circuit 10 to the IN labeled input of the first inverter 20 of a second delay circuit 10.

The first inverter circuit 20 is a CMOS device having a P transistor, Q.sub.3, and an N transistor, Q.sub.4. Next to transistor Q.sub.3 is the labeling P30/2.5 which denotes that transistor Q.sub.3 is a P-type device having a gate width, W, equal to 30 microns and a gate length, L, equal to 2.5 microns. As is well known in the art of MOS design, the magnitude of the drain-source current is a function of the ratio W/L. The type of transistor, N or P, and the associated gate ratio for each of the remaining transistors is shown in the drawings adjacent the transistor.

The control gates of transistors Q.sub.3 and Q.sub.4 are connected to the input terminal IN for receiving the signal that is to be delayed.

The drain of transistor Q.sub.3 is connected to the voltage source V.sub.CC and the drain of transistor Q.sub.4 is placed in circuit to ground through the conductive resistance of transistor Q.sub.20 when the gate of transistor Q.sub.20 is connected to the voltage source V.sub.CC. With the gate ratios shown, and only Q.sub.20 active, the delay for the input signal is 4.07 nano seconds. Each of the transistors Q.sub.5 through Q.sub.19 have gate electrodes labeled DY1 through DY15, respectively. Each input is switchable between a ground potential or the potential V.sub.CC by a control signal. The longest delay is provided when all DY inputs are connected to ground. The shortest intended delay is when DY1 is at the potential V.sub.CC and DY2 through DY15 are grounded.

The output circuit 40 comprises a second inverter circuit having transistors Q.sub.21 and Q.sub.22, which inverts the signal on line DLY and buffers the inverted signal to its output DBUF. The signal on line DLY is also directed to transistors Q.sub.23, Q.sub.24, Q.sub.25 and Q.sub.26, which transistors Q.sub.23, Q.sub.24, Q.sub.25 and Q.sub.26 perform an inverting function along with a reset function that is utilized when two or more delay lines are cascaded for increased delay.

In operation, the conducting resistance of Q.sub.20 draws a certain amount of current from the line DLY when transistor Q.sub.4 is conducting so as to limit the current available to charge/discharge the combined gate capacitance of transistors Q.sub.21, Q.sub.22, Q.sub.24 and Q.sub.25. When another transistor gate DY is activated, the conducting resistance of that transistor is placed in parallel with the conducting resistance of Q.sub.20 thereby lowering the resistance between the drain of Q.sub.4 and ground. The lower resistance increases the current flow through Q.sub.4 thereby increasing the amount of current available for charging/discharging the combined gate capacitance of Q.sub.21, Q.sub.22, Q.sub.24, and Q.sub.25. As is well known, the shorter the time it takes to charge/discharge the gate capacitance of a MOS transistor (such as transistors Q.sub.21, Q.sub.22, Q.sub.24 and Q.sub.25), the shorter the delay in the transistor turning "on" or "off". Conversely, the longer it takes to charge the gate capacitors the longer it will take a properly biased transistor to turn "on" or "off".

The rising edge of an input signal is delayed based on which DY input is activated. The falling edge has a minimal delay.

The DBUF output, taken from the source of Q.sub.21 and the drain of Q.sub.22, provides the delayed timing output of the delay circuit 10.

As previously stated, transistors Q.sub.23, Q.sub.24, Q.sub.25 and Q.sub.26 form an inverter circuit and a means for coupling the output of a first delay circuit 10 to the input of a second delay circuit 10 in order to increase the amount of delay beyond that available with one delay circuit.

The function of transistors Q.sub.23 and Q.sub.26 is to provide a clear signal for clearing the cascaded delay circuit upon receipt of a RESET signal on their gate electrodes. In the absence of the RESET signal transistors Q.sub.24 and Q.sub.25 operate as an inverter and a buffer to invert the signal on the line DLY and to buffer the signal to the next cascaded delay circuit.

While there has been shown what is considered to be the preferred embodiment of the invention, it will be manifest that many changes and modifications may be made therein without departing from the essential spirit of the invention. It is intended, therefore, in the annexed claims, to cover all such changes and modifications that may fall within the true scope of the invention.