Multilayer Wiring Substrate

The present invention relates to a multilayer wiring substrate.

In depositing multiple fine wiring layers over a glass ceramic layer, insulated with a polyimide resin layer, in a conventional multilayer wiring substrate, the adhesion of the polyimide resin layer is strengthened by coating the glass ceramic layer with a silane-based adhesion promoter or the like.

The silane-based adhesion promoter coat, however, by itself cannot provide strong enough adhesion between the glass ceramic layer and the polyimide resin layer. This entails the disadvantage that, along with a growth in the size of multilayer wiring substrates, a stress due to the difference in thermal expansion coefficient between the glass ceramic layer and the polyimide resin layer increases and thereby invites peeling of the polyimide off the glass ceramics.

An object of the invention is, therefore, to provide a multilayer wiring substrate free from the above-mentioned disadvantage of the conventional substrate.

According to an aspect of the invention, there is provided a multilayer wiring substrate which comprises: a glass ceramic section; a wiring layer section having a plurality of wiring layers insulated from each other by a polyimide material; and an intermediate layer made of an inorganic material and arranged between the ceramic section and the wiring layer section.

Other features and advantages of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

FIG. 1 shows a cross-sectional view of a first embodiment of the invention; and

FIG. 2 shows a cross-sectional view of a second embodiment of the invention .

Referring to FIG. 1, a first embodiment of the invention comprises a glass ceramic section 11, gold conductive wiring layers 14 formed within the section 11, a multilayer wiring section 13 formed over the section 11, gold conductive wiring layers 15 formed within the section 13 and insulated from each other by polyimide resin, and a silicon dioxide layer 12 formed between the sections 11 and 13. The layer 12, which is 1 micron thick, functions to ensure a strong adhesion between the glass ceramic and the polyimide resin. Via-holes 16 are formed in the layer 12 to electrically connect the layers 14 in the section 11 and the layers 15 in the section 13.

The layer 12 is formed over the section 11 by, for instance, the plasma CVD method and the via-holes 16 are bored by the reactive ion beam etching technique. The layer 12 may also be formed by a physical vapor depositing method, such as sputtering, and the via-holes 16 are bored by reactive ion etching, wet etching, or lifting off.

Further, what can be used for the layer 12 as an adhesive layer between the glass ceramic of the section 11 and the polyimide resin of the section 13 besides silicon dioxide include aluminum oxide, aluminum nitride, boron nitride or glass ceramic whose composition has been altered specifically to promote adhesion.

If the thermal expansion coefficient of the layer 12 sandwiched between the sections 11 and 13 is between those of the glass ceramic and the polyimide resin, the layer 12 will function not only as an adhesion-promoting layer but also to ease the stress between the two layers of materials differing in thermal expansion coefficient. Among inorganic insulating materials for the layer 12 is ceramic paste whose thermal expansion coefficient can be adjusted with various additives. In order to ensure an adequate functioning of this layer to ease the stress, it is important to so form the layer 12 as not to let the sections 11 and 13 be connected to or come into contact with each other in any peripheral part of the substrate.

Referring now to FIG. 2, in a second embodiment of the invention, a glass ceramic section 21 and a polyimide multilayer wiring section 23 are structured similarly to the counterparts of the first embodiment, and include conductive wiring layers 24 and 25, respectively. Sandwiched between the sections 21 and 23 is a stress-easing layer 22 composed of multilayer plating of gold and palladium.

This stress-easing layer 22 comprises a chromium-sputtered film 1,000 .ANG. thick, a palladium-sputtered film 1,000 .ANG. thick, a gold-plated film 5 .mu.m thick and a palladium-plated film 0.5 .mu.m thick. Between the section 21 and the layer 22, the chromium-sputtered film serves as an adhesive layer, and between the layer 22 and the section 23, the palladium-plated film does. The stress arising from the difference in thermal expansion coefficient between the sections 21 and 23 is eased by the gold-plated film provided in the layer 22.

Via-holes 26 are bored at those portions of the layer 22 electrically connecting the layers 24 in the section 21 and the layers 25 in the section 23.

The whole stress easing layer 22 except the via-holes 26 consists of a layer, only the portions for the via-holes 26 of which are open, or a fine mesh layer and, if connected to the ground potential of a power supply unit, can also be used for the impedance matching of signal wiring layers.

The following metals, besides those used in this embodiment, can be used to compose the stress-easing layer 22: titanium, tungsten or Nichrome sputtering in place of the chromium sputtering; platinum or nickel sputtering in place of the palladium sputtering; copper plating in place of the gold plating; and nickel or chromium plating in place of the palladium plating.

In this embodiment, too, in order to ensure adequate stress easing, it is important to so form the layer 22 as not to let the section 21 and the section 23 be connected to or come into contact with each other in any peripheral part of the substrate.