US 5,103,288 AGrant
Semiconductor Device Having Multilayered Wiring Structure With a Small Parasitic Capacitance
Issue Date:1992-04-07
•11 Claims
•3 Drawing Sheets
Abstract
The semiconductor device of the present invention includes a semiconductor substrate on which are formed semiconductor elements, and a plurality of wiring layers formed on the semiconductor substrate via porous insulating films. The surface of the plurality of the wiring layers is preferably covered with a compact insulating film. The size of the pores in the porous insulating film is preferably 5 nm to 50 nm in diameter, and the volume of the pores in the porous insulating film is preferably 50% to 80% of the total volume of the porous insulating film. The porous insulating film is formed by subjecting a mixed insulating film of a basic oxide and an acidic oxide to a heat treatment to precipitate only either one of the basic oxide and the acidic oxide, and then dissolving out selectively the basic or acidic oxide precipitated.
Metadata
Assignee
- NEC Corporation
Inventors
- Mitsuru Sakamoto
- Kuniyuki Hamano
Application Information
Application Number:US 6776191
Filing Date:1991-03-27
Priority Date:1988-03-15
Art Unit:253
Classifications
IPC:
H01C 1706H01C 700H01L 2188H01L 2928
Field of Search:
35771
Patent Drawings (3 sheets)
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring structure for a semiconductor device, and more particularly to a semiconductor device having a multilayered wiring structure with a small parasitic capacitance.
2. Description of the Related Art
With the view toward establishing a larger scale of integration for semiconductor devices, there are strong demands for development of techniques for making the wiring width and wiring spacing more minute and for multilayering of wirings. Under these circumstances, reduction in the parasitic capacitance of wirings becomes important in the wiring technique together with reduction in the wiring resistance. The reason for this is that the parasitic capacitance increases with the increase in the wiring density or with multilayering of the wirings so that it becomes difficult to diminish the power consumption during dynamic operation of semiconductor elements. Furthermore, the reduction in the parasitic capacitance of wirings brings about an improvement in the speed of signal transmission between semiconductor elements which is effective in increasing the operational speed of semiconductor devices.
In order to reduce the parasitic capacitance, it becomes necessary to reduce the relative dielectric constant of the interlayer insulating film between the multilayered wirings. As such interlayer insulating films, there have been known inorganic insulating films like silicon oxide film as disclosed in "Proceedings of Third International IEEE VLSI Multilevel Interconnection Conference," 1986, pp. 100-106 or in "Proceedings of First International IEEE VLSI Multilevel Interconnection Conference," 1984, pp. 37-44, organic insulating films like polyimide as disclosed in IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 4, 1978, pp. 462-467, and the like. However, since the relative dielectric constant .epsilon. of the former examples is on the order of 3.9 and that of the latter is about 3.0, these insulating films cannot be used as interlayer insulating films which satisfies the condition .epsilon. .ltoreq. 2.0 required for improvement of operating speed.
Besides the above, there is known a wiring technique called aerial wiring. In this technique, wiring is formed in the air without insertion of such an interlayer insulating film between metallic wirings. Although this aerial wiring technique makes it possible to attain approximately the condition of .epsilon. = 1.0, the technique has a drawback in that the wiring metal tends to generate sagging and deformation because of the insufficient supporting portions of the wiring, which causes short-circuiting between the wirings and breaking of the wirings, giving rise the wirings with poor reliability.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device which has a multilayered wiring structure with a small parasitic capacitance.
The semiconductor device in accordance with the present invention includes a semiconductor substrate on which are formed semiconductor elements, and a plurality of metallic wirings formed on the semiconductor substrate, the metallic wirings being formed in a multilayered form with porous insulating films interposed between adjacent wiring layers. Preferably, a porous insulating film is inserted between the metallic wirings as the interlayer insulating material, with the metallic wirings covered with a compact insulating film.
The diameter of the pores of the porous insulating film is preferable to be in the range of 5 to 50 nm, and the volumetric density of the pores of the porous insulating film is preferable to be in the range of 50 to 80%.
Further, the forming process of the porous insulating film preferably includes the steps in which an insulating film which is a mixture of a basic oxide and an acidic oxide is deposited, then only the basic oxide or the acidic oxide is precipitated by a heat treatment, following that, only the basic oxide or the acidic oxide that is precipitated is dissolved. Pores are formed in the portions from which the above-mentioned substance is dissolved.
It is preferable to form the mixed insulating film as a mixture of sodium oxide or calcium oxide and silicon dioxide or silicon dioxide/boron oxide, and it is preferable to have the concentration of sodium oxide or calcium oxide contained in the mixed insulating film to be in the range of 15 to 25 mol %. After preparing the mixture as in the above, sodium oxide or calcium oxide alone is dissolved. In the process of subjecting the mixed insulating film to a heat treatment, it is preferable to set a temperature of the heat treatment in the range of 350.degree. to 500.degree. C.
In the present invention, a porous insulator having a large number of minute pores in an insulating film is used as an interlayer insulating film between the metallic wirings so that it is possible not only to reduce the relative dielectric constant of the interlayer insulating film (to less than or equal to 2) and but also to provide a metallic wiring structure with high reliability.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a longitudinal cross-sectional view of the semiconductor device of a first embodiment of the present invention;
FIG. 2 is a longitudinal cross-sectional view of the semiconductor device of a second embodiment of the present invention;
FIG. 3 through FIG. 8 are longitudinal cross-sectional views for explaining a method of manufacturing the semiconductor device of the first embodiment of the present invention; and
FIG. 9 through FIG. 17 are longitudinal cross-sectional views for explaining a method of manufacturing the semiconductor device of the second embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
(First Embodiment)
As shown in FIG. 1, on a surface of a semiconductor substrate 101 having semiconductor elements formed thereon, these is formed an ionorgamic insulating layer 102 such as silicon oxide film, silicon nitride film or silicon oxynitride film as a passivation film. After forming contact holes in the insulating film 102, a first metallic wiring 103 is formed using pure aluminum, aluminum containing silicon or the like, and a porous insulating film 104 is deposited covering the first metallic wiring 103. Here, the porous insulating film 104 consists of an acidic oxide such as SiO.sub.2, a basic inorganic insulator such as CaO or Li.sub.2 O or an organic insulator such as polyimide with volume density of pores of 50-80%.
Then, after forming a metal 105 in the contact hole by electroless plating or low temperature CVD process, a second metallic wiring 106 is formed using a method similar to that of the first metallic wiring 103. Further, a porous insulating film 104 and a third metallic wiring 107 are formed using means similar to the above, and a metal 105, a fourth metallic wiring 108 and a topmost porous insulating film 104 covering the metallic wiring 108 are formed respectively.
Next, the method of manufacturing the semiconductor device shown in FIG. 1 will further be described in detail. First, as shown in FIG. 3, on the surface of a semiconductor substrate 301 having semiconductor elements formed thereon, there is deposited an inorganic insulating film 302 with two-layer structure of a silicon oxide film and a silicon oxynitride film. Here, the silicon oxide film is formed to have a thickness of about 1000 .ANG. by a CVD method while the silicon oxynitride film is formed to have a thickness of about 3000 .ANG. by a plasma CVD method.
Subsequently, after forming a contact hole 303 using a dry etching method, a first metallic wiring 304 is formed as shown in FIG. 4. The metallic wiring 304 is formed by deposition of pure aluminum metal by sputtering followed by a fine working using dry etching.
Then, a mixed insulating film 305 consisting of sodium oxide (Na.sub.2 O) and silicon oxide (SiO.sub.2) is formed to have a thickness of 5000 .ANG. as shown in FIG. 5. The mixed insulating film 305 is deposited by a CVD method, a coating method or a sputtering method so that the concentration of sodium oxide is in the range of 15 to 25 mol %. As the coating agent, use is made of a mixture of R.sub.1 Si(OR.sub.2).sub.3 or Si(OR.sub.2).sub.4 and NaOH with methyl-cellosolve used as the solvent. In the above, R.sub.1 and R.sub.2 represent hydrocarbon compounds of the form C.sub.m H.sub.n. In the case of formation of the film using the CVD method, deposition is carried out in reaction furnace by mixing SiH.sub.4, N.sub.2 O, NaOH gases or organic silane series gases.
A multilayered wiring is formed by using thus formed mixed insulating films 305 as the interlayer insulating films. The case of building a four-layered metallic wiring is shown as an example in FIG. 6.
After forming a top layer of mixed insulating film as shown in FIG. 7, the mixed insulating film 305 is converted to a porous insulating film 306 as indicated in FIG. 8.
The conversion is carried out as in the following. A semiconductor substrate in the state of FIG. 7 is subjected to a heat treatment at a temperature in the range of 300.degree. to 500 .degree. C. in an inert gas such as nitrogen or an oxidizing atmosphere. As a result of such heat treatment, a phase separation phenomenon in which the mixed insulating film 305 is separated into Na.sub.2 O and SiO.sub.2 takes place, giving rise to a micro-phase separation of "intertwining type" or "droplet type".
Then, by immersing the substrate in an acidic treatment solution such as hydrochloric acid, Na.sub.2 O alone is dissolved and there are formed holes in the portions from which Na.sub.2 O is dissolved out. The size of these pores depends upon that of Na.sub.2 O precipitation at the time of micro-phase separation. Under the conditions of heat treatment described above, there are formed numerous pores with diameter of about 10 nm.
In the above, the case of using the Na.sub.2 O/SiO.sub.2 system which gives rise to a phase separation phenomenon as the mixed insulating film was described. However, similar effect can be obtained by employing other mixed insulating films of a basic oxide/an acidic oxide system which give rise to the phase separation phenomenon such as Li.sub.2 O/SiO.sub.2 system and CaO/SiO.sub.2 system.
Further, in the above embodiment, description was made in the case of carrying out the phase separation of the mixed insulating film 305 by the heat treatment in the last step. However, microphase separation may be introduced in each formation step of the mixed insulating film by providing heat treatment. It should be noted, however, that the dissolution of the precipitated insulator is to be carried out in the final step.
(Second Embodiment)
Referring to FIG. 2, the use of a porous insulating film 205 to be inserted between metallic wirings is analogous to the first embodiment, but a protective insulating film 204 is formed covering the surface of the wiring metals. The protective insulating film 204 is constructed by a compact film with passivation effect such as a silicon oxynitride film of thickness of 100-2000 .ANG. or a silicon nitride film with small stress.
The remaining constitution of the embodiment is the same as that of the first embodiment. Namely, on a semiconductor substrate 201 having semiconductor elements thereon, there is formed an inorganic insulating film 202 with a contact hole to separate the semiconductor substrate 201 from multilayered wiring layers to be laminated on it. Then, metal wiring 203 laminated in the form of a multilayer and porous insulating films 205 serving as interlayer insulating films are formed.
In the case of the present embodiment, wiring reliability can be improved to a large extent by isolating the porous insulating film 205 from the metallic wiring 203 by means of a protective insulating film 204.
Next, the method of manufacturing the semiconductor device shown in FIG. 2 will be described in detail. First, an inorganic insulating film 402 is deposited on the surface of a semiconductor 401 and then a contact hole 403 is formed as shown in FIG. 9.
Next, a first metallic wiring 404 is formed as shown in FIG. 10. Up to this step, things are the same as in the first embodiment.
Then, after forming a polyimide film 405 having a thickness of 5000 .ANG. as an interlayer insulating film as shown in FIG. 11, a second metal wiring is formed on the polyimide film 405 as shown in FIG. 12. The case of a multilayered wirings of four layers is illustrated as an example in FIG. 13.
Next, the polyimide films 405 used as the interlayer insulating films are removed completely by an O.sub.2 plasma treatment as shown in FIG. 14. Then, a protective insulating film 406 is formed using a compact substance such as silicon nitride to cover the metal wiring 404 as shown in FIG. 15. The protective insulating film 406 is deposited by a plasma CVD method to have a thickness in the range of 500 to 1000 .ANG..
Next, as shown in FIG. 16, after forming a mixed insulating film 407 using a mixed insulator of a basic oxide/an acidic oxide which is microphase separable by heat treatment as described in the first embodiment, the mixed insulating films 407 are converted to porous insulating films as shown in FIG. 17.
In this embodiment, the metal wirings are coated with a protective insulator so that there is obtained an effect of improving the reliability of the wirings compared with the first embodiment.
In the foregoing, the first embodiment as well as the second embodiment are described, but it is possible to realize a variety of alterations and additions. For example, pores can be formed easily by mixing in advance 50 mol % or less of alkyl group such as CH.sub.3, C.sub.2 H.sub.5, C.sub.3 H.sub.7 in a basic oxide or an acidic oxide, and then removing the alkyl group by subjecting the product to a heat treatment of 300.degree.-500 .degree. C. The heat treatment in this case will become effective by carrying it out in a vacuum of equal to or smaller than 10 Torr in an atmosphere with a trace of nitrogen or oxygen. Moreover, the reliability of the wirings can be enhanced, for example, by adding a step of removing impurities that are sticking to the side walls of the pores by giving a baking after formation of the porous insulating films, by forming an overall passivation film after formation of a multilayered wiring according to the present methods, and the like.
Claims
What is claimed is:
1. A method of manufacturing semiconductor device comprising the steps of: depositing an insulating film which is a mixture of a basic oxide and an acidic oxide on a semiconductor substrate having semiconductor elements formed thereon; subjecting said mixed insulating film to a heat-treatment; forming a porous insulating film by selectively removing said basic oxide or said acidic oxide; and forming a wiring layer on said porous insulating film.
2. A method of manufacturing semiconductor device comprising the steps of: forming a multilayered wirings using an organic substance as an interlayer insulating film; removing said organic substance; forming a compact insulating film covering the surface of said multilayered wirings; forming next an insulating film which is a mixture of a basic oxide and an acidic oxide between said multilayered wirings; subjecting said mixed insulating film to a heat treatment; and forming a porous insulating film by selectively removing said basic oxide or said acidic oxide.
3. A semiconductor device comprising a semiconductor substrate having semiconductor elements formed therein, an inorganic insulating layer covering said semiconductor substrate, at least one contact hole selectively formed in said inorganic insulating layer to expose at least one part of said semiconductor substrate, first wiring layers selectively formed on said inorganic insulating layer, at least one of said first wiring layers being in contact with said at least one part of said semiconductor substrate via said at least one contact hole, a first porous insulating film formed on said inorganic insulating layer to fill intervals among said first wiring layers and formed on each of said first wiring layers to cover said first wiring layers, second wiring layers selectively formed on said first porous insulating film, and a second porous insulating film formed on said first porous insulating film to fill intervals among said second wiring layers and formed on each of said second wiring layers to cover said second wiring layers, the volume of pores in each of said first and second porous insulating films being in the approximate range from 50% to 80% of the volume of each of said first and second porous insulating films.
4. A semiconductor device as claimed in claim 3, wherein the diameter of the pores of each of said first and second porous insulating films is in the approximate range of 5 nm to 50 nm.
5. The semiconductor device as claimed in claim 3, further comprising third wiring layers selectively formed on said second porous insulating film and a third porous insulating film formed on said second porous insulating film to fill intervals among said third wiring layers and formed on each of said third wiring layers to cover said third wiring layers, the volume of pores in said third porous insulating film being in the approximate range from 50% to 80% of the volume of said third porous insulating film.
6. A semiconductor device comprising a semiconductor substrate having semiconductor elements therein, an inorganic insulating layer covering said semiconductor substrate, at least one first contact hole selectively formed in said inorganic insulating layer to expose at least one part of said semiconductor substrate, first wiring layers selectively formed on said inorganic insulating layer, at least one of said wiring layers being in contact with said at least one part of said semiconductor substrate via said at least one first contact hole, a first porous insulating film formed on said inorganic insulating layer to intervene among said first wiring layers and formed on each of said first wiring layers to cover said first wiring layers, at least one second contact hole selectively formed in said first porous insulating film and said inorganic insulating layer to expose at least another part of said semiconductor substrate, a conductive layer filling said at least one second contact hole in contact with said other part of said semiconductor substrate, second wiring layers selectively formed on said first porous insulating film, at least one of said second wiring layers being in contact with said conductive layer, and a second porous insulating film formed on said first porous insulating film to intervene among said second wiring layers and formed on each of said second wiring layers to cover said second wiring layers, the volume of pores in each of said first and second porous insulating films being in the approximate range from 50% to 80% of the volume of each of said first and second porous insulating films, and each of said first and second porous insulating films having a dielectric constant which is not greater than 2.
7. A semiconductor device as claimed in claim 6, wherein the diameter of the pores of each of said first and second porous insulating films is in the approximate range of 5 nm to 50 nm.
8. A semiconductor device as claimed in claim 3, wherein each of said first and second porous insulating films are made of a material selected from the group of acidic oxides consisting of SiO.sub.2, basic inorganic insulators CaO, Na.sub.2 O, and Li.sub.2 O, and organic insulators polyimide.
9. A semiconductor device as claimed in claim 6, wherein each of said first and second porous insulating films are made of a material selected from the group of acidic oxides consisting of SiO.sub.2, basic inorganic insulators CaO, Na.sub.2 O, and Li.sub.2 O, and organic insulators polyimide.
10. The semiconductor device as claimed in claim 6, further comprising at least one third contact hole selectively formed in said second porous insulating film to expose a part of at least one second wiring layer, an additional conductive layer filling said at least one third contact hole in contact with said part of said at least one second wiring layer, third wiring layers selectively formed on said second porous insulating film, at least one of said third wiring layers being in contact with said additional conductive layer, and a third porous insulating film formed on said second porous insulating film to intervene among said third wiring layers and formed on each of said third wiring layers to cover said third wiring layers, the volume of pores in said third porous insulating film being in the approximate range from 50% to 80% of the volume of said third porous insulating film, and said third porous insulating film has a dielectric constant which is not greater than 2.
11. A semiconductor device comprising a semiconductor substrate having semiconductor elements therein, an inorganic insulating layer covering said semiconductor substrate, at least one contact hole selectively formed in said inorganic insulating layer to expose at least one part of said semiconductor substrate, first wiring layers selectively formed on said inorganic insulating film, at least one of said first wiring layers being in contact with said at least one part of said semiconductor substrate via said at least one contact hole, a first pore-free insulating film formed on each of said first wiring layers, a first porous insulating film formed on said first pore-free insulating film to cover said first wiring layers and intervening among said first wiring layers, second wiring layers selectively formed on said first porous insulating film, a second pore-free insulating film intervening between said first porous insulating film and each of said second wiring layers, a third pore-free insulating film formed on each of said second wiring layers, and a second porous insulating film formed on said third pore-free insulating film to cover said second wiring layers and intervening among said second wiring layers, the volume of pores in each of said first and second porous insulating films being in the range from 50% to 80% of the volume of each of said first and second porous insulating films.
Patent Citations (14)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3906620 | 1975-09-01 | Anzai et al. | |
| US4460666 | 1984-07-01 | Dinkler et al. | |
| US4582575 | 1986-04-01 | Warren et al. | |
| US4734754 | 1988-03-01 | Nikawa | |
| US4751136 | 1988-06-01 | Kamiya et al. | |
| US4761677 | 1988-08-01 | Sasaki | |
| US4834034 | 1989-06-01 | Herndon et al. | |
| US4866009 | 1989-09-01 | Matsuda | |
| US4946709 | 1990-08-01 | Takada et al. | |
| JPX55-95857 | 1980-07-01 | ||
| JPX57-99756 | 1982-06-01 | ||
| JPX113252 | 1982-07-01 | ||
| JPX58-182546 | 1983-10-01 | ||
| JPX61-10757 | 1986-01-01 |
Non-Patent Literature (3)
- "Proceedings of Third International IEEE VLSI Multilevel Interconnection Conference", 1986, pp. 100-106.
- "Proceedings of First International IEEE VLSI Multilevel Interconnection Conference", 1984, pp. 37-44.
- IEEE Journal of Solid-State Circuits, vol. SC-13, No. 4, 1978, pp. 462-467.