High Speed Low Power DC Offsetting Circuit

This invention relates to the general subject of electronic circuits and, in particular, to the subject of amplifier circuits used to sum a high speed, DC coupled signal and a low speed high level DC coupled signal.

Amplifier design is a study in compromise. Often a single device can't achieve optimal speed, drift, bias-current, noise, and output-power specs. Although various devices emphasizing one or more of these areas have evolved, those skilled in the art often find that the required performance can only be obtained with a dedicated amplifier design. Moreover, if a single device can't provide the desired characteristics (high speed and DC precision, for example), those skilled in the art can often configure a composite amplifier to do the job. Composite designs combine the best features of two or more amplifiers to achieve a level of performance unobtainable in a single device. Williams, "Composite Amplifiers Yield High Speed and Low Offset", EDN, Jan. 22, 1987.

One frequently occurring problem is that of DC coupling signals, such as in FM modulators and phase-locked loops. Heretofore, at least three techniques have been used. One technique is based on floating the power supplies of wideband, DC-coupled amplifiers so as to overcome their limited offset voltage range. Another technique is based on summing a high-speed, low level signal with a low-speed, high level signal by converting the former to a current, and dropping this current across a resistor, one end of which is connected to the high level signal. Still another technique is to conventionally sum the signals with a summing amplifier of combined high frequency capability.

Clearly a single amplifier design is preferred to a composite design. Not only are the number of parts reduced but often the size is reduced. Single component designs also offer the potential for reduced costs due to economies of scale. Since the problem of DC-coupling a high speed signal and a low speed signal has applicability to the transmission of video information, a single amplifier design would have great utility to the industry.

One object of the present invention is to disclose a circuit for summing a high speed DC-coupled signal with a low speed high level DC-coupled signal.

Another object of the invention is to disclose an improved low power summing circuit having a high voltage range and a wide frequency response.

Yet another object of the invention is to disclose a circuit which allows one to use a low power, limited voltage range video amplifier in conjunction with low power, low frequency, high voltage range capable components to achieve a net power and complexity decrease.

Still another object of the invention is to disclose a circuit for combining a low-speed, high DC level signal with a high-speed, low DC signal to produce an output signal having the dc range of low speed circuitry and the frequency response of high speed circuitry.

Another object of the invention is to provide a low cost, cool running summing circuit.

In accordance with the present invention a high speed, low power DC-offsetting circuit is disclosed. The circuit comprises: an amplifier having an inverting input, a non-inverting input which is adapted to be connected to a high speed low DC voltage source and having an amplifier output; a current source which is connected to said inverting input and through a feedback resistor to said amplifier output; and capacitor means and resistor means, connected in series with each other at a circuit output node, for connecting said non-inverting input to said amplifier output.

The high-speed low power DC offset circuit adds a DC and low frequency signal to a high speed dc-coupled one. The circuit uses an amplifier in a unity or low gain connection to accomplish this. One unique feature is that the high speed signal passes through two paths to the output, one of which carries DC to some moderate break frequency, while the other carries frequencies from the break frequency to an upper limit which can be made arbitrarily high through appropriate component selection. These two paths cross over such that the frequency magnitude response and group delay are essentially flat from DC to the upper limit imposed externally of the offset circuit.

Some of the advantages of the disclosed circuit design include its simplicity, and its small size. Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention, the embodiment described therein, from the claims, and from the accompanying drawings.

FIG. 1 is an electrical schematic diagram of the circuit that is the subject of the present invention;

FIG. 2 is an equivalent DC circuit;

FIG. 3A is an equivalent AC circuit;

FIG. 3B is an ideal circuit equivalent of the circuit of FIG. 3A;

FIGS. 3C and 3D are simplified circuits for analysis of the circuit of FIG. 3B by superposition;

FIG. 4 is an electrical schematic diagram of the invention employed as a variable offset summer;

FIG. 5 is an electrical schematic diagram of the invention employed as a fixed offset summer;

FIG. 6 is an electrical schematic diagram of the invention when used with a resistive load; and

FIGS. 7A and 7B are equivalent AC circuits for the amplifier of FIG. 6

While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail several specific embodiments of the invention. It should be understood, however, that the present disclosure is to be considered an exemplification of the principles of the invention and is not intended to limit the invention to any illustrated specific embodiment.

One unique feature of the invention is that it allows one to combine a low-speed, high DC level signal with a high-speed low DC signal to produce a signal with DC range of low speed circuitry and the frequency response of high speed circuitry. This combining occurs with a frequency crossover effect which adds no distortion.

To understand how this is accomplished, consider the circuit 10 of FIG.1. An ideal differential voltage amplifier and an open circuit load are assumed. First, the DC response alone will be determined. FIG. 2 shows the DC equivalent circuit. The network equations are:

where Vi is a high-speed low DC signal and V.sub.-- is a low-speed high DC level signal.

where l.sub.os is a current source and R.sub.F is the feedback resistance. Therefore: ##EQU1## and as A gets very large:

Since the voltage l.sub.os R.sub.F can be large irrespective of the voltage level capability of Vi, the circuit can sum a high level DC offset with the fast signal Vi.

Next consider the circuits' AC operation. FIG. 3A shows the AC equivalent circuit. FIG. 3B is the equivalent based on the ideal amplifier assumption. By inspection of FIGS. 3C and 3D: ##EQU2## This is the transfer function of the AC equivalent circuit.

This figure explains the origin of the crossover effect. Since the highpass and lowpass paths both have the same break frequency w=1/RC, the overall transfer function is flat. One can also see that the characteristics of an ideal differential voltage amplifier are provided up to and including the crossover frequency; however those characteristics are not needed at the higher frequencies where low-DC-range-capable buffer amplifiers can operate. Well above the break frequency, the offset summer circuit has no effect other than gain reduction due to C's reactance, which eventually becomes inductive and large relative to the load. By adding high frequency capacitors in parallel to C, as required, this effect is made negligible. At frequencies much higher than the differential amplifiers' operating range, the uncontrolled output impedance of the differential amplifier is isolated from the load by the resistor R.

FIG. 4 shows one practical embodiment of a variable offset summer which incorporates the teachings of the present invention. FIG. 4 also includes some design considerations which follow in a straightforward manner from the topology. R1 reduces peaking of the video amp 20 caused by the capacitive load C1. R2 balances the op amp 22 input offset voltage component due to input bias current. R2 also isolates the input capacitance of the op amp 22 from the high speed video amplifier 20. This is useful when C1 is small. C3 filters the high frequency digital-to-analog converter 24 noise. A DAC-.phi.8 is a representative bipolar digital to analog converter 24.

FIG. 5 shows another embodiment of the invention when used as a fixed offset summer. This circuit has a 0 to +10 volt adjustment range and, in one test, showed DC to 70 MHz bandwidth in conjuction with a low power video amplifier, while driving a capacitive load of approximately 30 pF.

FIG. 6 shows a version of the circuit for use with resistive loads. The current source or sink connected to the inverting input of the amplifier provides the voltage offset. A summary AC analysis follows from FIGS. 7A and 7B. Specifically, from FIG. 7A: ##EQU3## This proves that frequency response can be made flat by selecting R2 and R1 for the gain to cancel the loss caused by the R.sub.L /R divider.

From the foregoing description, it will be observed that numerous variations, alternatives and modifications will be apparant to those skilled in the art. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. Various changes may be made, materials substituted and separate features of the invention may be utilized. For example, although a monolithic differential amplifier was illustrated in the drawings, the principles of the invention are equally applicable to monolithic operational amplifiers, hybrid operational amplifiers and video amplifiers, current-feedback amplifiers, and discrete component implementations of a differential amplifier. Thus, it will be appreciated that various modifications, alternatives, variations, etc., may be made without departing from the spirit and scope of the invention as defined in the appended claims. It is, of course, intended to cover by the appended claims all such modifications which are within the scope of the claims.