Manufacturing Method of Semiconductor Devices

1. Field of the Invention

This invention relates to a manufacturing method of semiconductor devices, and more particularly to a manufacturing method of semiconductor devices having lateral bipolar transistors with an SOI (Silicon on Insulator) structure, which are hereinafter referred to as BIP elements.

2. Description of the Related Art

Since lateral BIP elements formed on SOI films have a low stray capacity, they are expected to operate faster than those formed on bulk silicon substrates. Examples of such elements are disclosed in an article by J. C. Sturm et al., IEEE, EDL-8, No. 3, p. 103, 1987. A manufacturing sequence of a conventional BIP element of this type is shown in FIGS. 1A through 1D.

First, an SiO.sub.2 film 2 and a p-type SOI film 13.sub.1 are formed on an Si substrate 1. The p-type SOI film surface undergoes the implantation of boron ions and annealing to convert the surface layer of the p-type SOI film 13.sub.1 into a p-type high-concentration impurity layer (p.sup.+ -type layer). In this way, the p-type impurity layer (p-type layer)13.sub.2 and p.sup.+ -type layer 13.sub.3 are formed. After a CVD oxide film is deposited on the p.sup.+ -type layer 13.sub.3 to form a resist film pattern 15.sub.1 that covers a predetermined region of the CVD oxide film, with the resist film pattern 15.sub.1 as mask, the CVD oxide film is selectively etched to form a CVD oxide film pattern 14.sub.1. (FIG. 1A)

Then, with the resist film pattern 15.sub.1 as mask, the exposed p.sup.+ -type layer 13.sub.3 is etched to form a p.sup.+ -type region 13.sub.5. The p-type layer 132 is also partly etched in the direction of thickness. After the resist film 15.sub.1 is removed, another resist pattern 15.sub.2 is formed on the CVD oxide film pattern 14.sub.1 and a predetermined region of the p-type layer 13.sub.2. By using the resist pattern 15.sub.2 as mask, the p-type layer 132 undergoes selective etching to form an island p-type region 13.sub.6. (FIG. 1B)

After the resist pattern 15.sub.2 is removed, by using the CVD oxide film pattern 14.sub.1 as blocking mask, the p-type region 13.sub.6 undergoes the ion implantation of n-type impurities such as arsenic ion and annealing, which forms an n-type high-concentration impurity region (hereinafter, referred to as an n.sup.+ -type region) 17, an n.sup.+ -type region 18, and a p-type region 13 that is the remaining portion of the p-type region 13.sub.6. (FIG. 1C)

After an interlayer insulating film 111 is deposited and necessary contact holes are made therethrough, interconnections 10 are formed which each make ohmic contact with the individual impurity regions. Then, a passivation film 11.sub.2 is formed to complete an n-p-n lateral BIP element. Here, the emitter portion is indicated by E, the base portion by B, and the collector portion by C. In the BIP element, the p-type region 13 is an internal base region and the p.sup.+ -type region 135 is an external base region. An n.sup.+ -type region 17 that meets the left side of the internal base region 13 is the emitter region and an n.sup.+ -type region 18 that meets the right side of the internal base region 13 is the collector region. (FIG. 1D)

The SOI lateral BIP element produced by the aforementioned method, however, does not provide high performance as expected because of the following problems: first, the withstand voltage decreases significantly, and second, the long transit time of carriers in the base region impairs the high-frequency characteristics, such as cut-off frequency.

The cause of the decreased withstand voltage lies in the fact that a high electric field is apt to develop at the junction between the base region and the collector region. More specifically, when ion implantation is performed on the p-type region 13.sub.6, the sidewalls of the p.sup.+ -type region 13.sub.5 and p-type region 13.sub.6 are also liable to be affected by doping of the n-type impurities. This also forms the highly doped n.sup.+ -type regions 17.sub.2 and 18.sub.2 on the sidewalls as shown in FIG. 2, which creates a highly doped p-n junction with respect to the external base region 13.sub.5. With the base-collector junction applied with the reverse bias, formation of such a highly doped p-n junction decreases the base-collector withstand voltage.

The long transit time of carriers in the base region is ascribed to the uniformity of the impurity concentration profile parallel with the substrate surface in the base region, which results in the poor transport factor of carriers in the base region. The poor transport factor results from the fact that with the above-described method, it is impossible to give a desired impurity concentration profile to the p-type region 13 of the base region because of its structure.

A major object of the present invention is to provide a manufacturing method of semiconductor devices with which lateral BIP elements can be formed which not only operate very fast with a short transit time of carriers in the base region, but also have an excellent base-collector withstand voltage.

Another object of the present invention is to provide a method that enables BIP elements with the foregoing excellent characteristics and insulated-gate field-effect transistors such as MOSFETs to be formed on the same substrate with good compatibility.

The foregoing major object is accomplished by a manufacturing method comprising: a first step of forming on the surface of an insulating substrate a semiconductor layer composed of a semiconductor layer of a first conductivity type on which a high-concentration semiconductor layer of the first conductivity type is formed; a second step of forming an insulating film pattern that covers a prospective external base region of the high-concentration semiconductor layer of the first conductivity; a third step of leaving the high-concentration external base region of the first conductivity type just under the insulating film pattern by selectively etching the high-concentration semiconductor layer of the first conductivity type over the entire film thickness and then selectively etching the semiconductor layer of the first conductivity type over part of the film thickness with the insulating film pattern as mask, and at the same time, forming a thicker prospective internal base region just under the external base region and thinner portions on both side of the prospective internal base region; a fourth step of forming an island element region by leaving only a prospective emitter region and prospective collector region that are located on both sides of the prospective internal base region and have steps between these prospective emitter and collector regions and the prospective internal base region through selective etching of the thinner portions of the semiconductor layer of the first conductivity type; a fifth step of forming a sidewall insulating film that covers at least the sidewalls on the prospective collector region side among sidewalls of the external base region and sidewalls at the steps of the prospective internal base region adjoining the sidewalls of the external base region; and a sixth step of forming the emitter region and collector region of a second conductivity type in the prospective emitter region and collector region, respectively, and the internal base region of the first conductivity type between the emitter and collector regions by highly doping impurities of the second conductivity type into the island element regions through ion implantation perpendicular to the substrate with the insulating film pattern covering the external base region and the sidewall insulating film as blocking mask.

The other object is accomplished by a manufacturing method comprising: a first step of forming on the surface of an insulating substrate a semiconductor layer composed of a semiconductor layer of a first conductivity type on which a high-concentration semiconductor layer of the first conductivity type is formed; a second step of forming an insulating film pattern that covers a prospective external base region of the high-concentration semiconductor layer of the first conductivity; a third step of leaving the high-concentration external base region of the first conductivity type just under the insulating film pattern by selectively etching the high-concentration semiconductor layer of the first conductivity type over the entire film thickness and then selectively etching the semiconductor layer of the first conductivity type over part of the film thickness with the insulating film pattern as mask, and at the same time, forming a thicker prospective internal base region just under the external base region and thinner portions on both sides of the prospective internal base region; a fourth step of forming a first island element region for a BIP element by leaving a prospective emitter region and prospective collector region that are located on both sides of the prospective internal base region and have steps between these prospective emitter and collector regions and the prospective internal base region through selective etching of the thinner portions of the semiconductor layer of the first conductivity type, and at the same time, forming a second island element region for an insulated-gate field effect transistor; a fifth step of forming a gate electrode via a gate insulating film on a prospective channel-forming region in the second island element region for an insulated-gate field effect transistor; a sixth step of forming a first sidewall insulating film that covers at least the sidewalls on the prospective collector region side among sidewalls of the external base region and sidewalls at the steps of the prospective internal base region adjoining the sidewalls of the external base region, and at the same time, forming a second sidewall insulating film covering sidewalls of the gate electrode; and a seventh step of forming the emitter region and collector region of a second conductivity type in the prospective emitter region and collector region, respectively, and the internal base region of the first conductivity type between the emitter and collector regions and at the same time, forming a channel-forming region of the first conductivity type just under the gate electrode in the second island element region, and also forming the source region and drain region of the second conductivity type separated from each other on both sides of the channel-forming region, by highly doping impurities of the second conductivity type into the first and second island element regions through ion implantation perpendicular to the substrate with the insulating film pattern covering the external base region, the gate electrode, and the first and second sidewall insulating films as blocking mask.

In those manufacturing methods, field-effect transistors are formed simultaneously together with the lateral BIP transistors.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIGS. 1A through 1D are sectional views each illustrating the individual processes in a conventional manufacturing method of BIP elements;

FIG. 2 is a sectional view of a typical BIP element produced by a conventional method;

FIGS. 3A through 3G are sectional views each illustrating the individual processes in a manufacturing method of semiconductor devices according to the present invention;

FIG. 4 is a plan view of a semiconductor device produced by a method according to the present invention;

FIG. 5A is a sectional view taken along line a--a' of the FIG. 4 semiconductor device, FIG. 5B a sectional view taken along line b--b' of the FIG. 4 semiconductor device, and FIG. 5C a sectional view taken along line c--c' of the FIG. 4 semiconductor device;

FIG. 6A is an impurity concentration profile of a cross section of a BIP element in a semiconductor device of the sectional structure in FIG. 5A; FIG. 6B an impurity concentration profile of a cross section of a BIP element produced by a conventional method; and FIG. 6C an impurity concentration profile of a cross section of a MOSFET in a semiconductor device of the sectional structure in FIG. 5A; and

FIG. 7 is a sectional view of a semiconductor device of a complementary BiCMOS structure produced by a method according to the present invention.

An embodiment of a manufacturing method according to the present invention will be explained, referring to FIGS. 3A through 3G, FIG. 4 and FIG. 5. The embodiment relates to the method of simultaneously manufacturing n-p-n BIP elements and MOS field-effect transistors (MOSFETs), or a manufacturing method of BiCMOS's.

First, oxygen ions are implanted into a p-type single-crystal Si substrate 1 at an acceleration voltage of 180 kV at a dose of 2.times.10.sup.18 cm.sup.-2 to dope oxygen a specified thickness of the Si substrate 1. Annealing is then performed at 1300.degree. C. for 20 hours to cause the doped oxygen to react with silicon to form a 4000.ANG. of SiO.sub.2 layer 2, on which an SOI film 33.sub.1 of a thickness of 2500.ANG. is left. In this way, what is called an SOI substrate is obtained. (FIG. 3A).

Although in the embodiment, an Si substrate is used as semiconductor substrate, other IV-group semiconductors, such as Ge and C and compound semiconductors, such as SiGe, GaAs, and InP may be used.

An SOI substrate of the same structure as described above may be formed by the following method: a CVD--SiO.sub.2 layer 2 is formed on the Si substrate 1; then after polysilicon is deposited on the SiO.sub.2 layer 2, the polysilicon layer is converted into a single crystal layer in liquid or solid phase to form an SOI film 33.sub.1. In this case, instead of the Si substrate 1, an insulating single crystal substrate such as sapphire or spinel may be used.

Then, after boron ions are implanted in the SOI film 33.sub.1 at an acceleration voltage of 50 kV at a dose of 2.times.10.sup.11 cm.sup.-2, annealing is performed for two hours to convert the entire SOI film 33.sub.1 into a p-type region 33.sub.2 with an impurity concentration of approximately 10.sup.17 cm.sup.-3. Additionally, after boron ions are implanted at an acceleration voltage of 30 kV at a dose of 3.times.10.sup.15 cm.sup.-2, annealing is performed for two hours to form a p.sup.+ -type region 333 at the surface of the p-type region 33.sub.2. Then, after a CVD oxide film with a thickness of 4000.ANG. is formed on the p.sup.+ -type region 33.sub.3, a resist film pattern 35 is formed on a prospective base region of a BIP element. With the resist film pattern 35, as etching resistant mask, the CVD oxide film is selectively etched by reactive ion etching techniques to leave an oxide film pattern 34.sub.1. (FIG. 3B)

Next, of the p.sup.+ -type region 33.sub.3, only the region just under the oxide film pattern 34.sub.1 is left by selective etching to form a p.sup.+ -type external base region 33.sub.5. At the same time, the surface layer of the p-type region 33.sub.2 is also etched away to leave a p-type region 33.sub.4 with a thickness of 1000.ANG.. (FIG. 3C)

After this, the resist film pattern 35.sub.1 is removed and resist film patterns 35.sub.2 and 35.sub.3 are newly formed. The resist film pattern 35.sub.2 covers the oxide film pattern 34.sub.1 and p.sup.+ -type external base region 33.sub.5 as well as the p-type region 33.sub.4 at the portion just under the external base region, i.e. a prospective internal base region, and at the specified portions on both sides of the prospective internal base region, i.e. a prospective emitter region and prospective collector region. The resist film pattern 35.sub.3 covers the predetermined region in which a MOSFET is to formed. With these resist film patterns 35.sub.2 and 35.sub.3 as mask, selective etching is performed to form island element regions 33.sub.6 and 33.sub.7. The island element region 33.sub.6 corresponds to a BIP element portion and the island element region 33.sub.7 to a MOS element portion. (FIG. 3D)

Then, after the resist film patterns 35.sub.2 and 35.sub.3 are removed, the prospective collector region side of the BIP element portion is covered with a resist film 35.sub.4 and the MOS element portion is covered with a resist film 35.sub.5. By using these resist films as blocking mask, boron ions are diagonally implanted in the substrate, for example, at a tilt angle of 45.degree. to the substrate, at an acceleration voltage of 50 kV at a dose of 1.times.10.sup.13 cm.sup.-2 to form an ion implantation layer 36 just under the external base region 33.sub.5 in the island element region 33.sub.6. The implantation angle must be adjusted so as not to cause channeling due to implantedions. It is desirable to implant ions at angles ranging from 20.degree. to 80.degree. with respect to the substrate surface. In this case, by rotating the Si substrate 1 during ion implantation, ions may be implanted into the BIP element portion arranged in various directions. (FIG. 3E)

Next, oxide films 41.sub.1 and 41.sub.2 are formed at the BIP element portion and MOS element portion, respectively. Then, after the deposition of boron-doped polysilicon film, patterning is made to form a gate electrode 34.sub.2 on the specified region of the island element region 33.sub.7 for the MOSFET. Following this, phosphorus ions are almost vertically implanted into the substrate 1 at an acceleration voltage of 50 kV at a dose of 1.times.10.sup.13 cm.sup.-2 . This forms a p-type internal base region 33.sub.9 having the ion implantation layer 36 just under the external base region 33.sub.5 and n.sup.- -type regions 37.sub.1 and 38.sub.1 on both sides of the internal base region 33.sub.9 in the BIP element portion. At the same time, in the MOS element portion, a channel-forming region 33.sub.8 is formed below the gate electrode 34.sub.2 and n-type low-concentration diffused layers (n.sup.- -type regions) 39.sub.1 and 40.sub.1 are formed on both sides the channel-forming region 33.sub.8. (FIG. 3F)

Then, on the surfaces of the BIP element portion and the MOS element portion, a CVDSiO.sub.2 film is formed to a thickness of 2000.ANG.. After this, by performing reactive ion etching on the SiO.sub.2 film, sidewall SiO.sub.2 films 41.sub.3 and 41.sub.4 are formed on the sidewalls of the external base region 33.sub.5 and the sidewalls at the step portions the internal base region 33.sub.9 adjoining the sidewalls of the external base region 33.sub.5, and at the same time, a sidewall SiO.sub.2 film 41.sub.5 is also formed on the sidewalls of the gate electrode in the MOS element portion. Arsenic ions are then vertically implanted into the substrate 1, at an acceleration voltage of 60 kV at a dose of 3.times.10.sup.16 cm.sup.-2, followed by an hour of annealing at 900.degree. C. During the ion implantation, the oxide film pattern 34.sub.1, gate electrode 34.sub.2, and sidewall SiO.sub.2 films 41.sub.3, 41.sub.4, and 41.sub.5 function as blocking mask.

In this way, in the BIP element portion, an n.sup.+ -type collector region 37.sub.2 and emitter region 38.sub.2 are formed on both sides of the internal base region 33.sub.9, which is separated from the former by thin n.sup.- -type region 37.sub.3 and 38.sub.3. It is preferable, however, that the thin n.sup.- -type region 38.sub.3 is also converted to p-type region by B.sup.+ -ion implantation for foming the ion implantation layer 36, in view of enhancing emitter injection efficiency. In the MOS element portion, an n.sup.+ -type source region 39.sub.2 and drain region 40.sub.2 are formed on both sides of the channel-forming region 33.sub.8, which is separated from the former by thin n.sup.- -type regions 39.sub.3 and 40.sub.3. That is, in the MOS element portion, a LDD (Lightly-Doped-Drain) region intervenes between the channel-forming region and drain region. (FIG. 3G)

Next, after deposition of a CVDSiO film 42.sub.1 as inter layer insulating film or a BPSG film, aluminum interconnection 50 are made in a known manner and finally a passivating PSG film 42.sub.2 is deposited. This completes the lateral BIP element and MOSFET having the planar structure of FIG. 4 and the sectional structure of FIG. 5A (the sectional structure taken along line a--a' of FIG. 4). FIG. 5B is a sectional view taken along line b--b' of FIG. 4 and FIG. 5C is a sectional view taken along line c--c' of FIG. 4.

A semiconductor device according to the present invention produced in the above embodiment may have a planar structure other than the planar structure of FIG. 4 where in the BIP element portion, the base region (the external base region 335) has an extended portion perpendicular to the direction running from the collector region 37.sub.2 to the emitter region 38.sub.2 and extending outside these two regions. However, the base region of the BIP element with the structure as shown in FIG. 4 is preferable because the collector region 37.sub.2 is completely separated from the emitter region 38.sub.2. To obtain such a base region, when the island region 33.sub.6 of FIG. 3D is formed, the island region is shaped into the outward form of the BIP element of FIG. 4.

In a semiconductor device having a BIP element and MOSFET of the sectional structure of FIG. 5A, the channel-forming region 33.sub.8 of the MOSFET, the emitter region 38.sub.2, and collector region 37.sub.2 of the BIP element must all have the same film thickness (t.sub.0) and it is desirable that they meet the following empirical formula (1): ##EQU1## where .phi.F is the Fermi level of semiconductor, q the charge of electron, N.sub.A the impurity concentration of semiconductor, and .epsilon. the permittivity.

It is desirable that the relationship between the thickness T of the internal base region 33.sub.9 and t.sub.0 meets the following formula (2):

where 100.ANG. .ltoreq. t.sub.0 .ltoreq.3000.ANG.

Since t.sub.0 thinner than 100.ANG. causes h.sub.EF to drop, a semiconductor element according to this invention is not suitable for LSI switching elements. When t.sub.0 exceeds 3000.ANG., the characteristics of the element becomes more like those of transistors formed on bulk Si substrates, which prevents high speed operation characteristic of a SOI thin film.

It is desirable that the width W of the base region is t.sub.0 or less.

In the aforementioned manufacturing method of semiconductor devices, the most notable feature is that the sidewall SiO.sub.2 film 41.sub.3 is formed on the sidewalls of the external base region 33.sub.5 and the step portion of the internal base region 33.sub.9 as shown in FIG. 3G. Compared with the SiO.sub.2 films 41.sub.4 and 41.sub.5 formed in the same manner, the SiO.sub.2 film 41.sub.3 similarly protects part of the n.sup.- regions 37.sub.1, 38.sub.1, 39.sub.1, and 40.sub.1 from ion implantation of arsenic as shown in FIG. 3G, and then leaves the thin n.sup.- regions on both sides of the channel-forming region 33.sub.8 and at least the collector region 37.sub.2 side of the internal base region 33.sub.9. In addition to this, the SiO.sub.2 film 41.sub.3 has a unique function of protecting the p.sup.+ -type region at the sidewall of the external base region 33.sub.5 and the p-type region of the sidewall at the step portion of the internal base region 33.sub.9 adjoining the sidewall of the external region 33.sub.5 on the n.sup.- region 37.sub.1 side. That is, the SiO.sub.2 film 41.sub.3 can prevent the p-type region and p.sup.+ -type region from becoming n.sup.+ regions due to ion implantation of arsenic. As a result, in the BIP element of FIG. 5A, a decrease in the withstand voltage between the internal base region 33.sub.9 and collector region 37.sub.2 can be prevented.

When the finally formed BIP element has a base extended region 43.sub.5 as shown in FIG. 4, it is desirable to prevent the formation of an n.sup.+ region by forming a mask 43.sub.52 in the base extended region 43.sub.5 to protect the region 43.sub.5 from ion implantation of arsenic shown in FIG. 3G. This makes the separation of the collector region 37.sub.2 and emitter region 38.sub.2 more reliable.

In the above embodiment, the formation of the n.sup.- -type regions 37.sub.1, 38.sub.1, 39.sub.1, and 40.sub.1 by ion implantation of phosphorus are not necessarily required. That is, the regions 37.sub.2, 38.sub.2, 39.sub.2, and 40.sub.2 (n.sup.+ -type) of FIG. 3G may be directly formed by implanting impurity ions via the island element regions 33.sub.6 and 33.sub.7 (p-type) of FIG. 3E. As described above, by forming the n.sup.+ -type region by ion implantation via the SiO.sub.2 film after the formation of the n.sup.- -type region, the thin n.sup.- -type regions are formed on both sides of the p-type inner base region in the BIP element portion, and an LDD structure is constructed in the MOS element portion as shown in FIG. 5A. In the BIP element, however, it is preferable that the thin n.sup.- -type region 38.sub.3 is also converted to p-type region together with forming the p-type inner base region by B.sup.+ -ion implantation, in view of enhancing emitter injection efficiency. In the BIP element, the generation of avalanche breakdown due to a high electric field at the junction between the base region 33.sub.9 and collector region 37.sub.2 is reduced, thereby preventing a decrease in the open-base emitter-collector withstand voltage (V.sub.ECD) Thus, it is desirable to form the n.sup.- -type region 37.sub.3 of FIG. 3G. The formation of such an n.sup.- -type region between the base and collector regions has also been found in BIP elements of a vertical structure. In lateral BIP elements as formed in the embodiment, however, such an n.sup.- -type region can be formed as thin as on the order of 1000 to 2000.ANG. with the thickness controllability of nearly +10%, compared with vertical-structure BIP elements. Therefore, the thin n.sup.- -type regions of BIP elements formed according to the present invention are very effective.

FIG. 6A shows an impurity concentration profile of a BIP element cross section in a semiconductor device with a sectional structure similar to that of FIG. 5A in connection with the embodiment. In this semiconductor device, the thin n.sup.- -type region does not intervene between the base region and the emitter region. For comparison's sake, FIG. 6B shows an impurity concentration profile of a cross section of a conventional BIP element having the sectional structure of FIG. 1D. As seen from these figures, in the BIP element of the embodiment, an n-type region of lower concentration than the collector region is formed between the base region and collector region. Additionally, in the BIP element of the embodiment, the impurity concentration in the base region is lower on the side of the collector region, decreasing gradually from the emitter region toward the collector region. This structure is formed by tilted ion implantation as shown in FIG. 3E.

FIG. 6C illustrates an impurity concentration profile of the MOSFET cross section formed together with the BIP element in the embodiment. As seen from the figure, an LDD structure is formed with a low-concentration impurity layer intervening between the source-drain region and channel- region.

As noted above, with the semiconductor device formed according to the above embodiment of the present invention, particularly the BIP element, the increased withstand voltage between the base region and collector region, the increased emitter-collector withstand voltage voltage, and the formation of the impurity concentration profile of the base region increase the transport factor of carriers in the base region, or shortens the transit time of carriers, thereby improving the high-frequency characteristics, such as cut-off frequency. Thus, a manufacturing method according to this invention enables the formation of lateral BIP elements that operate at a very high speed.

While in the embodiment, BIP elements and MOSFETs are formed simultaneously in a semiconductor element, only BIP elements of the same characteristics may be formed. With BIP elements only, power consumption increases significantly as more elements are integrated, which may result in a serious problem. Since heat dissipation is poor on the SOI film, this makes the power consumption problem much worse. Therefore, it is desirable to mix BIP elements and CMOSFETs on a substrate because the combination of them greatly reduces the overall power consumption on the SOI film.

In the manufacturing method of semiconductor devices according to the present invention, it is possible to form high performance BIP elements and CMOSFETs at the same time as described in the above embodiment, which provides a high performance BiCMOS structure not found in conventional semiconductor devices. In addition, to make use of the features of lateral BIP elements, two SOI film thicknesses are used to minimize the number of processes, which enables simultaneous formation with MOSFETs. An LDD structure of MOSFET and a low-concentration impurity region intervening between the base and collector regions in a BIP element can be formed at the same time, which improves not only the reliability of the MOSFET but also the withstand voltage of the BIP element without complicating the processes.

FIG. 7 illustrates a sectional structure of a semiconductor device of a complementary BiCMOS structure formed according to a manufacturing method of the present invention. In the figure, the structures of Nch MOSFET and n-p-n BIP element are the same as those of FIG. 5A. The parts of a Pch MOSFET are indicated by the 70s and 80s replacing the reference numbers of the Nch MOSFET and the parts of a p-n-p BIP element are represented by the 70s replacing the reference numbers of the n-p-n BIP element. The difference between the BiCMOS structure of FIG. 7 and that of FIG. 5A is that the base region of the BIP element is left thicker than the emitter and collector regions, and at the same time, the source-drain region of the MOSFET is left thicker than the channel-forming region. This arrangement is obtained by selectively etching and thinning the predetermined region of the semiconductor layer in the same etching process.

As described above, in a manufacturing method according to the present invention, it is possible to simultaneously form Pch MOSFETs and p-n-p BIP elements in the same substrate as well as the aforementioned Nch MOSFETs and n-p-n BIP elements.

Elements formed together with BIP elements are not limited to MOSFETs and may be other types of FETs such as MIS-type FETs, Schottky junction FETs, or SIS-type FETs.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.