Semiconductor Memory Including Reduced Capacitive Coupling Between Adjacent Bit Lines

The invention relates to a semiconductor memory apparatus, and more particularly to a semiconductor memory apparatus having complementary bit lines, each connected to a sense amp circuit.

A conventional semiconductor memory apparatus of a complementary bit line type comprises a predetermined number of memory cells to provide a desired memory capacity, a predetermined number of complementary bit line pairs, among which each two complementary bit line pairs are connected to a corresponding memory cell to provide dual ports, a predetermined number of word lines, two of which word lines are connected to a corresponding memory cell to allow asynchronous access for the dual ports, and a predetermined number of sense amplifier (defined "amp" hereinafter) circuits each connected to one of the complementary bit line pairs.

In operation, it is assumed that each of the complementary bit line pairs is under "high" at first in accordance with the initialization of the memory apparatus. When a word selection signal becomes "high" on a word line for a first selected port, a signal level difference begins to be produced between bit lines of a complementary bit line pair for the first selected port dependent on a content of a memory cell. Subsequently, when a word signal becomes "high" on a word line for a second selected port, a signal level difference begins to be produced between bit lines of a complementary bit line pair for the second selected port dependent on the content of the memory cell in the same manner as in the first selected port. At this moment, a sense amp circuit connected to the bit lines for the first selected port is enabled to amplify and stabilize the signal level difference. Thus, information is read from a port corresponding to a selected memory cell. The structure and operation of the conventional semiconductor memory apparatus of the complementary bit line type will be explained in more detail later.

According to the conventional semiconductor memory apparatus, however, there are disadvantages that an erasure or a destruction of information occurs in a memory cell, and that erroneous information is read from a memory cell, because a signal level is pulled, for instance, from "high" to "low" on a bit line of the second selected port under the influence of a signal level on a bit line of the first selected port, where the bit lines of the first and second selected ports are heavily coupled by a line-to-line capacitance produced therebetween. This results in an inversion of a readout information at the second selected port.

These disadvantages will be overcome, if the line-to-line capacitance is lowered to a predetermined level between adjacent bit lines of the dual ports, or if accesses are synchronized between the dual ports. For this purpose, the length of bit lines must be shortened to reduce the line-to-line capacitance, making it difficult to increase the memory capacity. Further, access control of the dual ports will be complicated.

Accordingly, it is an object of the invention to provide a semiconductor memory apparatus in which a memory capacity can be increased without the influence of a line-to-line capacitance.

It is a further object of the invention to provide a semiconductor memory apparatus in which there is no limitation in an access to dual ports.

According to the invention, a semiconductor memory apparatus comprises,

a predetermined number of memory cells, each storing a binary information;

a plurality of complementary bit line pairs, to which corresponding memory cells are connected, each complementary bit line pair being accessible to the corresponding memory cells;

a plurality of sense amplifier circuits, each connected to a complementary bit line pair and amplifying a signal level difference between bit lines of the complementary bit line pair; and

a plurality of grounded lines each provided between adjacent complementary bit line pairs and avoiding the formation of a line-to-line capacitance between adjacent bit lines of the adjacent complementary bit line pairs.

The invention will be explained in more detail in conjunction with appended drawings wherein,

FIG. 1 is a circuit diagram showing a conventional semiconductor memory apparatus,

FIG. 2 is a timing chart showing operation in the conventional semiconductor memory apparatus,

FIG. 3 is a matrix diagram showing an embodiment according to the invention,

FIG. 4 is a circuit diagram showing a pertinent portion in the embodiment of the present invention shown in FIG. 3, and

FIG. 5 is a timing chart showing operation in the embodiment at the present invention shown in FIG. 3.

Before explaining an embodiment according to the invention, the aforementioned conventional semiconductor memory apparatus of a complementary bit line type will be explained with reference to FIG. 1. The semiconductor memory apparatus comprises complementary bit line pairs D.sub.1 and D.sub.1, D.sub.2 and D.sub.2, - - - for ports 1.sub.1, 1.sub.2, - - - , word lines 11.sub.1 and 12.sub.1, - - - crossing the bit line pairs, memory cells 3, - - - to be addressed by the bit line pairs and the word lines, and sense amp circuits 4.sub.1, 4.sub.2, - - - each connected to a corresponding bit line pair among the bit line pairs. One of the memory cells 3 includes transfer gate MOS transistors 3A, 3B, 3C and 3D, and driver MOS transistors 3E and 3F. As clearly shown in FIG. 1, the transfer gate transistors 3A and 3B are connected to the bit line pair D.sub.1 and D.sub.1 and the word line 11.sub.1, and the transfer gate transistors 3C and 3D are connected to the bit line pair D.sub.2 and D.sub.2 and the word line 12.sub.1. On the other hand, the driver transistors 3E and 3F are connected by drain electrodes thereof through the transfer gate transistors 3A, 3B, 3C and 3D to the bit line pairs and the word lines, and by source electrodes to the ground. If it is assumed that a content of the memory cell 3 is "1", the drain electrode of the driver transistor 3E is "high", so that the driver transistor 3F is connected to ground rendered conductive. Therefore, (coupled to ground) the drain electrode of the driver transistor 3F is "low", so that the driver transistor 3E is not connected to ground rendered conductive.

The sense amp circuits 4.sub.1 and 4.sub.2 include MOS transistors 4A.sub.1, 4B.sub.1 and 4C.sub.1, and 4A.sub.2, 4B.sub.2, and 4C.sub.2, and allow a sense amp enabling signal to be applied to each of the gate electrodes of the MOS transistors 4C.sub.1 and 4C.sub.2. In this semiconductor memory apparatus, parasitic capacitances C.sub.1, C.sub.3, C.sub.4, C.sub.5, C.sub.6 and C.sub.7 are produced as shown in FIG. 1, and a line-to-line capacitance C.sub.2 is produced between the bit lines D.sub.1 and D.sub.2.

In operation, the bit lines D.sub.1, and D.sub.1, and D.sub.2 and D.sub.2 for the ports 1.sub.1 and 1.sub.2 are initialized to be "high" at first as shown in FIG. 2. At time t.sub.1, when a word selection signal for the port 1.sub.1 is enabled on the word line 11.sub.1, a signal level difference begins to be produced between the bit lines D.sub.1 and D.sub.1 for the port 1.sub.1 in accordance with a content "1" of the memory cell 3 as described before. Subsequently, when a word selection signal for the port 1.sub.2 is enabled on the word line 12.sub.1 at time t.sub.2, a signal level difference begins to be produced in the same manner as in the port 1.sub.1. At this moment, an enabling signal is applied to an enabling signal line 6.sub.1 of the MOS transistor 4C.sub.1 in the sense amp circuit 4.sub.1, so that the signal level difference between the bit lines D.sub.1 and D.sub.1 for the port 1.sub.1 is amplified in the sense amp circuit 4.sub.1 to stabilize a state of the signal level difference. In this situation, a signal level of the bit line D.sub.2 for the port 1.sub.2 is pulled from "high" to "low" in accordance with the influence of the line-to-line capacitance C.sub.2 as indicated by a point P.sub.1, although the signal level is inherently "high" dependent on the content of the memory cell 3. On the contrary, a signal level of the bit line D.sub.2 becomes "high" invertedly. At time t.sub.3, a sense amp enabling signal is applied to an enabling signal line 6.sub.2 of the MOS transistor 4C.sub.2 in the sense amp circuit 4.sub.2 to read information from the memory cell 3 at the port 1.sub.2. Although the signal level of the bit line D.sub.2 exhibits a tendency to restore the inherent state as indicated by a point P.sub.2, it can not get back to a state correctly based on the content of the memory cell 3. As a result, an inverted signal is read at the port 1.sub.2 from the memory cells. Therefore, the aforementioned disadvantages are produced by the conventional semiconductor memory apparatus of the complementary bit line type.

Next, a semiconductor memory apparatus of a complementary bit line type while referring to an embodiment according to the invention will be explained in FIG. 3. The semiconductor memory apparatus comprises memory cell arrays 2.sub.1, 2.sub.2, 2.sub.3, - - - , each of which includes memory cells 3.sub.1, 3.sub.2, 3.sub.3, - - - each connected to bit line pairs D.sub.1 and D.sub.1 for a port 1.sub.1, D.sub.2 and D.sub.2 for a port 1.sub.2, - - - and to corresponding word lines 11.sub.1 and 12.sub.1, 11.sub.2 and 12.sub.2, 11.sub.3 and 12.sub.3, - - - , sense amp circuits 4.sub.1, 4.sub.2, 4.sub.3, 4.sub.4, 4.sub.5, 4.sub.6 - - - each connected to a corresponding bit line pair among the bit line pairs D.sub.1 and D.sub.1 for the port 1.sub.1, and D.sub.2 and D.sub.2 for the port 1.sub.2, and other bit line pairs for ports 1.sub.3, 1.sub.4, 1.sub.5, 1.sub.6 - - - , and to sense amp enabling line 6.sub.1 or 6.sub.2, and sealed lines 5.sub.1, 5.sub.2, 5.sub.3, 5.sub.4, 5.sub.5, - - - each connected to ground and provided between bit lines for each two adjacent ports.

FIG. 4 shows a pertinent portion of the semiconductor memory apparatus in the embodiment of FIG. 3, wherein like parts are indicated by like reference numerals in FIGS. 1 and 3. The difference between the semiconductor memory apparatus in the embodiment and the conventional one is that the former further comprises the sealed (grounded) lines 5.sub.1, 5.sub.2, 5.sub.3, 5.sub.4, 5.sub.5, - - - to avoid the aforementioned influence of the line-to-line capacitance. As shown in FIG. 4, the line-to-line capacitance C.sub.2 is no longer produced when the grounded line 5.sub.2 is provided between the bit lines D.sub.1 and D.sub.2. Instead, capacitances C.sub.21 and C.sub.22 are produced between the bit line D.sub.1 and the grounded line 5.sub.2, and the grounded line 5.sub.2 and the bit line D.sub.2. The grounded line 5.sub.2 is preferably provided, such that the capacitances C.sub.21 and C.sub.22 are equal in value.

In operation, the bit lines D.sub.1 and D.sub.1, and D.sub.2 and D.sub.2 for the ports 1.sub.1 and 1.sub.2 are initialized to be "high" at first as shown in FIG. 5. At time t.sub.1, when a word selection signal for the port 1.sub.1 is enabled on the word line 11.sub.1, a signal level difference begins to be produced between the bit lines D.sub.1 and D.sub.1 for the port 1.sub.1 in accordance with a content "1" of the memory cell 3 in the same manner as in the conventional memory apparatus. Subsequently, when a word selection signal for the port 1.sub.2 is enabled on the word line 12.sub.1 at time t.sub.2, a signal level difference begins to be produced in the same manner as in the port 1.sub.1. At this moment, an enabling signal is applied to an enabling signal line 6.sub.1 of the MOS transistor 4C.sub.1 in the sense amp circuit 4.sub.1, so that the signal level difference between the bit lines D.sub.1 and D.sub.1 for the port 1.sub.1 is amplified in the sense amp circuit 4.sub.1 to stabilize a state of the signal level difference. At the same time, a signal level difference begins to be produced between the bit lines D.sub.2 and D.sub.2 for the port 1.sub.2 in accordance with the content of the memory cell 3. In this situation, a signal level of the bit line D.sub.2 continues to be "high", because there is no line-to-line capacitance between the bit lines D.sub.1 and D.sub.2. At time t.sub.3, an enabling signal is applied to an enabling signal line 6.sub.2 of the MOS transistor 4C.sub.2 in the sense amp circuit 4.sub.2, so that the signal level difference between the bit lines D.sub.2 and D.sub.2 for the port 1.sub.2 is amplified in the sense amp circuit 4.sub.2 to stabilize a state of the signal level difference. Thus, information of the memory cell 3 can be read at the dual ports 1.sub.1 and 1.sub.2 without any complicated control in regard to a read-out timing and so on.

Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.