Contrast Control Based on Mean and Deviation Values

In recent liquid crystal display television receivers, real-timer digital signal processing for video signals has been frequently employed, and among the television signal processings a base-band video-signal processing which is performed in a digital fashion has been put to practical use in a form of IDTV. The conventional digital video-signal processing circuit is constructed as shown in FIG. 1. More specifically, a composite video signal output from a video detector (not shown) is converted into a digital signal by an analog to digital converter (A/D converter) 11 and then separated into a luminance signal Y and a chrominance signal C by a luminance/chrominance separator circuit (Y/C separator circuit) 12. The chrominance signal C is demodulated into color-difference signals, R-Y and B-Y by a color-difference demodulator circuit 13 and transferred to a matrix circuit 14. In the matrix circuit 14, the color difference signals R-Y and B-Y are added to the luminance signal Y from Y/C separator circuit 12. As a result, color signals, R, G and B are obtained. Then these color signals R, G and B are sent to a liquid crystal display section (not shown) to be displayed on a liquid crystal display panel.

The above liquid crystal display panel provides a low gradient. Therefore, if the above liquid crystal display panel is not used efficiently, a picture with an adequate contrast of light and shade is not available on the above liquid crystal display panel. In the above conventional video-signal processing circuit, the luminance signal Y obtained by Y/C separator circuit 12 is directly input to the matrix circuit 14, which generates color signals R, G and B corresponding to a level of the luminance signal Y. Therefore, in case that a picture is of an average brightness, the color signals R, G, B vary with a median level of the luminance signal Y as their median level. Hence a picture can be displayed with adequate contrast or with a high gradient on the liquid crystal display panel. In case that a picture is a bright scene or a dark scene, and the level of the luminance signal Y is high or low, the color signals R, G, B from the matrix circuit 14 incline towards a high level or a low level. In this case, the liquid crystal display panel is used inefficiently so that a picture with an inadequate contrast of light and shade is displayed on the display panel.

The present invention has been made in consideration of the above described situations and its object is to provide a level control circuit which is capable of controlling the color signals such that they always vary with a mean value of the luminance signal as their median level and within a certain range even when the luminance signal various greatly, and which permits a picture to be displayed with high contrast of light and dark on the liquid crystal display panel.

According to the invention, there is provided a level control circuit used in a digital video-signal processing circuit, which comprises mean value detection means for detecting a mean value of a luminance signal composed of digital signals; subtraction means for subtracting the means value detected by said mean value detection means from the luminance signal; and restriction means for restricting an output signal from said subtraction means to a range defined by predetermined upper and lower limits.

The level control circuit constructed as described above outputs a signal having constant upper and lower levels and a mean value as the median level even though the luminance signal varies greatly. Accordingly, when the level-controlled luminance signal is added to color-difference signals, color signals R, G, B are obtained, which allow a picture to be displayed with an adequate gradient on the liquid crystal display panel.

FIG. 1 is a block diagram showing a construction of a conventional digital-video-signal processing circuit;

FIGS. 2 through 5 are views showing the first embodiment of the present invention;

FIG. 2 is a block diagram of a digital video signal processing circuit according to the present invention;

FIG. 3 is a block diagram showing a detailed construction of a level control circuit;

FIG. 4 is a block diagram showing an embodiment of a mean value detection circuit;

FIG. 5 is a block diagram showing the level control circuit employing the means value detection circuit of FIG. 4;

FIG. 6 is a block diagram showing an overall construction of a contrast calculation circuit according to the second embodiment of the invention;

FIG. 7 is a block diagram showing a detail of the contrast calculation circuit of FIG. 6; and

FIG. 8 is a block diagram showing other embodiment of the present invention .

Now, the first embodiment of the present invention will be described referring to the accompanying drawings. FIG. 2 is a view showing a construction of the digital-video-signal processing circuit. A composite video signal from a video detector (not shown) is subjected to a sampling process in an analog to digital converter (A/D converter) 11 thereby converted into a digital signal of several bits. Then the digital signal is transferred to Y/C separator circuit (luminance/chrominance separator circuit) 12 to be separated into a luminance signal Y and a chrominance signal C. The chrominance signal C is demodulated by a color-difference demodulator circuit 13 into color-difference signals R-Y and B-Y and then further transferred to a matrix circuit 14. The luminance signal Y obtained by Y/C separator circuit 12 is supplied to a level control circuit 15. The level control circuit 15, as will be described in detail later, controls the level of the luminance signal Y from Y/C separator circuit 12 on the basis of a mean value of the luminance signal Y to obtain a luminance signal Y', which is further supplied to the matrix circuit 14. The matrix circuit 14 adds the luminance signal Y' to the color-difference signals, R-Y, B-Y from the color-difference demodulator circuit 13, thereby obtaining color signals R', G', B' A liquid crystal display display panel (not shown) is driven on the basis of the color signals, R', G', B'.

The detail of the level control circuit 15 will be described with reference to FIG. 3. The luminance signal Y from Y/C separator circuit 12 is supplied to a mean value detector circuit 21 and a positive terminal of a subtractor circuit 22. The mean value detector circuit 21 calculates the mean value Y of the luminance signal Y and supplies the same to a negative terminal of the subtractor circuit 22. The subtractor circuit 22 subtracts the calculated mean value Y from the luminance signal Y and supplies the difference to a limiting circuit 23. The limiting circuit 23 restricts the amplitude of the supplied signal to a range defined by predetermined upper and lower limits. Then the output signal of the limiting circuit 23 is supplied as the luminance signal Y' to the matrix circuit 14.

In the level control circuit having the above mentioned construction, a difference signal between the luminance signal Y and its mean value Y is obtained and the amplitude of the difference signal is restricted to a range defined by predetermined upper and lower limits. Only the part of the luminance signal Y which lie in a settled range above or below its mean value Y is selected and output as the luminance signal Y'. Then, the matrix circuit 14 extracts color signals R', G', B' from color-difference signals R-Y, B-Y on the basis of the luminance signal Y'. Hence, the color signals R', G', B' will have levels which lie within a settled range. The liquid crystal display panel is efficiently driven by the above color signals R', G', B' thereby displaying a picture with an adequate contrast of light and dark.

The above mentioned mean value detector circuit 1 calculates a mean value Y of one field of the luminance signal Y from the following equation: ##EQU1## In this case, a memory and an adder circuit are used to obtain the mean value Y from the above equation. However, a number of memories and adder circuits are required to constitute the mean value detector circuit 21.

Meanwhile, the above mean value detector circuit 21 can be constructed with a simple circuit construction shown in FIG. 4. In the circuit shown in FIG. 4, a low-pass filter of a circular-adder type constitutes the mean value detector circuit 21, since a low-pass filter has a mean value detection function. More specifically, the luminance signal Y from Y/C separator circuit 12 is supplied to an adder circuit 31 and also to the negative terminal of a subtractor circuit 32. The output signal of the adder circuit 31 is supplied to the positive terminal of the above subtractor circuit 32 through a delay circuit 33 having a delay time of one sampling interval. The output signal of the subtractor circuit 32 is further supplied to a multiplier circuit 34. In the multiplier circuit 34, the output signal of the subtractor circuit 32 is multiplied by a given constant K and the product is input to the adder circuit 31. The adder circuit 31 adds the output signal of the adder circuit 34 to the luminance signal Y and supplies the sum to the delay circuit 33 and at the same time outputs the sum as the mean value Y of the luminance signal Y.

In the circuit of FIG. 4, an output signal Zn-1 sampled previously by one sampling time is retained in the delay circuit 33, at the time when a luminance signal Yn is input. Accordingly, in the subtractor circuit 32, a subtraction, Zn-1, - Yn is executed and the difference is multiplied by a constant K in the multiplier circuit 34. Then, the product K(Zn-1 - Yn) is supplied to the adder circuit 31. The adder circuit 31 adds the luminance signal Yn to the output signal K(Zn-1 - Yn) of the multiplier circuit 34. The sum Zn i.e., Yn +K(Zn-1 - Yn) is output as the mean value Yn of the luminance signal Yn.

Accordingly, the signal processing in FIG. 4 will be expressed by

The mean value Yn of the luminance signal Yn obtained by the above mean value detector circuit 21 is transferred to the subtrator circuit 22 of FIG. 3, where a subtraction, Y-Y is executed. In this case, the difference is given by ##EQU2##

As shown in FIG. 4, when the low-pass filter of a circular adder type is employed to constitute the mean value detector circuit 21, the level control circuit 15 of FIG. 3 may be constructed as shown in FIG. 5. The signal "K(Zn-1- Yn)" supplied from the multiplier circuit 34 is multiplied by "-1" in a multiplier circuit 35 and then the signal, "-K(Zn-1 - Yn)" is obtained. The limiting circuit 23 restricts the output signal of the multiplier circuit 35 to a range defined by the upper and lower limits, and then outputs the restricted signal as the output signal Y' of the level control circuit 15.

It will be apparent from the above description that with use of the level control circuit having a vary simple construction. The initial object can be achieved

Now, the second embodiment of the present invention will be described with reference to FIGS. 6 and 7.

FIG. 6 is a block diagram showing a construction of a contrast circuit portion in the digital-video-signal processing circuit. A video signal is separated into a chrominance signal and a luminance signal Y in a preceding luminance/chrominance signal separator stage (not shown). The separated luminance signal Y is a binary-digit data, for example, of 6 bits and with a symbol. The luminance signal Y is supplied through a signal line 120 to an amplifier stage, e.g., a multiplier circuit 121 and a contrast calculation circuit 122. The contrast calculation circuit 122, as will be described in detail later, calculates a contrast value from the above luminance signal Y and sets a gaincontrol signal on the basis of the contrast value. The gain-control signal is supplied to a multiplier circuit 121. The multiplier circuit 121 executes a multiplication processing for the above luminance signal Y on the basis of the gain-control signal from the contrast calculation circuit 122 and outputs the product as an output signal of a contrast circuit to a following processing circuit, e.g., a matrix circuit (not shown). The matrix circuit adds the color difference signals R-Y, B-Y demodulated by a color-demodulator circuit (not shown) to the luminance signal Y from the above multiplier circuit 121. Thereby reproducing color signals R, G, B to a display driving circuit (not shown). The display driving circuit drives the liquid crystal display panel (not shown) on the basis of the reproduced color signals R, G, B.

FIG. 8 is a view showing the detail of the above contrast calculation circuit 122. The luminance signal Y of 6 bits transferred from a preceding processing circuit through the signal line 120 is supplied to a data input terminal D of a flip flop circuit 131 of a D-type. The D type flip-flop circuit 131 latches the luminance signal Y in synchronism with clock pulses CK and outputs the latched luminance signal Y through an invertor circuit 132 to an accumulator circuit 133. The accumulator circuit 133 accumulates the supplied data and outputs an over-flow signal caused by accumulation of data to one input terminal of an AND circuit 134. The AND circuit 134 serves to limit a range of the accumulated data to an effective display-picture. An effective display-picture selection signal for excluding the data in the blanking periods from the data is supplied to the other terminal of the AND circuit 134. The output signal for the above AND circuit 134 is supplied to an over-flow counter 135. The over-flow counter 135 counts number of times when over-flows are caused and supplies the count-output to the data input terminal D of a D-type flip-flop circuit 136. The flip-flop circuit 136 latches the value of the flip-flop circuit 136 in accordance with vertical synchronizing signals V sync which are supplied to its clock terminal CK at intervals of one field. At this time, the count value of the over-flow counter 135 is reset by the above synchronizing signals V sync.

The output signal of the above flip-flop circuit 136 is supplied to a luminance-deviation calculation circuit 137, which is composed of a subtractor circuit 138, a D-type flip-flop circuit 139 and an absolute value circuit 40. The output signal of the above flip-flop circuit 136 is supplied to the negative terminal of the subtractor circuit 138. To the positive terminal of the subtractor circuit 138 is supplied the luminance signal Y transferred from the preceding circuit through the signal line 120. The output signal of the subtractor circuit 138 is latched in the flip flop circuit 139 in synchronism with the clock pulses CK and is supplied to the absolute value circuit 110. The absolute value circuit 140 is composed of, for example, an exclusive OR circuit and obtains an absolute value of the data latched in the flip-flop circuit 139 and then supplies the absolute value to an one-field adder circuit 141.

The one-field adder circuit 141 composed of the above delay circuit 133, multiplier circuit 134, 135, accumulates absolute values which are output from the absolute value circuit 140 during the period of one field in order to obtain and supply a contrast value to a control-signal circuit 142.

The control-signal output circuit 142 subtracts a certain rate of the contrast value, i.e., a certain rate of the output signal of the one-field adder circuit 141 from the multiplier constant in the multiplier circuit 121 of FIG. 6, thereby producing a gain control signal. The gain control signal is supplied to the multiplier circuit 121 to control its gain.

Now, the operation of the above contrast calculation circuit 122 will be described. The luminance signal Y of 6 bits and having a symbol, which are supplied to the flip-flop circuit 131 through the signal line 120, is latched in the circuit 131 in synchronism with the clock pulses CK and further is supplied to the invertor circuit 132 to be inverted into a positive luminance data. The positive luminance data is accumulated by the accumulator circuit 133. The accumulator circuit 133 sequentially accumulates input data and supplies an over-flow signal to the AND circuit 134 to limit the range of the data to be accumulated when an over flow of the accumulated data occurs. The output signal of AND circuit 134 is supplied to the over-flow counter 135 to be counted. In other words, number of times when the accumulator circuit 133 causes over-flows is counted by the over-flow counter 135. The count values are latched in the flip-flop circuit 136 at intervals of one field in synchronism with the vertical synchronizing signal. At this time, the above over-flow counter 135 is reset in accordance with the vertical synchronizing signal. In the above mentioned process, the mean value of one field of the luminance signal Y is latched in the flip-flop circuit 136.

The mean value of the luminance signal Y latched in the flip-flop circuit 136 is supplied to the luminance deviation calculator circuit 137, which calculates a luminance deviation. More specifically, in the luminance deviation calculator circuit 137, the subtraction circuit 138 subtracts the mean value of the luminance signal Y latched in the flip-flop circuit 136 from the luminance signal Y input to the circuit 138 through the signal line 120 and latches the difference in the flip-flop circuit 139 in synchronism with the clock pulses CK. In this manner, deviation from the mean value of each luminance signal is obtained. The deviation latched in the flip-flop circuit 139 is supplied to the absolute value circuit 140. The absolute value circuit 140 obtains an absolute value of the supplied deviation and outputs the absolute value as the output signal of the luminance deviation calculator circuit 137.

One-field adder circuit 141 accumulates deviations which are output from the luminance deviation calculator circuit 137 during the period of one field, thereby obtaining a contrast value.

Thereafter, the control signal output circuit 142 subtracts a certain rate of the contrast value, i.e., a certain rate of the output signal of the above one-field adder circuit 141 from the multiplier constant of the multiplier circuit 121 of FIG. 6, thereby obtaining a gain-control signal. The above rate of the contrast value to be subtracted from the multiplier constant decides a level of automatic contrast adjustment. In case that the rate of the contrast value to be subtracted from the multiplier constant is "zero", no automatic contrast adjustment is effected. When the above rate of the contrast value is gradually increased from "zero", the automatic contrast adjustment functions and provides a desired effect at a certain rate of the contrast value to be subtracted from the multiplier constant.

In the above embodiment, deviation of a luminance signal from its mean value is effectively used to control gain of the amplifier means, so that the gain of the amplifier means can be appropriately controlled in accordance with the amplitude level of the luminance signal and a picture can be always displayed with steady contrast, even though the picture is of a light scene or of a dark scene, i.e., even though the luminance signal is of a relatively high level or of a relatively low level. For example, even though the luminance signal of a picture lies at around white level and varies slightly, the control-signal output circuit 142 generates a gain-control signal corresponding to the amplitude level of the luminance signal and the gain of the multiplier circuit 121 is increased so as to allow the picture to be displayed with adequate contrast.

In the above mentioned embodiment, it has been described that the luminance signal Y transferred through the signal line 120 is supplied to the multiplier circuit 121 and at the same time to the contrast calculation circuit 122 in order to obtain a contrast value. However, as shown in FIG. 8, the output signal of the multiplier circuit 121 may be supplied to the contrast calculator circuit 122 to obtain the contrast value. In this manner, it is possible to obtain effects similar to those provided by the above described embodiment.