Current Biasing for I.sup.2 L Circuits

The present invention relates to improved current biasing of integrated injection logic (I.sup.2 L) circuits.

I.sup.2 L circuits are formed in an integrated circuit and comprise an inverted npn transistor structure having multiple open collectors and an pnp injector, as is well known. The collector of the pnp injector is formed in common with the base input of the npn transistor while its base is common to the emitter of the latter. Biasing of the I.sup.2 L circuit is normally achieved by connecting a resistor from the emitter of the injector to a positive voltage. This technique though very simple, has the drawback that the hole efficiency of the injector alpha determines the amount current sourced from the injector to the base of the inverted npn transistor. This current then directly effects the charging of the input node (base of the npn transistor) of the I.sup.2 L circuit and is dependent on process variations in the manufacturing of the integrated circuit. Hence, the speed of operation of the I.sup.2 L circuit will vary with process tolerances in production of such circuits. This is undesirable in that the circuit can fail circuit specifications which reduces yield of production parts incorporating such I.sup.2 L circuits.

Thus, there is a need for an improved biasing arrangement for use in I.sup.2 L circuits for minimizing the effects of injector alpha on the speed of the circuit due to integrated circuit fabrication process tolerances.

In accordance with the above there is provided a current bias arrangement comprising a negative feedback loop for matching the collector current of the injector transistor of a I.sup.2 L circuit to a reference current wherein the reference current is sourced to a first collector of a two-collector I.sup.2 L gate comprising the feedback loop while the second collector thereof is connected to the input of the gate, the feedback loop also includes circuitry coupled between the first collector and the injector input of the I.sup.2 L gate which regulates the current through the injector of the gate and the output of the bias arrangement is then taken at the injector input to drive the injector inputs of multiple I.sup.2 L circuits coupled thereto.

FIGS. 1 and 2 are prior art logic and schematic diagrams respectively of a conventional I.sup.2 L gate; and

FIG. 3 is a schematic diagram of an embodiment of the current biasing arrangement of the present invention.

Referring to FIGS. 1 and 2 there is shown a conventional I.sup.2 L gate 10 including input 12, injector node 14 and multiple outputs 16 and 18. As known, the I.sup.2 L gate is formed in an integrated circuit wherein the n-epitaxial region forms both the emitter of npn transistor 19 and the base of pnp injector transistor 17 which are coupled to a common potential in operation. The base of npn transistor 19 is formed by p-type material diffused into the epitaxial region which also comprises the collector of injector 17 both of which are coupled to input 12. Multiple collector outputs are then formed of multiple n-type material regions diffused into the base region of transistor 19. Transistor 19 is shown as having at least two such collectors coupled to terminals 16 and 18 although additional collectors could be realized. The emitter of injector 17 is separately deposited in the epitaxial region of the integrated circuit and consists of a p-type material that is coupled to injector bias node 14. Transistor 19 is schematically shown and referred to as an inverted transistor. This refers to the fact that the collectors of transistor 19 in the I.sup.2 L configuration correspond to the emitters of a standard vertical npn transistor while the emitter of the former corresponds to the collector of the latter. The foregoing structure of I.sup.2 L gate 10 is well known and is not novel.

Typically, injection node 14 is coupled in operation to a positive operating potential via a resistor (not shown) while the base of the injector and emitter of transistor 19 are coupled to a common or ground potential. Thus, a positive input signal at input 12 turns on transistor 19 which is supplied base current drive from injector 17. The potential at outputs 16 and 18 will go to a logic zero as transistor 19 is turned on and will go to a logic one as input 12 goes to a logic zero.

As previously mentioned, the gain of injector 17 varies widely with manufacturing process tolerances found in today's integrated circuit fabrication techniques. As the gain of the injector varies the amount of base current supplied from the collector thereof is not controlled which effects the charging of the node coupled to input 12. Hence, the speed of operation of the I.sup.2 L gate is affected. The present invention provides a bias circuit and method for controlling the current at the collector of the injector in order to have a well defined injector current thereby making the gate delay (speed) independent of the injector transistor.

Turning now to FIG. 3 the current bias circuit 20 of the present invention will be described. Bias circuit 20 is utilized to provide a known and predetermined injector current to I.sup.2 L circuits such as I.sup.2 L gates 22 and 24 of the type as illustrated in FIGS. 1 and 2. The I.sup.2 L injector bias circuit of the present invention minimizes the effects of injector alpha on speed and comprises a negative feedback loop to match the current at the collector of the injector to a well controlled reference current as will now be explained.

Bias circuit 20 includes a two-collector I.sup.2 L gate 26 the structure of which is shown in FIG. 2. One of the collector outputs, either 16 or 18 is connected to the input 12. Gate 20, in combination with the circuitry coupled between the other collector output and the injector input node 27 comprises a negative feedback loop that is used to match the current at the collector of the pnp injector to a controlled reference current. Thus, the collector of gate 26 that is not returned to the input of the gate is coupled to the emitter of npn transistor 28, the base of which is biased by a potential V.sub.B. The collector of transistor 28 is coupled to current source 30 the latter of which is returned to a first power supply conductor to which is supplied V.sub.CC. Current source 30 supplies the controlled reference current that is the desired injector current. Pnp transistor 32 has its base coupled to the collector of transistor 28, its collector coupled to a second power supply conductor to which is applied ground reference and an emitter coupled to current source 34. Current source 34 being coupled to V.sub.CC provides a current sufficient to supply base current drive to the base of npn transistor 36 and transistor 32. The collector of transistor 36 is returned to V.sub.CC while its emitter is coupled to output node 27; the injector input nodes for I.sup.2 L gates 22, 24 and 26.

In operation, V.sub.B is of sufficient magnitude, i.e., at least two base-to-emitter voltage drops, to prevent the inverted transistor 19 of gate 26 from becoming saturated and breaking down from excessive reverse bias on collector 18. Hence, the predetermined and desired current I.sub.REF is sourced through the collector-emitter path of transistor 28 into the collector (18) of gate 26 coupled thereto. This forces the base-to-emitter voltage of transistor 19 to a resulting value. By connecting the other collector (16) of transistor 19 back to its base (the input of gate 26) a current mirror is produced such that this collector wants to sink the same magnitude of current as is forced into the other collector of the gate. Therefore, the injector current sourced from injector 17 of the gate 26 to the base of transistor 19 thereof is forced to be substantially the known current I.sub.REF. The feedback loop will regulate the current in the collector coupled to terminal 16 until the injector current is matched to the reference current. In a regulated state, the voltage V.sub.O is set and is such that if node 27 is coupled to the injector input node 14 of additional I.sup.2 L gates 22 and 24 then the base-to-emitter voltage drop of the injector transistors of these gates should be equal to that of the injector of gate 26. This will result in substantially the same injector current in all the gates with each being equal to I.sub.REF.

Hence, by using a two-collector I.sup.2 L gate in a negative feedback loop, wherein one collector is coupled to the input of the gate and driving circuitry is coupled between the other collector of the gate and the injector input thereof, the injector current can be matched to a known reference current that is forced into the other collector of the gate. The resulting circuit can be used to bias I.sup.2 L circuits having their injector inputs coupled to the injector input of the two-collector gate of the bias circuit.