Apparatus for Sequential Optical Systems Where an Independently Controllable Transmission Gate Is Interposed Between Successive Optoelectronic Gates

This invention relates to optoelectronic apparatus.

To make competitive optical computers and photonic switches, optical devices are required that perform functions that are similar to the functions performed by electronic devices in electronic systems. By using optoelectronic devices, such as the quantum well self electro-optic effect devices (SEEDs) disclosed in U.S. Re. Pat. No. 32,893 issued to D. A. B. Miller on Mar. 21, 1989, many such corresponding functions can be achieved. The symmetric SEEDs (S-SEEDs) disclosed in U.S. Pat. No. 4,754,132 issued to H. S. Hinton et al. on June 28, 1988 have been shown to operate as set-reset latches, differential logic gates, or optical tri-state logic devices (U.S. Pat. No. 4,800,262 issued to A. L. Lentine on Jan. 24, 1989). More recently, S-SEEDs have been applied as logic gates capable of implementing any boolean logic function in a single combinational circuit with a single clock cycle of delay (allowed U.S. patent application Ser. Nos. 07/399,638 and 07/399,730 of A. L. Lentine et al.). This is important because it avoids the optical cascading otherwise needed to perform more complex logic functions; the approach is lacking, however, in that there is no apparent way to implement sequential circuits, such as shift registers, counters, multiplexers and demultiplexers.

Allowed U.S. patent application Ser. No. 07/283,336 of H. S. Hinton et al. discloses one known sequential optical circuit apparatus comprising optically cascaded S-SEEDs in an integrated structure; while the monolithic structure eliminates the need for the bulk optics of free space optically interconnected subsystems, the structure is complex, and adds capacitance thereby reducing system speed. Because the devices are optically cascaded, it is not possible in some applications to use short pulses to rapidly switch the devices because of saturation of the first device of a cascaded pair. In view of the foregoing, a recognized deficiency in the art is the lack of an apparatus for implementing optical sequential logic without requiring optical cascading.

This deficiency is eliminated and a technical advance is achieved in accordance with the principles of the invention in an apparatus where information is communicated to and from the apparatus in the optical domain, but where the apparatus includes a transmission gate advantageously interposed between successive optoelectronic gates to sequentially convey information internally, significantly in the form of electrical, rather than optical, signals. Since there is no need to optically cascade component gates, the apparatus construction is simplified because there is no need to align the optical output of one gate for transmission as the optical input to a second gate. Switching speed is improved since the structure is of reduced size and therefore reduced capacitance compared to the known Hinton et al. monolithic structure and since there is no tendency to overdrive and thereby saturate a first gate in order to provide sufficient optical input power to a second gate.

An apparatus in accordance with the invention includes first and second optoelectronic gates and a transmission gate. The first optoelectronic gate has a logical state controllable by an optical input signal and generates an electrical signal representative of the logical state. The transmission gate is electrically coupled to the first optoelectronic gate and selectively transmits the electrical signal. The second optoelectronic gate is electrically coupled to the transmission gate and has an optical state controllable by the selectively transmitted electrical signal.

In an illustrative embodiment, the transmission gate is optoelectronic, responsive to an optical control signal, and comprises two back to back p-i-n photodiodes each including a quantum well region. The first and second optoelectronic gates are S-SEEDs comprising p-i-n photodiodes also each including a quantum well region. The transmission gate is electrically coupled from a point between the p-i-n photodiodes of the first S-SEED gate to a point between the p-i-n photodiodes of the second S-SEED gate. The transmission gate is responsive to a first level of the optical control signal for substantially blocking current, and to a second level of the optical control signal for substantially passing current.

In a mode referred to as non-cascaded operation, the optical control signal and the optical input signal are applied substantially simultaneously. However, in a cascaded mode of operation, the optical control signal is applied after the optical input signal is applied. When the first optoelectronic gate is implemented as an S-SEED, an optical signal is applied to the first gate during the application of the optical control signal to the transmission gate.

An optical shift register in accordance with the invention comprises N optoelectronic processing gates arranged in sequence and N-1 optoelectronic transmission gates each being electrically interposed between successive ones of the N processing gates, N being a positive integer greater than two. Each processing gate has an optical state controllable by an optical input signal and controllable by an electrical input signal, and generates an electrical signal representative of optical state. Each transmission gate is responsive to an optical control signal and selectively transmits an electrical signal between the successive processing gates. The shift register is responsive to optical control signals applied sequentially to successive transmission gates for shifting information represented by the optical state of one processing gate to successive processing gates of the shift register.

Further illustrative apparatus in accordance with the invention includes a 2.times.1 switch and a 1.times.2 switch. The 2.times.1 switch, which is usable, for example, as a multiplexer or as an exclusive OR gate, comprises first, second, and third optoelectronic gates, and first and second transmission gates. The first optoelectronic gate has a logical state controllable by a first optical input signal and generates a first electrical signal representative of the logical state. The first transmission gate is electrically coupled to the first optoelectronic gate and selectively transmits the first electrical signal. The second optoelectronic gate has a logical state controllable by a second optical input signal and generates a second electrical signal representative of the logical state. The second transmission gate is electrically coupled to the second optoelectronic gate and selectively transmits the second electrical signal. The third optoelectronic gate is electrically coupled to the first and second transmission gates and has an optical state that is controllable by the selectively transmitted first electrical signal, and is controllable by the selectively transmitted second electrical signal.

The 1.times.2 switch, which is usable, for example, as a demultiplexer, also comprises first, second, and third optoelectronic gates, and first and second transmission gates. The first optoelectronic gate has a logical state controllable by an optical input signal and generates an electrical signal representative of the logical state. The first transmission gate is electrically coupled to the first optoelectronic gate and selectively transmits the electrical signal. The second optoelectronic gate is electrically coupled to the first transmission gate and has an optical state that is controllable by the electrical signal selectively transmitted by the first transmission gate. The second transmission gate is electrically coupled to the first optoelectronic gate and selectively transmits the electrical signal generated by the first optoelectronic gate. The third optoelectronic gate is electrically coupled to the second transmission gate and has an optical state that is controllable by the electrical signal selectively transmitted by the second transmission gate.

FIG. 1 is a circuit diagram of an exemplary apparatus in accordance with the invention comprising two optoelectronic signal processing gates and an electrically interposed, optoelectronic transmission gate;

FIG. 2 is a circuit diagram of an illustrative optical shift register in accordance with the invention;

FIG. 3 is a circuit diagram of a further exemplary apparatus usable as a 2.times.1 switch or as a 1.times.2 switch;

FIG. 4 is a timing diagram associated with use of the apparatus of FIG. 3 as a multiplexer;

FIG. 5 is a timing diagram associated with use of the apparatus of FIG. 3 as a demultiplexer;

FIG. 6 is another circuit diagram of the apparatus of FIG. 3 with the signals relabelled for use of the apparatus to perform an exclusive OR logic function; and

FIG. 7 is an alternative embodiment of the apparatus of FIG. 1 where the transmission gate is electronic and responsive to an electrical signal V.sub.c.

FIG. 1 is a circuit diagram of an exemplary embodiment of the invention, comprising two optoelectronic signal processing gates, 101, 102 and an optoelectronic transmission gate 151 electrically connected between gates 101 and 102. In this embodiment gates 101, 102 are implemented using symmetric self electro-optic effect devices (S-SEEDs). The logical state of optical processing gate 101 is represented by an internal voltage V.sub.1, which controls the voltage across the multiple quantum well (MQW) intrinsic regions in the S-SEED of gate 101. Each of the optical gates 101, 102 has one or more optical outputs that also represent the logical state of the device. The logical state of gate 102 is represented by an internal voltage V.sub.2, which controls the voltage across the MQW regions in the S-SEED of gate 102. Thus, the logical states of gates 101, 102 are represented by both electrical and optical states although the optical output beams from gates 101, 102 are not used in the present embodiment. Optoelectronic transmission gate, 151 operates as an open circuit without incident light and as a short circuit with incident light. Several elements are applicable as optical transmission gate 151. Among these are back to back photodiodes, FET phototransistors, bipolar phototransistors, and photoconductors. An electrically controlled transmission gate, e.g. a FET, may also be used as shown in FIG. 7. If the optoelectronic processing gates are SEEDs and if the transmission gate is implemented using back to back quantum well p-i-n diodes, the entire apparatus may be implemented with only one type of device (i.e. MQW diodes), making circuit fabrication simple.

In the present embodiment, optical processing gates 101, 102 are S-SEEDs comprising serially connected p-i-n diodes with quantum wells in the intrinsic region, and transmission gate 151 comprises two back to back p-i-n photodiodes which may be identical to the quantum well diodes used in the S-SEEDs. There are two modes of operation referred to herein as cascaded operation and non-cascaded operation. In cascaded operation, a complementary set of input beams, 104, 114, first sets the state of S-SEED 101. Input beams 104, 114 essentially determine V.sub.1. A set of clock beams, 105, 115, is then applied to S-SEED 101 to provide output beams, 108, 118. Clock beams 105, 115, do not substantially alter the optical state or the voltage V.sub.1 of S-SEED 101. At the same time a set of transfer beams, 109, 119, is applied to transmission gate 151 to transfer the voltage V.sub.1 on the center node of S-SEED 101 to the center node of S-SEED 102. Now V.sub.2 =V.sub.1. In this implementation, if the transfer beams 109, 119, are applied without the clock beams, 105, 115, S-SEED 101 will likely lose its state; however if the optical processing gates are more complex than S-SEEDs and hold their state indefinitely without incident light beams, only the transfer beams would need to be applied. Lastly, a set of clock beams, 106, 116, incident on S-SEED 102 provides a set of output beams, 107, 117, representative of the optical state of S-SEED 102. This operation provides the functional equivalent of cascading optical processing gates. The cascading is not done by routing the optical outputs from one gate to the inputs of the next gate, but is electrical in that the voltage representing the state of the first gate is applied directly to the second gate.

In the non-cascaded mode of operation, transfer beams 109, 119 are applied concurrently with the signal beams incident on S-SEED 101, essentially "shorting" V.sub.1 and V.sub.2 so that the signal beams determine the voltage on V.sub.1 and V.sub.2 at the same time. Subsequently, clock beams 106, 116 are applied to S-SEED 102 to provide output beams 107, 117. Operation in a non-cascaded mode eliminates the need for clock beams 105, 115 and requires only one clock cycle of delay rather than two. However, since both V.sub.1 and V.sub.2 are switched with the input signals 104, 114 in the non-cascaded mode of operation, more input signal energy is required. The specific application determines whether cascaded or non-cascaded operation is preferable.

The operation of optoelectronic transmission gates may be better understood by considering their application in several exemplary optical systems. As a first example, consider an optical shift register comprising N optical processing gates with N-1 transmission gates as illustrated in FIG. 2. Operation of the shift register is an extension of the cascaded operation described above. As above, first the input beams 104, 114 set the state of S-SEED 101. Clock beams 105, 115 and transfer beams 109, 119 are then applied transferring the data from S-SEED 101 to S-SEED 102. Clock beams 106, 116 and transfer beams 110, 120 are subsequently applied and the data is transferred to S-SEED 103. This process continues until the data is transferred to the last S-SEED 160 in the shift register. Like other shift registers, half of the data transfers take place during one half clock cycle and the other half take place during the complement half clock cycle. Thus clock beams 106, 116 are complements of clock beams 105, 115; transfer beams 110, 120 are complements of transfer beams 109, 119. Data can be read in or out in parallel to every other S-SEED thereby performing serial to parallel or parallel to serial conversion.

Note that the shift register can shift data from left to right as described above by having the odd (even) numbered transfer beams applied concurrently with the odd (even) numbered clock beams. The shift register can shift data from right to left by having the odd (even) numbered transfer beams applied concurrently with the even (odd) numbered clock beams.

As a second example, consider the 2.times.1 switch shown in FIG. 3. The switch can be operated in either a cascaded or non-cascaded mode. S-SEEDs 201, 202 act as input S-SEEDs for two sets of input signals, signal set 1 (231,241) and signal set 2 (232,242). These signals set the state of S-SEEDs 201, 202 and thus voltages V.sub.1 and V.sub.2. If transfer beam set 1 (214,224) is applied to transmission gate 204 while clock beam set 1 (211,221) is applied to S-SEED 201, (and optionally clock set 2 (212,222) is applied to S-SEED 202), V.sub.3 =V.sub.1. Similarly, if transfer beam set 2 (215,225) is applied to transmission gate 205 while (optionally clock beam set 1 (211,221) is applied to S-SEED 201), and clock set 2 (212,222) is applied to S-SEED 202, V.sub.3 =V.sub.2. Thus, one of two inputs is selected; the apparatus operates as a 2.times.1 switch.

The transmission gates are also operable in a non-cascaded mode thus eliminating the need for clock beam sets 1 (211,221) and 2 (212,222). To select input set 1, transfer beam set 1 (214,224) is turned on and transfer beam set 2 (215, 225) is turned off, essentially shorting V.sub.1 and V.sub.3. At the same time, signal set 1 (231,241) is applied to set V.sub.1 and V.sub.3 concurrently. Even though signal set 2 (232, 242) may also have been applied, because transfer beam set 2 (215,225) was turned off, signal set 2 does not effect V.sub.3. Clock beams 213, 223 are then applied to S-SEED 203 to read the output state of the 2.times.1 switch.

The functionality of a 1.times.2 switch is obtained by operating the 2.times.1 switch in reverse; in cascaded operation, signal set 3 (233,243) is applied to S-SEED 203, transfer set 1 or transfer set 2 is applied to transfer the data to either S-SEED 201 or 202, and the appropriate clock set 1 or 2 is applied. This 1.times.2 switch can be operated in a non-cascaded mode as well.

Any arbitrary interconnection network may be obtained from 2.times.1 switches. For medium to large networks, operation should be in a cascaded mode; otherwise the voltage on many nodes must be changed at once. For non-cascaded operation, the capacitance associated with each node requires larger energies of the signal beams, although there would only be one clock cycle of delay through the entire network. For cascaded operation, the capacitance associated with each node is only slightly greater than that of a single S-SEED. Accordingly, smaller signal beam energies are required and there are N clock cycle delays through an N stage interconnection network. A four-directional shift register may also be obtained from the 1.times.2 and 2.times.1 switches; operation should be in a cascaded mode.

The 2.times.1 and 1.times.2 switches may be extended to N.times.1 and 1.times.N switches. An N.times.1 time multiplexer (mux) and a 1.times.N demultiplexer (demux) may also be obtained. This is illustrated for a 2.times.1 mux and 1.times.2 demux. For a 2.times.1 mux, the input and output beams are the same as the input and output beams for a 2.times.1 switch; however, the timing is different. A timing diagram is shown in FIG. 4. In operation, the two signal sets 1 and 2 are applied sequentially. (If the two input signal sets are received concurrently, one of the sets may be clocked through an additional S-SEED.) First input signal set 1 is applied. During the first half of the interval when signal set 1 is applied, transfer set 1 is also applied, thus setting V.sub.3 to the voltage determined by signal set 1. During the second half of this half clock cycle, output clock set 3 (213,223) is turned on to produce an output representative of the data from input signal set 1. Then input signal set 2 is applied. During the first half of the interval where signal set 2 is applied, transfer set 2 is also applied, thus setting V.sub.3 to the voltage determined by signal set 2. During the second half of this half clock cycle, output clock set 3 is turned on to produce an output representative of the data from input set 2. Considering the output set 3 (253,263) produced in response to clock set 3, the odd numbered bits are representative of the data from input set 1 and the even numbered bits are representative of the data from input set 2. The data rate is twice that of each incoming bit stream.

A 2.times.1 demux may be obtained using the apparatus of FIG. 3 by applying timing signals in accordance with the timing diagram of FIG. 5. In this application, there is only one set of input signal beams (input set 3; 233, 243) incident on S-SEED 203; every odd bit is transmitted to S-SEED 201 and every even bit is transmitted to S-SEED 202. When the first input bit is present on S-SEED 203, transfer beam set 1 is turned on, thus setting V.sub.1 and V.sub.3 equal to the voltage determined by that first input bit. Then clock beam set 1 is turned on and transfer beam set 1 is turned off; the state of S-SEED 201 is thereby made the same as the state of S-SEED 203. When the second input bit is present on S-SEED 203, transfer beam set 2 is turned on, thus setting V.sub.2 and V.sub.3 equal to the voltage determined by that second bit. Then clock beam set 2 is turned on and transfer beam set 2 is turned off; the state of S-SEED 202 is thereby made the same as the state of S-SEED 203. Note that the two outputs are sequential, not concurrent; the outputs can be made concurrent by passing one output through an addition S-SEED.

A further application of the apparatus of FIG. 3 is as an exclusive OR gate implementing the logical function C=AB,+AB. The logical output of an exclusive OR is one if the two inputs differ and zero if the two inputs are the same. Input signal beams 231, 242 (FIG. 3) are set equal to A (FIG. 6). Input signal beams 232, 241 (FIG. 3) are set equal to A (FIG. 6). Transfer beams 214, 224 (FIG. 3) are set equal to B (FIG. 6). Transfer beams 215, 225 (FIG. 3) are set equal to B (FIG. 6). Only clock beams 213, 223 are used; output beam 263 is equal to C and output beam 253 is equal to C. A variety of other logic functions may be implemented using this technique.

The preceding arrangements using optical transmission gates to interconnect optical processing gates differ from known arrangements using electrical transmission gates to interconnect electrical processing gates. In the electrical domain, specific logic levels are defined. In the electrooptic circuits, specific voltage levels are defined as well; however, the logic decisions are based upon the ratios of the optical input powers, not the absolute levels. Because the gain mechanism in electronics is different than in the optical implementation, different noise margins and fan-out/fan-in requirements are applicable. The use of optics eliminates clock skew since all clock beams are applied perpendicular to the circuit. In electronics, the clock beams propagate in the plane of the circuits. As stated previously, the optoelectronic circuits allow the use of short pulses for the clock beams, leading to faster processing than would be possible with electronics alone.

It is to be understood that the above-described embodiments are merely illustrative of the principles of the invention and that many variations may be devised by those skilled in the art without departing from the spirit and scope of the invention. It is therefore intended that such variations be included within the scope of the claims.