Signal Switching Circuit and Signal Change-Over Circuit Using the Same

The present invention relates to a signal switching circuit usable in a system including various logical circuits and a signal change-over circuit using such a signal switching circuit or circuits.

FIG. 1 shows a typical signal change-over circuit heretofore employed. In this circuit logical signals S.sub.1, S.sub.2, . . . , S.sub.n output from a plurality of logical circuits 10.sub.1, 10.sub.2, . . . , 10.sub.n are provided via transmission lines 12.sub.1, 12.sub.2, . . . , 12.sub.n to logic gate circuits 20.sub.1, 20.sub.2, . . . , 20.sub.n at one input thereof in a selector circuit 200. The logic gate circuits 20.sub.1 through 20.sub.n are supplied at the other inputs with control signals C.sub.1 through C.sub.n for enabling and disabling them. A desired one of the logic gate circuits 20.sub.1 to 20.sub.n is enabled by one of the control signals C.sub.1 to C.sub.n to select a desired one of the logical signals S.sub.1 to S.sub.n, which is provided to an output terminal 40 via an OR gate 30. Each signal path, which comprises, for example, the logical circuit 10.sub.1, the transmission line 12.sub.1 and the logic gate circuit 20.sub.1, constitutes a signal switching circuit 100.sub.1.

Such a signal change-over circuit is also referred to as a multiplexer and can be used, for example, to output a selected one of clock signals of different frequencies from a plurality of clock signal sources.

The logic gate circuits 20.sub.1 to 20.sub.n which open and close the gate for the logical signals, are not limited specifically to the NAND gates shown in FIG. 1 but may also be various other gate circuits. An ordinary gate circuit is able to control passage of a signal of a frequency between 50 to 70 MHz or so. However, in the case of handling a signal of a frequency higher than 100 MHz, for example, even if the gate circuit is closed, the input signal leaks to the output side of the gate circuit and the leakage level is so high as not to be negligible. That is, in the conventional signal change-over circuit depicted in FIG. 1, for instance, even if the NAND gate circuit 20.sub.1 is held disabled by the control signal C.sub.1, the logical signal S.sub.1 from the transmission line 12.sub.1 leaks to the output side of the NAND gate 20.sub.1 and interferes with other selected logical signals in the OR gate 30.

Further, in the signal change-over circuit shown in FIG. 1 the logical signals S.sub.1 to S.sub.n from the logical circuits 10.sub.1 to 10.sub.n are always present on the transmission lines 12.sub.1 to 12.sub.n regardless of the ON/OFF state of the gate circuits 20.sub.1 to 20.sub.n. This poses another problem as the logical signals S.sub.1 to S.sub.n on the lines 12.sub.1 to 12.sub.n interfere with one another as their frequencies rise.

It is therefore an object of the present invention to provide a signal switching circuit which is free from the leakage of signals even if their frequencies are high.

Another object of the present invention is to provide a signal change-over circuit which employs a plurality of such signal switching circuits and is free from interference of signals between a plurality of transmission lines.

According to an aspect of the present invention, the signal switching circuit has an arrangement in which a transmission line is connected in series to the emitter of an output transistor of an emitter-coupled logical circuit which provides a logical signal, and switching diode means is connected in series to the output end of the transmission line. The switching diode means is turned ON and OFF by bias control means which responds to a control signal. In the ON state the switching diode means permits the passage therethrough of the logical signal from the transmission line but in the OFF state it cuts off current, cutting off the emitter current of the output transistor of the emitter-coupled logical circuit. Thus, since no logical signal is provided on the transmission line from the emitter-coupled logical circuit when the switching diode means is in the OFF state, there is no possibility of the leakage of the logical signal through the switching diode means.

Where a signal change-over circuit is formed by a plurality of such signal switching circuits, emitter currents of output transistors of emitter-coupled logical circuits cannot flow into the transmission lines connected to the switching diode means held in the OFF state by the control signals, and consequently no logical signals are provided on the transmission lines. Thus, no interference of signals between the transmission lines will occur.

According to another aspect of the present invention, the signal switching circuit is made up of a transmission line connected at one end to the emitter output of an emitter-coupled logical circuit which outputs a logical signal, gate means connected at one input to the other end of the transmission line and supplied at the other input with a control signal for enabling and disabling it, and level holding means which is supplied with the control signal and, when the control signal is in the logical state of disabling the gate means, produces a high-level output to thereby hold the one input of the gate at the high level regardless of the logical signal.

With such a signal switching circuit, when the gate means is disabled by the control signal, the level holding means which is supplied with the same control means yields a high-level output, by which the input of the gate means connected to the transmission line is held at the high level. This is essentially equivalent to the state in which no logical signal is provided from the emitter output of the emitter-coupled logical circuit, and hence no logical signal will leak through the gate means being disabled.

Where a signal change-over circuit is formed using a plurality of such signal switching circuits, transmission lines connected to the inputs of the gate means which are being disabled by control signals are all held at the high level, and consequently no logical signals are present on the transmission lines. Thus, no signal interference will occur between the transmission lines.

FIG. 1 is a circuit diagram of a typical signal change-over circuit heretofore employed;

FIG. 2 is a block diagram of a signal change-over circuit formed by a plurality of signal switching circuits produced according to an embodiment of the present invention;

FIG. 3 is a block diagram of a signal change-over circuit formed using signal switching circuits produced according to another embodiment of the present invention;

FIG. 4 is a circuit diagram of another embodiment of the signal switching circuit of the present invention;

FIG. 5 is a circuit diagram of a modified form of the output side of the signal switching circuit shown in FIG. 4;

FIG. 6 is a circuit diagram of another embodiment of the signal switching circuit of the present invention;

FIG. 7 is a circuit diagram of another embodiment of the signal switching circuit according to the invention;

FIG. 8 is a circuit diagram of still another embodiment of the signal switching circuit; and

FIG. 9 is a circuit diagram of a signal change-over circuit using a plurality of signal switching circuits depicted in FIG. 8.

FIG. 2 illustrates a signal change-over circuit (a multiplexer) formed by a plurality of signal switching circuits produced according to an embodiment of the present invention. The signal switching circuit 100.sub.1 includes an emitter-coupled logical circuit (hereinafter referred to as an ECL circuit) 10.sub.1, a transmission line 12.sub.1 and a gate circuit 20.sub.1. In addition to the signal switching circuit 100.sub.1 a plurality of signal switching circuits 100.sub.2 through 100.sub.n identical in construction therewith are provided, and the outputs of these signal switching circuits 100.sub.1 through 100.sub.n, are connected to an OR gate 30 serving as a coupling means, thus constituting the signal change-over circuit.

The ECL circuit 10.sub.1 constitutes a signal source which generates a logical signal S.sub.1 of a high-speed pulse, and the emitter of its output transistor 10A is connected in series to the transmission line 12.sub.1 of a characteristic impedance Z.sub.0 (50 .OMEGA., for instance). High-level and low-level voltages V.sub.H and V.sub.L of the logical signal S.sub.1 which is generated by the ECL circuit 10.sub.1 are, for example, -0.8 and -1.7 V, respectively, and the corresponding emitter currents I.sub.EH and I.sub.EL of the output transistor 10A are, for instance, 23 and 6 mA, respectively. The output end of the transmission line 12.sub.1 is connected to the anode of a switching diode 21 of the gate circuit 20.sub.1. The gate circuit 20.sub.1 comprises: a pair of series-connected switching diodes 21 and 22 which have their cathodes interconnected and the former of which has its anode connected to the transmission line 12.sub.1 ; a parallel switching diode 23 which is connected between the common connection point A of the series-connected switching diodes 21 and 22 and the common potential point, in a direction in which the anode of the diode 23 is connected to the common connection point A; a bias supply circuit 24 by which the series-connected switching diodes 21 and 22 are reversely biased (turned OFF) and the parallel switching diode 23 is forwardly biased (turned ON); a current pull-in control circuit 27 which pulls in current from the series-connected switching diodes 21 and 22 and turns them ON and the parallel switching diode 23 OFF; an impedance matching resistor 14 connected to the anode side of the switching diode 22; and a power supply V.sub.T which, when in the ON state, supplies an ON current via the matching resistor 14 to the switching diode 22 and, when in the OFF state, holds an output side transmission line 13 at a fixed potential. The diodes 21, 22 and 23 are high-frequency diodes of small junction capacitance.

The current pull-in control circuit 27 is a made up of, for example, a switching element 25 and a constant-current source 26. For example, when the control signal C.sub.1 is high-level, the switching element 25 connects therethrough the constant-current source 26 to the common connection point A side of the diodes 21 and 22, and the constant-current source 26 pulls in a constant current Ic, for example, 30 mA from the common connection point A, and hence pulls in the current through the series-connected switching diodes 21 and 22 and turns them ON. On the other hand, the parallel switching diode 23 is turned OFF, because no current can be pulled in therefrom. As a result of this, the gate circuit 20.sub.1 conducts and the output signal S.sub.1 from the ECL circuit 10.sub.1 is provided via the series-connected switching diodes 21 and 22 to the transmission line 13 at the output side of the gate circuit 20.sub.1 and is then supplied to the OR circuit 30 which forms coupling means. The ON-state current of the switching diode 21 is the emitter current from the output transistor 10A of the ECL circuit 10.sub.1, and the ON-state current of the switching diode 22 is supplied from the -0.5-volt power supply V.sub.T via the 50-ohm matching resistor 14. Since the constant-current source 26 pulls in the 30-mA current in this example, the ON-state current of the switching diode 22 is I.sub.OH =6 mA and I.sub.OL =24 mA when the logical signal S.sub.1 is high- and low-level, respectively. The ON state of the switching diodes 21 and 22 is equivalent to the connection of the emitter of the output transistor 10A of the ECL circuit 10.sub.1 to a -2-volt normal termination voltage V.sub.TT via the 50-ohm resistor, and circuit constants are designed so that they bear the following relationships:

Conversely, when the control signal C.sub.1 to the switching element 25 is low-level, the constant-current source 26 is grounded, and by the bias supply circuit 24, the series-connected switching diodes 21 and 22 are reversely biased and the parallel switching diode 23 is forwardly biased. The power source +V and the resistance of the bias supply circuit 24 are 15 volts and 15 kilohms, for example. Consequently, the series-connected switching diodes 21 and 22 are turned OFF to disable the gate circuit 20.sub.1 and the parallel switching diode 23 is turned ON. In this instance, since no current flows through the series switching diodes 21 and 22 when they are OFF, no emitter current flows in the output transistor 10A of the ECL circuit 10.sub.1 connected to them via the transmission line 12.sub.1. That is, the logical signal S.sub.1 is not provided on the transmission line 12.sub.1 from the output transistor 10A. Even if a low-level signal corresponding to the signal S.sub.1 is provided on the transmission line 12.sub.1 due to a leakage in the output transistor 10A, it cannot pass through the gate circuit 20.sub.1 because the series switching diodes 21 and 22 are in the OFF state.

In this way, the gate circuit 20.sub.1 connects and disconnects the signal transmission lines 12.sub.1 and 13 in accordance with the ON/OFF state of the switching element 25. In practice, the operation of the constant-current source 26 is placed directly under ON/OFF control of the control signal C.sub.1, that is, the switching element 25 is not used, and the constant-current source 26 is connected directly to the common connection point A. The voltage source V.sub.T connected to the matching resistor 14 of the gate circuit 20.sub.1 is not always needed but instead the end of the impedance matching resistor 14 may be connected to the common potential point.

In this embodiment, since the switching diodes 21 and 22 are connected in series between the signal transmission lines 12.sub.1 and 13, the overall junction capacitance of the diodes 21 and 22 in their OFF state is one-half that in the case of one diode being connected between the transmission lines 12.sub.1 and 13, and consequently the leakage of signal can be reduced.

Besides, since the switching diode 23 is turned ON to permit conduction between the signal transmission lines 12.sub.1 and 13 and the common potential point, a signal which tends to leak through the junction capacitance formed by the series-connected switching diodes 21 and 22 is by-passed via the switching diode 23. Thus, even if a signal is provided on the transmission line 12.sub.1 due to leakage or interference when the gate circuit 20.sub.1 is OFF, the leakage of signal to the output side of the gate circuit 20.sub.1 is very small.

In a signal change-over circuit (or multiplexer), a plurality of such signal switching circuits are provided and their outputs are connected to the OR circuit 30 as shown in FIG. 2, since the series-connected switching diodes 21 and 22 of the gate circuits in unselected signal switching circuits are turned OFF, their ECL circuits do not output logical signals. Accordingly, there is no signal interference from the transmission lines of the unselected signal switching circuits to the transmission line of the selected signal switching circuit. For example, when the signal switching circuit 100.sub.1 is selected, even if the signal S.sub.1 provided on the transmission line 12.sub.1 applies an interference signal to the transmission line of an unselected signal switching circuit, for example, the adjacent transmission line 12.sub.2 of the signal switching circuit 100.sub.2, the signal leakage level from its gate circuit 20.sub.2 to the output side thereof is negligibly small.

FIG. 3 illustrates another embodiment of the signal switching circuit of the present invention, which is also shown to be used in the signal change-over circuit. In this embodiment the current pull-in control circuit 27 of the gate circuit 20.sub.1 does not employ the constant-current source but instead it is arranged to pull in current from the common connection point A to a power source (V.sub.TT -V.sub.D) via a series connection of the impedance matching resistor 14 and a transistor switching element 25. V.sub.D is the junction voltage of the switching diodes 21 and 22 and is about 0.8 volts, for example. The connection point of the matching resistor 14 and the switching element 25 is grounded via a capacitance 28 in AC-wise. This pull-in current is liable to vary with variations in electrical properties of parts forming the entire circuit and their temperature dependence, and differs with the high and low levels of the logical signal S.sub.1 on the transmission line 12.sub.1, and hence the level of the output logical signal is not very accurate, but this circuit structure is low-cost since no constant-current source is employed. In this embodiment output lines 13.sub.1 through 13.sub.n of the signal switching circuits 100.sub.1 through 100.sub.n of the same construction are coupled by a wired OR and a logical signal is provided via a buffer gate 60. A resistor 15 for supplying an ON-state current to the diodes 22 of the gate circuits 20.sub.1 through 20.sub.n is provided in common thereto and its resistance value is selected sufficiently higher than that of the matching resistor 14, for example, about 10 times high than the latter. The signal switching circuit 100.sub.1 is identical in construction with that shown in FIG. 2, except the above.

FIG. 4 illustrates another embodiment of the signal switching circuit of the present invention, in which the signal switching circuit 100.sub.1 depicted in FIG. 2 is formed as a differential signal switching circuit. In this embodiment the ECL circuit 10 outputs a logical signal S and an inverted logical signal S from a differential output circuit 10C via output transistors 10A and 10B, respectively, and these logical signals S and S are input into gate circuits 20a and 20b via lines 12a and 12b, respectively. The outputs of the gate circuits 20a and 20b are connected to a power source V.sub.T via matching resistors 14a and 14b of a characteristic impedance Z.sub.0, and in this example, the output of the gate circuit 20a is provided. The gate circuits 20a and 20b are each identical in construction and in operation with the gate circuit 20.sub.1 depicted in FIG. 2. The operations of constant-current sources 26a and 26b of current pull-in control circuits 27a and 27b are turned ON and OFF by the same control signal C. The transmission lines 12a and 12b constitute a so-called twisted pair line 12 of a characteristic impedance Z.sub.0, and lines 13a and 13b also form a twisted pair line 13. By transmitting the differential logical signals S and S over the twisted pair lines 12 and 13, noise which is generated by current variations in the both transmission lines is cancelled between them. Where it is desired to provide both of the differential signals S and S to the stage following the signal switching circuit shown in FIG. 4, the output side of circuit points 16a and 16b need only to be constructed as depicted in FIG. 5. That is, the output ends of the transmission lines 13a and 13b are connected to the power source V.sub.T via the matching resistors 14a and 14b, respectively, and at the same time, they are connected to a differential buffer amplifier 60 so that the logical signals S and S are provided at its non-inverting output and inverting output, respectively. A signal change-over circuit can be formed by providing a plurality of signal switching circuits 100 shown in FIG. 4 and by applying their outputs to the OR circuit 30 as depicted in FIG. 2. It is also possible to provide a plurality of structures from the ECL circuit 10 to the circuit points 16a and 16b shown in FIG. 4 and to couple the corresponding circuit points 16a and 16b by a wired OR circuit as shown in FIG. 3.

FIG. 6 illustrates another embodiment of the signal switching circuit of the present invention, in which the signal switching circuit 100.sub.1 depicted in FIG. 3 is formed as a differential signal switching circuit. Also in this embodiment the ECL circuit 10 outputs the logical signals S and S from the differential output circuit 10C via the output transistors 10A and 10B, and the signals S and S are applied via the twisted pair line 12 to the gate circuit 20 as is the case with the embodiment shown in FIG. 4. The gate circuit 20 has the same structure as that of the gate circuit 20.sub.1 depicted in FIG. 3 but includes a series connection of another switching diode 21b and another matching resistor 14b. The anode of the switching diode 21b is connected to the output end of the transmission line 12b and the matching resistor 14b is connected to the junction of the switching element 25 and the matching resistor 14a. With such an arrangement, when the switching element 25 is turned ON by the control signal C, current is pulled in toward the power source V.sub.TT -V.sub.D via the switching diodes 21a, 21b and 22, turning them ON but OFF the diode 23. Conversely, when the switching element 25 is turned OFF by the control signal C, the diode 23 is turned ON by the bias current supply circuit 24, whereas the diodes 21a, 21b and 22 are turned OFF. A signal change-over circuit can be formed by a plurality of signal switching circuits 100 shown in FIG. 6 and by coupling their outputs with a wired OR circuit as depicted in FIG. 3.

FIG. 7 illustrates a modified form of the embodiment of FIG. 6, in which the differential logical signals S and S are applied to the next-stage circuit. In this embodiment the gate circuit 20 has an arrangement in which the switching diodes 21a, 22a and 23a and the matching resistor 14a are provided in association with the transmission line 12a and the switching diodes 21b, 22b and 23b and the matching resistor 14b are provided in association with the transmission line 12b. The output of the gate circuit 20 is provided via the transmission lines 13a and 13b to the differential buffer amplifier 60, from which the logical signals S and S are delivered. A signal change-over circuit can be formed by a plurality of such signal switching circuits 100 and a wired OR circuit by which the corresponding circuit points 16a and 16b are coupled.

FIG. 8 illustrates still another embodiment of the signal switching circuit 100 of the present invention. The ECL circuit 10 yields a desired logical signal S via the emitter of the output transistor 10A. The logical signal S is provided to one end of the transmission line 12 of a characteristic impedance Z.sub.0. The other end of the transmission line is connected to the one input of an AND gate 21 in the gate circuit 20, and the control signal C is applied to the other input of the AND gate 21 for controlling its ON/OFF operation. The control signal C is also applied to an inverter 22 formed by, for example, an ECL circuit. The output of the inverter 22 is connected to the output end of the transmission line 12, forming a wired OR circuit. The one input of the AND gate 21 is further connected via a matching resistor 23 of a characteristic impedance Z.sub.0 to a termination voltage source V.sub.TT.

When the control signal C is high-level, the AND gate 21 is enabled. At this time, the inverter 22 yields a low-level output, which is ORed with the logical signal S from the transmission line 12, and as a result, the logical signal S is applied intact to the one input of the AND gate 21 and is output therethrough. When the control signal C is low-level, the AND gate 21 is disabled. At this time, the inverter 22 provides a high-level output, which is ORed with the logical signal S from the transmission line 12, and as a result, the one input of the AND gate 21 is held high regardless of the logical signal S. Since the AND gate 21 is being disabled, the high-level output does not pass through the gate 21. Since the output end of the transmission line 12 and the output side of the inverter 22 are coupled in a wired OR form, the transmission line 12 is also held high by the high-level output of the inverter 22.

As described above, when the signal switching circuit is in the logical state in which the control signal C disables the gate 21, the inverter 22 produces the high-level output to hold high-level the input side of the gate 21 connected to the transmission line 12 regardless of the logical signal S, inhibiting the application of the logical signal S to the input of the gate 21. Thus, even if the frequency of the logical signal S rises, there is no possibility of leakage of the logical signal S to the output side of the gate 21.

FIG. 9 illustrates an example in which a signal change-over circuit is formed by a plurality of signal switching circuits of the same construction as the circuit shown in FIG. 8. That is, n signal switching circuits 100 are provided and the outputs of AND gates 21.sub.1 to 21.sub.n of their gate circuits 20.sub.1 to 20.sub.n are connected to an OR circuit 30. The OR circuit 30 is provided for supplying the outputs of the gate circuits 20.sub.1 to 20.sub.n and it may also be a simple wired OR circuit. Each signal switching circuit is exactly identical in construction with the circuit shown in FIG. 8, hence is exactly identical in operation, too.

When a desired one of control signals C.sub.1 to C.sub.n for the gates circuits 20.sub.1 to 21.sub.n, for example, C.sub.1 is made high-level, the AND gate 21 supplied with the control signal C.sub.1 is enabled to permit the passage therethrough of the corresponding logical signal S.sub.1. Since the other control signals C.sub.2 to C.sub.n are held low-level, the AND gates 21 of the gate circuits 20.sub.2 to 20.sub.n remain disabled, and consequently, the logical signals S.sub.2 to S.sub.n do not leak to the outputs of the gate circuits 20.sub.2 to 20.sub.n as described above with respect to FIG. 8. Thus, only the selected logical signal S.sub.1 is provided as the output of the signal change-over circuit to the output terminal 40 via the OR circuit 30. In addition, the transmission lines 12.sub.2 to 12.sub.n associated with the AND gates 21 which are supplied with the low-level control signals C.sub.2 to C.sub.n are all held high-level as described previously, and the logical signals S.sub.2 to S.sub.n are not essentially present on the transmission lines 12.sub.2 to 12.sub.n. Accordingly, there is no possibility of interference of the unselected logical signals S.sub.2 through S.sub.n to the selected logical signal S.sub.1 between the transmission lines 12.sub.1 to 12.sub.n.

As described above, according to the signal switching circuit of the present invention, since the closing of the gate circuit 20 by the control signal C prevents the application of the logical signal S from the ECL circuit 10 to the transmission line 12, the logical signal S will not leak to the output side of the gate circuit 20. Moreover, in the case where a signal change-over circuit is formed by a plurality of such signal switching circuits, no interference of logical signals will occur between the transmission lines 12.

It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of the present invention.