System for Controlling Data Transfer Using Transfer Handshake Protocol Using Transfer Complete and Transfer Inhibit Signals

1. Field of the Invention

The present invention relates to data processing systems and more particularly to a method and apparatus for controlling data transfers between first and second information processing elements within a data processing system.

2. Description of the Relevant Art

Data transfers frequently are initiated by a first or a second information processing element, such as a central processing unit (CPU) or an I/O channel, by one information processing element signaling the other that a data transfer is requested. The device which receives the request then signals that it is ready to make the transfer, the transfer occurs, and the requesting device sends an acknowledgment of completion of the transfer. Finally, the device which received the request for transfer acknowledges that its operation is also complete. Although this is an effective serial "handshake" method for controlling the transfer of data between two information processing elements, the sending device must await the acknowledgment from the receiving device before it attempts another transfer. This wastes time, especially when the sending device must perform other tasks and may be busy when the acknowledgment occurs.

The present invention is directed to an apparatus for controlling data transfer handshake protocol so that certain protocol events may occur prior to or simultaneously with the completion of a preceding protocol event, and the ultimate result of the pending protocol event may be determined at a later time. In one embodiment of the present invention directed to data transfers between a central processing unit and an I/O channel, the CPU operates to transfer data (either receive or send) between itself and the I/O channel every five processor clock cycles. At the beginning of each set of five clock cycles, the CPU places data on the data bus (or, if receiving data, assumes data is on the data bus) and generates a transfer request (CPU-XFR) signal. If it receives a data accepted (DATA-ACC) signal it anticipates that a previous data transfer has completed. The CPU-XFR signal is generated regardless of whether or not the previous data transfer actually is complete at the time.

In the embodiment described the previous data transfer normally is completed one clock cycle after the transfer request signal is generated, and at that time a transfer complete signal is generated. If the transfer complete signal is not generated a transfer inhibit signal is generated for inhibiting the generation of the succeeding DATA-ACC signal (and hence the next CPU-XFR signal) so that the CPU may determine the cause of noncompletion and either abort or retry the previously attempted data transfer.

FIG. 1 is a block diagram of a CPU and I/O channel according to the present invention.

FIG. 2 is a flowchart illustrating data transfer protocol according to the present invention.

FIG. 3 is a schematic diagram of a circuit for controlling data transfers according to the present invention.

FIG. 4 is a diagram illustrating Phase A and Phase B pulses used with the circuit of FIG. 2.

FIG. 5 is a timing diagram illustrating normal operation of the apparatus of FIG. 2.

FIG. 6 is a timing diagram illustrating operation of the circuit of FIG. 2 when a data transfer is inhibited.

FIG. 1 is a block diagram of an apparatus according to the present invention wherein data is transferred between a CPU 4 and an I/O channel 8 over a data bus 12. Data in turn is transferred between I/O channel 8 and an I/O device 16 through an I/O bus 20. For controlling data transfer between CPU 4 and I/O channel 8. CPU 4 communicates a transfer request (CPU-XFR) signal to I/O channel over a line 22, and I/O channel 8 communicates a data accepted (DATA-ACC) signal to CPU 4 over a line 23.

FIG. 2 illustrates the normal sequence of operation when CPU 4 transfers data to or from I/O channel 8. As shown in FIG. 2. I/O channel 8 requests an interrupt from CPU 4 in a step 32, and CPU 4 grants the interrupt in a step 34. Following the interrupt grant. CPU 4 initializes the appropriate control registers in the I/O channel 8 in a step 38. CPU 4 then places a block of data to be transferred on data bus 12 and makes a transfer request in a step 42. At this time the CPU resumes other tasks in a step 46 until it is time to perform the next transfer in the sequence. In this embodiment a transfer is attempted after every five processors clock cycles. If it is ascertained in a step 50 that the data transfer has been accepted by the I/O channel (which indicates that another transfer may proceed). and if it is ascertained in a step 54 that there is more data to transfer, then the CPU 4 places the next block of data on data bus 12 and indicates that a transfer is to occur in step 42. If it was ascertained in step 50 that data was not accepted by the I/O channel, then CPU 4 performs an error routine designated for the situation in a step 58. At this time CPU 4 may abort the data transfer operation, retry the previous transfer, or proceed with a new transfer. After the error routine is performed and/or after there is no more data to transfer, processing resumes in a step 62.

FIG. 3 is a schematic diagram of a control circuit 70 according to the present invention. Circuit 70 preferably is located within I/O channel 8, although that is not necessary. Circuit 70 receives the CPU-XFR signal from CPU 4 on line 22 indicating that a transfer is to occur, and CPU 4 receives a DATA-ACC signal on line 23 indicating whether or not the previous transfer was successful. Additionally, circuit 70 generates well known service out (SVO) signals to the I/O devices over line 71 and receives well known service in (SVI) signals from the I/O devices on a line 72.

In the discussion which follows, a "Phase A" latch is a conventional latch which is enabled by the positive or high-going portion of the Phase A pulse train illustrated in FIG. 4. Similarly, a "Phase B" latch is a conventional latch which is enabled by the positive or high going portion of the Phase B pulse train illustrated in FIG. 4. The Phase A and Phase B pulse trains may comprise any set of interleaved and nonoverlapping pulse trains wherein each Phase A positive pulse alternates with each Phase B positive pulse.

Circuit 70 receives the CPU-XFR signal and stores the signal in a Phase B latch 74 which in turn communicates the signal to a programmed logic array 78 for decoding. In the preferred embodiment, the CPU-XFR signal is actually several unique decodings of a larger set of coded control signals received from CPU 4. The decoded signal then is communicated to a Phase A latch 82 for producing a CTL-SVO-CLR signal on line 84, a CTL-SVO-SET signal on line 86, and a CTL-CLR signal on line 90. The CTL-SVO-CLR signal may be used for clearing the SVO signal when CPU 4 issues a transfer request which does not require a handshake, or when for some other reason I/O device 8 does not respond with an SVI signal.

The CTL-SVO-CLR signal is communicated to an inverting input terminal of an AND gate 94 as is the SVI-LCH signal on line 104, and the noninverting input terminal of AND gate 94 is connected for receiving an SVO signal on a line 96. The CTL-SVO-SET signal is communicated to the noninverting input terminal of an AND gate 100. The inverting input terminal of AND gate 100 is connected for receiving an SVI-LCH signal on a line 104 for reasons discussed below. The signals from AND gates 94 and 100 are communicated to an OR gate 106 the output terminal of which is connected to a Phase B latch 110. Phase B latch 110 communicates an SVO-ENA signal on a line 114 to a Phase A latch 118, to a NOR gate 120 and to program logic array 78. Phase A latch 118 communicates the SVO-ENA signal as an SVO signal to AND gate 94 on line 96 and to I/O devices 16 on line 71.

Circuit 70 receives an SVI signal from I/O devices 16 on line 72 wherein it is stored in a Phase B latch 124. Phase B latch 124 in turn communicates the SVI signal as an SVI-LCH signal on line 104. The SVI-LCH signal is communicated to the noninverting input terminal of AND gate 100, to an inverting input terminal of AND gate 94, and to one of the input terminals of an AND gate 132. The other input terminal of AND gate 132 is connected for receiving the CTL-SVO-SET signal from line 86.

Another AND gate 134 has its inverting input connected for receiving the CTL-CLR signal from line 90. The noninverting input of AND gate 134 receives an N-XFR-OK-LCH signal on a line 138. The output terminals from AND gates 132 and 134 are connected to the input terminals of an OR gate 140 which in turn has its output terminal connected to a Phase B latch 144. Phase B latch 144 communicates the signals so received as an N-XFR-OK signal on a line 148 to a Phase A latch 150, to NOR gate 120 and to program logic array 78. Phase A latch 150 communicates the N-XFR-OK signal to AND gate 134 as N-XFR-OK-LCH on line 138.

Normal operation of circuit 70 may be understood by referring to FIGS. 3 and 5. Circuit 70 receives the CPU-XFR signal on line 22 and, if DATA-ACC is high (indicating the previous transfer was successful). CPU-XFR is decoded to produce a high CTL-SVO-SET signal on line 86 at the leading edge of pulse 2A. Since the SVI-LCH signal on line 104 ordinarily is low at this time, a high signal appears at the output of AND gate 100 which is communicated through OR gate 106 and to the input terminal of Phase B latch 110. At the leading edge of pulse 2B. the high signal from OR gate 106 is communicated to line 114 as a high SVO-ENA signal. At the leading edge of pulse 3A. the high SVO-ENA signal appears as a high SVO signal on lines 71 and 96 and as a low DATA-ACC signal on line 23. The high SVO signal on line 96 is fed back to AND gate 94 which at this time is receiving a low signal from CTL-SVO-CLR on line 84, and a low SVI-LCH signal on line 104, and the resulting high signal at the output terminal of AND gate 94 is communicated through OR gate 106 and to the input of Phase B latch 110, thus maintaining the present state of the SVO-ENA, SVO and DATA-ACC signals. At the leading edge of pulse 4A, a high SVI signal should appear on line 72. The SVI signal appears as a high SVI-LCH signal at the leading edge of pulse 4B. The SVI-LCH signal is communicated to AND gates 94, 100 and 132. The high SVI-LCH signal applied to AND gate 100 prevents SVO from being set by CTL-SVO-SET should this signal go high. Since CTL-SVO-SET is now low, the high SVI-LCH signal has no effect on AND gate 132 and the N-XFR-OK signal on line 148 remains low.

The high SVI-LCH signal produced at the leading edge of pulse 4B. as described above, is used also for clearing the SVO signal. The high SVI-LCH signal on line 104 disables AND gate 94, and the low signal appearing at the output terminal of AND gate 94 is communicated through OR gate 106 and then to the input of Phase B latch 110. Accordingly, at the leading edge of pulse 4B. SVO-ENA goes low, and this low signal is communicated at the leading edge of pulse 5A as a high DATA-ACC signal on line 23 and a low SVO signal on lines 71 and 96. The high DATA-ACC signal on line 23 indicates that the transfer has occurred (although it has not yet completed). Since DATA-ACC indicates that a transfer has occurred, CPU 4 will anticipate transfer completion during the next transfer request at the leading edge of pulse 6A. At the same time, the SVI signal on line 72 should go low. The low SVI signal is communicated through Phase B latch 124 so that a low SVI-LCH signal appears on line 104 at the leading edge of pulse 6B. At this time the high CTL-SVO-SET signal also should appear on line 86. This combination of signals at the input terminals of AND gate 100 produces a high signal which is communicated through OR gate 106 and Phase B latch 110 to appear as a high SVO-ENA signal 114 at the leading edge of pulse 7B. The high SVO-ENA signal is communicated through Phase A latches 118 and 119, and the operation proceeds as described above.

FIG. 6 is a timing diagram representing the operation of circuit 70 when a data transfer is inhibited. In FIG. 6, processing proceeds as in FIG. 5 and CPU 4 attempts another data transfer at the leading edge of pulse 6 A. However, the previous data transfer has not completed and the SVI signal did not go low at the leading edge of pulse 6A, possibly as a result of error correction steps taken by the controller, etc.. Consequently, a high SVI-LCH signal remains on line 104 at the leading edge of pulse 7A thus rendering AND gate 100 unresponsive to the high CTL-SVO-SET signal appearing on line 86. As a result. SVO-ENA and SVO remain low. At the same time, the high SVI-LCH signal coupled with the high CTL-SVO-SET signal at the input terminals of AND gate 132 produce a high signal which is propagated through OR gate 140 and to the input terminal of Phase B latch 144. At the leading edge of pulse 7B, a high N-XFR-OK signal appears on line 148, and this signal is communicated to NOR gate 120 and Phase A latch 150. At the leading edge of pulse 8A, the high N-XFR-OK-LCH signal appears on line 138 and the high N-XFR-OK signal appears as a low DATA-ACC signal on line 23. The high N-XFR-OK-LCH signal on line 138 coupled with the low CTL-CLR signal on line 90 produce a high signal at the output terminal of AND gate 134 for maintaining the high N-XFR-OK signal on line 148. Thus, when the CPU detects the low DATA-ACC signal on line 23 at the leading edge of pulse 11A, it knows that a previous data transfer was not completed properly. The CPU then may perform an error routine and either abort or retry the previous transfer or proceed with the next transfer. After the error is resolved. CPU 4 issues a CPU-XFR signal which sets CTL-CLR high to clear the high N-XFR-OK and N-XFR-OKLCH signals. Processing then resumes as under normal operation.

While the above is a complete description of a preferred embodiment of the present invention, various modifications are obvious to those skilled in the art. Consequently, the scope of the invention should not be limited except as properly described in the claims.